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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/sound/soc/ep93xx-i2s.c
4 * EP93xx I2S driver
5 *
6 * Copyright (C) 2010 Ryan Mallon
7 *
8 * Based on the original driver by:
9 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18
19#include <sound/core.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/initval.h>
24#include <sound/soc.h>
25
26#include <linux/platform_data/dma-ep93xx.h>
27#include <linux/soc/cirrus/ep93xx.h>
28
29#include "ep93xx-pcm.h"
30
31#define EP93XX_I2S_TXCLKCFG 0x00
32#define EP93XX_I2S_RXCLKCFG 0x04
33#define EP93XX_I2S_GLSTS 0x08
34#define EP93XX_I2S_GLCTRL 0x0C
35
36#define EP93XX_I2S_I2STX0LFT 0x10
37#define EP93XX_I2S_I2STX0RT 0x14
38
39#define EP93XX_I2S_TXLINCTRLDATA 0x28
40#define EP93XX_I2S_TXCTRL 0x2C
41#define EP93XX_I2S_TXWRDLEN 0x30
42#define EP93XX_I2S_TX0EN 0x34
43
44#define EP93XX_I2S_RXLINCTRLDATA 0x58
45#define EP93XX_I2S_RXCTRL 0x5C
46#define EP93XX_I2S_RXWRDLEN 0x60
47#define EP93XX_I2S_RX0EN 0x64
48
49#define EP93XX_I2S_WRDLEN_16 (0 << 0)
50#define EP93XX_I2S_WRDLEN_24 (1 << 0)
51#define EP93XX_I2S_WRDLEN_32 (2 << 0)
52
53#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
54
55#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
56
57/*
58 * Transmit empty interrupt level select:
59 * 0 - Generate interrupt when FIFO is half empty
60 * 1 - Generate interrupt when FIFO is empty
61 */
62#define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
63#define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
64
65#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
66#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
67#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
68#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
69#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
70
71#define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
72
73struct ep93xx_i2s_info {
74 struct clk *mclk;
75 struct clk *sclk;
76 struct clk *lrclk;
77 void __iomem *regs;
78 struct snd_dmaengine_dai_dma_data dma_params_rx;
79 struct snd_dmaengine_dai_dma_data dma_params_tx;
80};
81
82static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
83 [SNDRV_PCM_STREAM_PLAYBACK] = {
84 .name = "i2s-pcm-out",
85 .port = EP93XX_DMA_I2S1,
86 .direction = DMA_MEM_TO_DEV,
87 },
88 [SNDRV_PCM_STREAM_CAPTURE] = {
89 .name = "i2s-pcm-in",
90 .port = EP93XX_DMA_I2S1,
91 .direction = DMA_DEV_TO_MEM,
92 },
93};
94
95static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
96 unsigned reg, unsigned val)
97{
98 __raw_writel(val, info->regs + reg);
99}
100
101static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
102 unsigned reg)
103{
104 return __raw_readl(info->regs + reg);
105}
106
107static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
108{
109 unsigned base_reg;
110
111 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
112 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
113 /* Enable clocks */
114 clk_prepare_enable(info->mclk);
115 clk_prepare_enable(info->sclk);
116 clk_prepare_enable(info->lrclk);
117
118 /* Enable i2s */
119 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
120 }
121
122 /* Enable fifo */
123 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
124 base_reg = EP93XX_I2S_TX0EN;
125 else
126 base_reg = EP93XX_I2S_RX0EN;
127 ep93xx_i2s_write_reg(info, base_reg, 1);
128
129 /* Enable TX IRQs (FIFO empty or underflow) */
130 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
131 stream == SNDRV_PCM_STREAM_PLAYBACK)
132 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
133 EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
134 EP93XX_I2S_TXCTRL_TXUFIE);
135}
136
137static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
138{
139 unsigned base_reg;
140
141 /* Disable IRQs */
142 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
143 stream == SNDRV_PCM_STREAM_PLAYBACK)
144 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
145
146 /* Disable fifo */
147 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
148 base_reg = EP93XX_I2S_TX0EN;
149 else
150 base_reg = EP93XX_I2S_RX0EN;
151 ep93xx_i2s_write_reg(info, base_reg, 0);
152
153 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
154 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
155 /* Disable i2s */
156 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
157
158 /* Disable clocks */
159 clk_disable_unprepare(info->lrclk);
160 clk_disable_unprepare(info->sclk);
161 clk_disable_unprepare(info->mclk);
162 }
163}
164
165/*
166 * According to documentation I2S controller can handle underflow conditions
167 * just fine, but in reality the state machine is sometimes confused so that
168 * the whole stream is shifted by one byte. The watchdog below disables the TX
169 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
170 * is being reset and by filling the buffer we get some time before next
171 * underflow happens.
172 */
173static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
174{
175 struct ep93xx_i2s_info *info = dev_id;
176
177 /* Disable FIFO */
178 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
179 /*
180 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
181 * possible and get more time for DMA to catch up. Actually there are
182 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
183 * 1ms.
184 */
185 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
186 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
187 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
189 }
190 /* Re-enable FIFO */
191 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
192
193 return IRQ_HANDLED;
194}
195
196static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
197{
198 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
199
200 info->dma_params_tx.filter_data =
201 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
202 info->dma_params_rx.filter_data =
203 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
204
205 dai->playback_dma_data = &info->dma_params_tx;
206 dai->capture_dma_data = &info->dma_params_rx;
207
208 return 0;
209}
210
211static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
212 struct snd_soc_dai *dai)
213{
214 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
215
216 ep93xx_i2s_disable(info, substream->stream);
217}
218
219static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
220 unsigned int fmt)
221{
222 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
223 unsigned int clk_cfg;
224 unsigned int txlin_ctrl = 0;
225 unsigned int rxlin_ctrl = 0;
226
227 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
228
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_I2S:
231 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
232 break;
233
234 case SND_SOC_DAIFMT_LEFT_J:
235 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
236 break;
237
238 case SND_SOC_DAIFMT_RIGHT_J:
239 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
240 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
241 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
242 break;
243
244 default:
245 return -EINVAL;
246 }
247
248 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
249 case SND_SOC_DAIFMT_BP_FP:
250 /* CPU is provider */
251 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
252 break;
253
254 case SND_SOC_DAIFMT_BC_FC:
255 /* Codec is provider */
256 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
257 break;
258
259 default:
260 return -EINVAL;
261 }
262
263 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
264 case SND_SOC_DAIFMT_NB_NF:
265 /* Negative bit clock, lrclk low on left word */
266 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
267 break;
268
269 case SND_SOC_DAIFMT_NB_IF:
270 /* Negative bit clock, lrclk low on right word */
271 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
272 clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
273 break;
274
275 case SND_SOC_DAIFMT_IB_NF:
276 /* Positive bit clock, lrclk low on left word */
277 clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
278 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
279 break;
280
281 case SND_SOC_DAIFMT_IB_IF:
282 /* Positive bit clock, lrclk low on right word */
283 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
284 break;
285 }
286
287 /* Write new register values */
288 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
289 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
290 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
291 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
292 return 0;
293}
294
295static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
296 struct snd_pcm_hw_params *params,
297 struct snd_soc_dai *dai)
298{
299 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
300 unsigned word_len, div, sdiv, lrdiv;
301 int err;
302
303 switch (params_format(params)) {
304 case SNDRV_PCM_FORMAT_S16_LE:
305 word_len = EP93XX_I2S_WRDLEN_16;
306 break;
307
308 case SNDRV_PCM_FORMAT_S24_LE:
309 word_len = EP93XX_I2S_WRDLEN_24;
310 break;
311
312 case SNDRV_PCM_FORMAT_S32_LE:
313 word_len = EP93XX_I2S_WRDLEN_32;
314 break;
315
316 default:
317 return -EINVAL;
318 }
319
320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
321 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
322 else
323 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
324
325 /*
326 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
327 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
328 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
329 * value is 64, because our sample size is 32 bit * 2 channels.
330 * I2S standard permits us to transmit more bits than
331 * the codec uses.
332 */
333 div = clk_get_rate(info->mclk) / params_rate(params);
334 sdiv = 4;
335 if (div > (256 + 512) / 2) {
336 lrdiv = 128;
337 } else {
338 lrdiv = 64;
339 if (div < (128 + 256) / 2)
340 sdiv = 2;
341 }
342
343 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
344 if (err)
345 return err;
346
347 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
348 if (err)
349 return err;
350
351 ep93xx_i2s_enable(info, substream->stream);
352 return 0;
353}
354
355static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
356 unsigned int freq, int dir)
357{
358 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
359
360 if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
361 return -EINVAL;
362
363 return clk_set_rate(info->mclk, freq);
364}
365
366#ifdef CONFIG_PM
367static int ep93xx_i2s_suspend(struct snd_soc_component *component)
368{
369 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
370
371 if (!snd_soc_component_active(component))
372 return 0;
373
374 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
375 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
376
377 return 0;
378}
379
380static int ep93xx_i2s_resume(struct snd_soc_component *component)
381{
382 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
383
384 if (!snd_soc_component_active(component))
385 return 0;
386
387 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
388 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
389
390 return 0;
391}
392#else
393#define ep93xx_i2s_suspend NULL
394#define ep93xx_i2s_resume NULL
395#endif
396
397static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
398 .shutdown = ep93xx_i2s_shutdown,
399 .hw_params = ep93xx_i2s_hw_params,
400 .set_sysclk = ep93xx_i2s_set_sysclk,
401 .set_fmt = ep93xx_i2s_set_dai_fmt,
402};
403
404#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
405
406static struct snd_soc_dai_driver ep93xx_i2s_dai = {
407 .symmetric_rate = 1,
408 .probe = ep93xx_i2s_dai_probe,
409 .playback = {
410 .channels_min = 2,
411 .channels_max = 2,
412 .rates = SNDRV_PCM_RATE_8000_192000,
413 .formats = EP93XX_I2S_FORMATS,
414 },
415 .capture = {
416 .channels_min = 2,
417 .channels_max = 2,
418 .rates = SNDRV_PCM_RATE_8000_192000,
419 .formats = EP93XX_I2S_FORMATS,
420 },
421 .ops = &ep93xx_i2s_dai_ops,
422};
423
424static const struct snd_soc_component_driver ep93xx_i2s_component = {
425 .name = "ep93xx-i2s",
426 .suspend = ep93xx_i2s_suspend,
427 .resume = ep93xx_i2s_resume,
428 .legacy_dai_naming = 1,
429};
430
431static int ep93xx_i2s_probe(struct platform_device *pdev)
432{
433 struct ep93xx_i2s_info *info;
434 int err;
435
436 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
437 if (!info)
438 return -ENOMEM;
439
440 info->regs = devm_platform_ioremap_resource(pdev, 0);
441 if (IS_ERR(info->regs))
442 return PTR_ERR(info->regs);
443
444 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
445 int irq = platform_get_irq(pdev, 0);
446 if (irq <= 0)
447 return irq < 0 ? irq : -ENODEV;
448
449 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
450 pdev->name, info);
451 if (err)
452 return err;
453 }
454
455 info->mclk = clk_get(&pdev->dev, "mclk");
456 if (IS_ERR(info->mclk)) {
457 err = PTR_ERR(info->mclk);
458 goto fail;
459 }
460
461 info->sclk = clk_get(&pdev->dev, "sclk");
462 if (IS_ERR(info->sclk)) {
463 err = PTR_ERR(info->sclk);
464 goto fail_put_mclk;
465 }
466
467 info->lrclk = clk_get(&pdev->dev, "lrclk");
468 if (IS_ERR(info->lrclk)) {
469 err = PTR_ERR(info->lrclk);
470 goto fail_put_sclk;
471 }
472
473 dev_set_drvdata(&pdev->dev, info);
474
475 err = devm_snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
476 &ep93xx_i2s_dai, 1);
477 if (err)
478 goto fail_put_lrclk;
479
480 err = devm_ep93xx_pcm_platform_register(&pdev->dev);
481 if (err)
482 goto fail_put_lrclk;
483
484 return 0;
485
486fail_put_lrclk:
487 clk_put(info->lrclk);
488fail_put_sclk:
489 clk_put(info->sclk);
490fail_put_mclk:
491 clk_put(info->mclk);
492fail:
493 return err;
494}
495
496static int ep93xx_i2s_remove(struct platform_device *pdev)
497{
498 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
499
500 clk_put(info->lrclk);
501 clk_put(info->sclk);
502 clk_put(info->mclk);
503 return 0;
504}
505
506static struct platform_driver ep93xx_i2s_driver = {
507 .probe = ep93xx_i2s_probe,
508 .remove = ep93xx_i2s_remove,
509 .driver = {
510 .name = "ep93xx-i2s",
511 },
512};
513
514module_platform_driver(ep93xx_i2s_driver);
515
516MODULE_ALIAS("platform:ep93xx-i2s");
517MODULE_AUTHOR("Ryan Mallon");
518MODULE_DESCRIPTION("EP93XX I2S driver");
519MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/sound/soc/ep93xx-i2s.c
4 * EP93xx I2S driver
5 *
6 * Copyright (C) 2010 Ryan Mallon
7 *
8 * Based on the original driver by:
9 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18
19#include <sound/core.h>
20#include <sound/dmaengine_pcm.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/initval.h>
24#include <sound/soc.h>
25
26#include <linux/platform_data/dma-ep93xx.h>
27#include <linux/soc/cirrus/ep93xx.h>
28
29#include "ep93xx-pcm.h"
30
31#define EP93XX_I2S_TXCLKCFG 0x00
32#define EP93XX_I2S_RXCLKCFG 0x04
33#define EP93XX_I2S_GLSTS 0x08
34#define EP93XX_I2S_GLCTRL 0x0C
35
36#define EP93XX_I2S_I2STX0LFT 0x10
37#define EP93XX_I2S_I2STX0RT 0x14
38
39#define EP93XX_I2S_TXLINCTRLDATA 0x28
40#define EP93XX_I2S_TXCTRL 0x2C
41#define EP93XX_I2S_TXWRDLEN 0x30
42#define EP93XX_I2S_TX0EN 0x34
43
44#define EP93XX_I2S_RXLINCTRLDATA 0x58
45#define EP93XX_I2S_RXCTRL 0x5C
46#define EP93XX_I2S_RXWRDLEN 0x60
47#define EP93XX_I2S_RX0EN 0x64
48
49#define EP93XX_I2S_WRDLEN_16 (0 << 0)
50#define EP93XX_I2S_WRDLEN_24 (1 << 0)
51#define EP93XX_I2S_WRDLEN_32 (2 << 0)
52
53#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
54
55#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
56
57/*
58 * Transmit empty interrupt level select:
59 * 0 - Generate interrupt when FIFO is half empty
60 * 1 - Generate interrupt when FIFO is empty
61 */
62#define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
63#define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
64
65#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
66#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
67#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
68#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
69#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
70
71#define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
72
73struct ep93xx_i2s_info {
74 struct clk *mclk;
75 struct clk *sclk;
76 struct clk *lrclk;
77 void __iomem *regs;
78 struct snd_dmaengine_dai_dma_data dma_params_rx;
79 struct snd_dmaengine_dai_dma_data dma_params_tx;
80};
81
82static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
83 [SNDRV_PCM_STREAM_PLAYBACK] = {
84 .name = "i2s-pcm-out",
85 .port = EP93XX_DMA_I2S1,
86 .direction = DMA_MEM_TO_DEV,
87 },
88 [SNDRV_PCM_STREAM_CAPTURE] = {
89 .name = "i2s-pcm-in",
90 .port = EP93XX_DMA_I2S1,
91 .direction = DMA_DEV_TO_MEM,
92 },
93};
94
95static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
96 unsigned reg, unsigned val)
97{
98 __raw_writel(val, info->regs + reg);
99}
100
101static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
102 unsigned reg)
103{
104 return __raw_readl(info->regs + reg);
105}
106
107static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
108{
109 unsigned base_reg;
110
111 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
112 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
113 /* Enable clocks */
114 clk_enable(info->mclk);
115 clk_enable(info->sclk);
116 clk_enable(info->lrclk);
117
118 /* Enable i2s */
119 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
120 }
121
122 /* Enable fifo */
123 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
124 base_reg = EP93XX_I2S_TX0EN;
125 else
126 base_reg = EP93XX_I2S_RX0EN;
127 ep93xx_i2s_write_reg(info, base_reg, 1);
128
129 /* Enable TX IRQs (FIFO empty or underflow) */
130 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
131 stream == SNDRV_PCM_STREAM_PLAYBACK)
132 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
133 EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
134 EP93XX_I2S_TXCTRL_TXUFIE);
135}
136
137static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
138{
139 unsigned base_reg;
140
141 /* Disable IRQs */
142 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
143 stream == SNDRV_PCM_STREAM_PLAYBACK)
144 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
145
146 /* Disable fifo */
147 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
148 base_reg = EP93XX_I2S_TX0EN;
149 else
150 base_reg = EP93XX_I2S_RX0EN;
151 ep93xx_i2s_write_reg(info, base_reg, 0);
152
153 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
154 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
155 /* Disable i2s */
156 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
157
158 /* Disable clocks */
159 clk_disable(info->lrclk);
160 clk_disable(info->sclk);
161 clk_disable(info->mclk);
162 }
163}
164
165/*
166 * According to documentation I2S controller can handle underflow conditions
167 * just fine, but in reality the state machine is sometimes confused so that
168 * the whole stream is shifted by one byte. The watchdog below disables the TX
169 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
170 * is being reset and by filling the buffer we get some time before next
171 * underflow happens.
172 */
173static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
174{
175 struct ep93xx_i2s_info *info = dev_id;
176
177 /* Disable FIFO */
178 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
179 /*
180 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
181 * possible and get more time for DMA to catch up. Actually there are
182 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
183 * 1ms.
184 */
185 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
186 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
187 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
189 }
190 /* Re-enable FIFO */
191 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
192
193 return IRQ_HANDLED;
194}
195
196static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
197{
198 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
199
200 info->dma_params_tx.filter_data =
201 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
202 info->dma_params_rx.filter_data =
203 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
204
205 dai->playback_dma_data = &info->dma_params_tx;
206 dai->capture_dma_data = &info->dma_params_rx;
207
208 return 0;
209}
210
211static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
212 struct snd_soc_dai *dai)
213{
214 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
215
216 ep93xx_i2s_disable(info, substream->stream);
217}
218
219static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
220 unsigned int fmt)
221{
222 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
223 unsigned int clk_cfg;
224 unsigned int txlin_ctrl = 0;
225 unsigned int rxlin_ctrl = 0;
226
227 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
228
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_I2S:
231 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
232 break;
233
234 case SND_SOC_DAIFMT_LEFT_J:
235 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
236 break;
237
238 case SND_SOC_DAIFMT_RIGHT_J:
239 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
240 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
241 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
242 break;
243
244 default:
245 return -EINVAL;
246 }
247
248 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249 case SND_SOC_DAIFMT_CBS_CFS:
250 /* CPU is master */
251 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
252 break;
253
254 case SND_SOC_DAIFMT_CBM_CFM:
255 /* Codec is master */
256 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
257 break;
258
259 default:
260 return -EINVAL;
261 }
262
263 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
264 case SND_SOC_DAIFMT_NB_NF:
265 /* Negative bit clock, lrclk low on left word */
266 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
267 break;
268
269 case SND_SOC_DAIFMT_NB_IF:
270 /* Negative bit clock, lrclk low on right word */
271 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
272 clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
273 break;
274
275 case SND_SOC_DAIFMT_IB_NF:
276 /* Positive bit clock, lrclk low on left word */
277 clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
278 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
279 break;
280
281 case SND_SOC_DAIFMT_IB_IF:
282 /* Positive bit clock, lrclk low on right word */
283 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
284 break;
285 }
286
287 /* Write new register values */
288 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
289 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
290 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
291 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
292 return 0;
293}
294
295static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
296 struct snd_pcm_hw_params *params,
297 struct snd_soc_dai *dai)
298{
299 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
300 unsigned word_len, div, sdiv, lrdiv;
301 int err;
302
303 switch (params_format(params)) {
304 case SNDRV_PCM_FORMAT_S16_LE:
305 word_len = EP93XX_I2S_WRDLEN_16;
306 break;
307
308 case SNDRV_PCM_FORMAT_S24_LE:
309 word_len = EP93XX_I2S_WRDLEN_24;
310 break;
311
312 case SNDRV_PCM_FORMAT_S32_LE:
313 word_len = EP93XX_I2S_WRDLEN_32;
314 break;
315
316 default:
317 return -EINVAL;
318 }
319
320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
321 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
322 else
323 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
324
325 /*
326 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
327 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
328 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
329 * value is 64, because our sample size is 32 bit * 2 channels.
330 * I2S standard permits us to transmit more bits than
331 * the codec uses.
332 */
333 div = clk_get_rate(info->mclk) / params_rate(params);
334 sdiv = 4;
335 if (div > (256 + 512) / 2) {
336 lrdiv = 128;
337 } else {
338 lrdiv = 64;
339 if (div < (128 + 256) / 2)
340 sdiv = 2;
341 }
342
343 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
344 if (err)
345 return err;
346
347 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
348 if (err)
349 return err;
350
351 ep93xx_i2s_enable(info, substream->stream);
352 return 0;
353}
354
355static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
356 unsigned int freq, int dir)
357{
358 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
359
360 if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
361 return -EINVAL;
362
363 return clk_set_rate(info->mclk, freq);
364}
365
366#ifdef CONFIG_PM
367static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
368{
369 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
370
371 if (!dai->active)
372 return 0;
373
374 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
375 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
376
377 return 0;
378}
379
380static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
381{
382 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
383
384 if (!dai->active)
385 return 0;
386
387 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
388 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
389
390 return 0;
391}
392#else
393#define ep93xx_i2s_suspend NULL
394#define ep93xx_i2s_resume NULL
395#endif
396
397static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
398 .shutdown = ep93xx_i2s_shutdown,
399 .hw_params = ep93xx_i2s_hw_params,
400 .set_sysclk = ep93xx_i2s_set_sysclk,
401 .set_fmt = ep93xx_i2s_set_dai_fmt,
402};
403
404#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
405
406static struct snd_soc_dai_driver ep93xx_i2s_dai = {
407 .symmetric_rates= 1,
408 .probe = ep93xx_i2s_dai_probe,
409 .suspend = ep93xx_i2s_suspend,
410 .resume = ep93xx_i2s_resume,
411 .playback = {
412 .channels_min = 2,
413 .channels_max = 2,
414 .rates = SNDRV_PCM_RATE_8000_192000,
415 .formats = EP93XX_I2S_FORMATS,
416 },
417 .capture = {
418 .channels_min = 2,
419 .channels_max = 2,
420 .rates = SNDRV_PCM_RATE_8000_192000,
421 .formats = EP93XX_I2S_FORMATS,
422 },
423 .ops = &ep93xx_i2s_dai_ops,
424};
425
426static const struct snd_soc_component_driver ep93xx_i2s_component = {
427 .name = "ep93xx-i2s",
428};
429
430static int ep93xx_i2s_probe(struct platform_device *pdev)
431{
432 struct ep93xx_i2s_info *info;
433 int err;
434
435 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
436 if (!info)
437 return -ENOMEM;
438
439 info->regs = devm_platform_ioremap_resource(pdev, 0);
440 if (IS_ERR(info->regs))
441 return PTR_ERR(info->regs);
442
443 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
444 int irq = platform_get_irq(pdev, 0);
445 if (irq <= 0)
446 return irq < 0 ? irq : -ENODEV;
447
448 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
449 pdev->name, info);
450 if (err)
451 return err;
452 }
453
454 info->mclk = clk_get(&pdev->dev, "mclk");
455 if (IS_ERR(info->mclk)) {
456 err = PTR_ERR(info->mclk);
457 goto fail;
458 }
459
460 info->sclk = clk_get(&pdev->dev, "sclk");
461 if (IS_ERR(info->sclk)) {
462 err = PTR_ERR(info->sclk);
463 goto fail_put_mclk;
464 }
465
466 info->lrclk = clk_get(&pdev->dev, "lrclk");
467 if (IS_ERR(info->lrclk)) {
468 err = PTR_ERR(info->lrclk);
469 goto fail_put_sclk;
470 }
471
472 dev_set_drvdata(&pdev->dev, info);
473
474 err = devm_snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
475 &ep93xx_i2s_dai, 1);
476 if (err)
477 goto fail_put_lrclk;
478
479 err = devm_ep93xx_pcm_platform_register(&pdev->dev);
480 if (err)
481 goto fail_put_lrclk;
482
483 return 0;
484
485fail_put_lrclk:
486 clk_put(info->lrclk);
487fail_put_sclk:
488 clk_put(info->sclk);
489fail_put_mclk:
490 clk_put(info->mclk);
491fail:
492 return err;
493}
494
495static int ep93xx_i2s_remove(struct platform_device *pdev)
496{
497 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
498
499 clk_put(info->lrclk);
500 clk_put(info->sclk);
501 clk_put(info->mclk);
502 return 0;
503}
504
505static struct platform_driver ep93xx_i2s_driver = {
506 .probe = ep93xx_i2s_probe,
507 .remove = ep93xx_i2s_remove,
508 .driver = {
509 .name = "ep93xx-i2s",
510 },
511};
512
513module_platform_driver(ep93xx_i2s_driver);
514
515MODULE_ALIAS("platform:ep93xx-i2s");
516MODULE_AUTHOR("Ryan Mallon");
517MODULE_DESCRIPTION("EP93XX I2S driver");
518MODULE_LICENSE("GPL");