1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
 4 */
 5
 6#ifndef DT_CLOCK_OXSEMI_OX820_H
 7#define DT_CLOCK_OXSEMI_OX820_H
 8
 9/* PLLs */
10#define CLK_820_PLLA		0
11#define CLK_820_PLLB		1
12
13/* Gate Clocks */
14#define CLK_820_LEON		2
15#define CLK_820_DMA_SGDMA	3
16#define CLK_820_CIPHER		4
17#define CLK_820_SD		5
18#define CLK_820_SATA		6
19#define CLK_820_AUDIO		7
20#define CLK_820_USBMPH		8
21#define CLK_820_ETHA		9
22#define CLK_820_PCIEA		10
23#define CLK_820_NAND		11
24#define CLK_820_PCIEB		12
25#define CLK_820_ETHB		13
26#define CLK_820_REF600		14
27#define CLK_820_USBDEV		15
28
29#endif /* DT_CLOCK_OXSEMI_OX820_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
 4 */
 5
 6#ifndef DT_CLOCK_OXSEMI_OX820_H
 7#define DT_CLOCK_OXSEMI_OX820_H
 8
 9/* PLLs */
10#define CLK_820_PLLA		0
11#define CLK_820_PLLB		1
12
13/* Gate Clocks */
14#define CLK_820_LEON		2
15#define CLK_820_DMA_SGDMA	3
16#define CLK_820_CIPHER		4
17#define CLK_820_SD		5
18#define CLK_820_SATA		6
19#define CLK_820_AUDIO		7
20#define CLK_820_USBMPH		8
21#define CLK_820_ETHA		9
22#define CLK_820_PCIEA		10
23#define CLK_820_NAND		11
24#define CLK_820_PCIEB		12
25#define CLK_820_ETHB		13
26#define CLK_820_REF600		14
27#define CLK_820_USBDEV		15
28
29#endif /* DT_CLOCK_OXSEMI_OX820_H */