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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 */
5
6#ifndef __DT_BINDINGS_CLOCK_IMX21_H
7#define __DT_BINDINGS_CLOCK_IMX21_H
8
9#define IMX21_CLK_DUMMY 0
10#define IMX21_CLK_CKIL 1
11#define IMX21_CLK_CKIH 2
12#define IMX21_CLK_FPM 3
13#define IMX21_CLK_CKIH_DIV1P5 4
14#define IMX21_CLK_MPLL_GATE 5
15#define IMX21_CLK_SPLL_GATE 6
16#define IMX21_CLK_FPM_GATE 7
17#define IMX21_CLK_CKIH_GATE 8
18#define IMX21_CLK_MPLL_OSC_SEL 9
19#define IMX21_CLK_IPG 10
20#define IMX21_CLK_HCLK 11
21#define IMX21_CLK_MPLL_SEL 12
22#define IMX21_CLK_SPLL_SEL 13
23#define IMX21_CLK_SSI1_SEL 14
24#define IMX21_CLK_SSI2_SEL 15
25#define IMX21_CLK_USB_DIV 16
26#define IMX21_CLK_FCLK 17
27#define IMX21_CLK_MPLL 18
28#define IMX21_CLK_SPLL 19
29#define IMX21_CLK_NFC_DIV 20
30#define IMX21_CLK_SSI1_DIV 21
31#define IMX21_CLK_SSI2_DIV 22
32#define IMX21_CLK_PER1 23
33#define IMX21_CLK_PER2 24
34#define IMX21_CLK_PER3 25
35#define IMX21_CLK_PER4 26
36#define IMX21_CLK_UART1_IPG_GATE 27
37#define IMX21_CLK_UART2_IPG_GATE 28
38#define IMX21_CLK_UART3_IPG_GATE 29
39#define IMX21_CLK_UART4_IPG_GATE 30
40#define IMX21_CLK_CSPI1_IPG_GATE 31
41#define IMX21_CLK_CSPI2_IPG_GATE 32
42#define IMX21_CLK_SSI1_GATE 33
43#define IMX21_CLK_SSI2_GATE 34
44#define IMX21_CLK_SDHC1_IPG_GATE 35
45#define IMX21_CLK_SDHC2_IPG_GATE 36
46#define IMX21_CLK_GPIO_GATE 37
47#define IMX21_CLK_I2C_GATE 38
48#define IMX21_CLK_DMA_GATE 39
49#define IMX21_CLK_USB_GATE 40
50#define IMX21_CLK_EMMA_GATE 41
51#define IMX21_CLK_SSI2_BAUD_GATE 42
52#define IMX21_CLK_SSI1_BAUD_GATE 43
53#define IMX21_CLK_LCDC_IPG_GATE 44
54#define IMX21_CLK_NFC_GATE 45
55#define IMX21_CLK_LCDC_HCLK_GATE 46
56#define IMX21_CLK_PER4_GATE 47
57#define IMX21_CLK_BMI_GATE 48
58#define IMX21_CLK_USB_HCLK_GATE 49
59#define IMX21_CLK_SLCDC_GATE 50
60#define IMX21_CLK_SLCDC_HCLK_GATE 51
61#define IMX21_CLK_EMMA_HCLK_GATE 52
62#define IMX21_CLK_BROM_GATE 53
63#define IMX21_CLK_DMA_HCLK_GATE 54
64#define IMX21_CLK_CSI_HCLK_GATE 55
65#define IMX21_CLK_CSPI3_IPG_GATE 56
66#define IMX21_CLK_WDOG_GATE 57
67#define IMX21_CLK_GPT1_IPG_GATE 58
68#define IMX21_CLK_GPT2_IPG_GATE 59
69#define IMX21_CLK_GPT3_IPG_GATE 60
70#define IMX21_CLK_PWM_IPG_GATE 61
71#define IMX21_CLK_RTC_GATE 62
72#define IMX21_CLK_KPP_GATE 63
73#define IMX21_CLK_OWIRE_GATE 64
74#define IMX21_CLK_MAX 65
75
76#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 */
5
6#ifndef __DT_BINDINGS_CLOCK_IMX21_H
7#define __DT_BINDINGS_CLOCK_IMX21_H
8
9#define IMX21_CLK_DUMMY 0
10#define IMX21_CLK_CKIL 1
11#define IMX21_CLK_CKIH 2
12#define IMX21_CLK_FPM 3
13#define IMX21_CLK_CKIH_DIV1P5 4
14#define IMX21_CLK_MPLL_GATE 5
15#define IMX21_CLK_SPLL_GATE 6
16#define IMX21_CLK_FPM_GATE 7
17#define IMX21_CLK_CKIH_GATE 8
18#define IMX21_CLK_MPLL_OSC_SEL 9
19#define IMX21_CLK_IPG 10
20#define IMX21_CLK_HCLK 11
21#define IMX21_CLK_MPLL_SEL 12
22#define IMX21_CLK_SPLL_SEL 13
23#define IMX21_CLK_SSI1_SEL 14
24#define IMX21_CLK_SSI2_SEL 15
25#define IMX21_CLK_USB_DIV 16
26#define IMX21_CLK_FCLK 17
27#define IMX21_CLK_MPLL 18
28#define IMX21_CLK_SPLL 19
29#define IMX21_CLK_NFC_DIV 20
30#define IMX21_CLK_SSI1_DIV 21
31#define IMX21_CLK_SSI2_DIV 22
32#define IMX21_CLK_PER1 23
33#define IMX21_CLK_PER2 24
34#define IMX21_CLK_PER3 25
35#define IMX21_CLK_PER4 26
36#define IMX21_CLK_UART1_IPG_GATE 27
37#define IMX21_CLK_UART2_IPG_GATE 28
38#define IMX21_CLK_UART3_IPG_GATE 29
39#define IMX21_CLK_UART4_IPG_GATE 30
40#define IMX21_CLK_CSPI1_IPG_GATE 31
41#define IMX21_CLK_CSPI2_IPG_GATE 32
42#define IMX21_CLK_SSI1_GATE 33
43#define IMX21_CLK_SSI2_GATE 34
44#define IMX21_CLK_SDHC1_IPG_GATE 35
45#define IMX21_CLK_SDHC2_IPG_GATE 36
46#define IMX21_CLK_GPIO_GATE 37
47#define IMX21_CLK_I2C_GATE 38
48#define IMX21_CLK_DMA_GATE 39
49#define IMX21_CLK_USB_GATE 40
50#define IMX21_CLK_EMMA_GATE 41
51#define IMX21_CLK_SSI2_BAUD_GATE 42
52#define IMX21_CLK_SSI1_BAUD_GATE 43
53#define IMX21_CLK_LCDC_IPG_GATE 44
54#define IMX21_CLK_NFC_GATE 45
55#define IMX21_CLK_LCDC_HCLK_GATE 46
56#define IMX21_CLK_PER4_GATE 47
57#define IMX21_CLK_BMI_GATE 48
58#define IMX21_CLK_USB_HCLK_GATE 49
59#define IMX21_CLK_SLCDC_GATE 50
60#define IMX21_CLK_SLCDC_HCLK_GATE 51
61#define IMX21_CLK_EMMA_HCLK_GATE 52
62#define IMX21_CLK_BROM_GATE 53
63#define IMX21_CLK_DMA_HCLK_GATE 54
64#define IMX21_CLK_CSI_HCLK_GATE 55
65#define IMX21_CLK_CSPI3_IPG_GATE 56
66#define IMX21_CLK_WDOG_GATE 57
67#define IMX21_CLK_GPT1_IPG_GATE 58
68#define IMX21_CLK_GPT2_IPG_GATE 59
69#define IMX21_CLK_GPT3_IPG_GATE 60
70#define IMX21_CLK_PWM_IPG_GATE 61
71#define IMX21_CLK_RTC_GATE 62
72#define IMX21_CLK_KPP_GATE 63
73#define IMX21_CLK_OWIRE_GATE 64
74#define IMX21_CLK_MAX 65
75
76#endif