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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright (C) 2017 Google, Inc.
4 *
5 * Authors:
6 * Sean Paul <seanpaul@chromium.org>
7 */
8
9#ifndef _DRM_HDCP_H_INCLUDED_
10#define _DRM_HDCP_H_INCLUDED_
11
12#include <linux/types.h>
13
14/* Period of hdcp checks (to ensure we're still authenticated) */
15#define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
16#define DRM_HDCP2_CHECK_PERIOD_MS 500
17
18/* Shared lengths/masks between HDMI/DVI/DisplayPort */
19#define DRM_HDCP_AN_LEN 8
20#define DRM_HDCP_BSTATUS_LEN 2
21#define DRM_HDCP_KSV_LEN 5
22#define DRM_HDCP_RI_LEN 2
23#define DRM_HDCP_V_PRIME_PART_LEN 4
24#define DRM_HDCP_V_PRIME_NUM_PARTS 5
25#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
26#define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
27#define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
28
29/* Slave address for the HDCP registers in the receiver */
30#define DRM_HDCP_DDC_ADDR 0x3A
31
32/* HDCP register offsets for HDMI/DVI devices */
33#define DRM_HDCP_DDC_BKSV 0x00
34#define DRM_HDCP_DDC_RI_PRIME 0x08
35#define DRM_HDCP_DDC_AKSV 0x10
36#define DRM_HDCP_DDC_AN 0x18
37#define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
38#define DRM_HDCP_DDC_BCAPS 0x40
39#define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
40#define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
41#define DRM_HDCP_DDC_BSTATUS 0x41
42#define DRM_HDCP_DDC_KSV_FIFO 0x43
43
44#define DRM_HDCP_1_4_SRM_ID 0x8
45#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
46#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
47
48/* Protocol message definition for HDCP2.2 specification */
49/*
50 * Protected content streams are classified into 2 types:
51 * - Type0: Can be transmitted with HDCP 1.4+
52 * - Type1: Can be transmitted with HDCP 2.2+
53 */
54#define HDCP_STREAM_TYPE0 0x00
55#define HDCP_STREAM_TYPE1 0x01
56
57/* HDCP2.2 Msg IDs */
58#define HDCP_2_2_NULL_MSG 1
59#define HDCP_2_2_AKE_INIT 2
60#define HDCP_2_2_AKE_SEND_CERT 3
61#define HDCP_2_2_AKE_NO_STORED_KM 4
62#define HDCP_2_2_AKE_STORED_KM 5
63#define HDCP_2_2_AKE_SEND_HPRIME 7
64#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
65#define HDCP_2_2_LC_INIT 9
66#define HDCP_2_2_LC_SEND_LPRIME 10
67#define HDCP_2_2_SKE_SEND_EKS 11
68#define HDCP_2_2_REP_SEND_RECVID_LIST 12
69#define HDCP_2_2_REP_SEND_ACK 15
70#define HDCP_2_2_REP_STREAM_MANAGE 16
71#define HDCP_2_2_REP_STREAM_READY 17
72
73#define HDCP_2_2_RTX_LEN 8
74#define HDCP_2_2_RRX_LEN 8
75
76#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
77#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
78#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
79 HDCP_2_2_K_PUB_RX_EXP_E_LEN)
80
81#define HDCP_2_2_DCP_LLC_SIG_LEN 384
82
83#define HDCP_2_2_E_KPUB_KM_LEN 128
84#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
85#define HDCP_2_2_H_PRIME_LEN 32
86#define HDCP_2_2_E_KH_KM_LEN 16
87#define HDCP_2_2_RN_LEN 8
88#define HDCP_2_2_L_PRIME_LEN 32
89#define HDCP_2_2_E_DKEY_KS_LEN 16
90#define HDCP_2_2_RIV_LEN 8
91#define HDCP_2_2_SEQ_NUM_LEN 3
92#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
93#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
94#define HDCP_2_2_MAX_DEVICE_COUNT 31
95#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
96 HDCP_2_2_MAX_DEVICE_COUNT)
97#define HDCP_2_2_MPRIME_LEN 32
98
99/* Following Macros take a byte at a time for bit(s) masking */
100/*
101 * TODO: This has to be changed for DP MST, as multiple stream on
102 * same port is possible.
103 * For HDCP2.2 on HDMI and DP SST this value is always 1.
104 */
105#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
106#define HDCP_2_2_TXCAP_MASK_LEN 2
107#define HDCP_2_2_RXCAPS_LEN 3
108#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
109#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
110#define HDCP_2_2_RXINFO_LEN 2
111
112/* HDCP1.x compliant device in downstream */
113#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
114
115/* HDCP2.0 Compliant repeater in downstream */
116#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
117#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
118#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
119#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
120#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
121#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
122
123struct hdcp2_cert_rx {
124 u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
125 u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
126 u8 reserved[2];
127 u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
128} __packed;
129
130struct hdcp2_streamid_type {
131 u8 stream_id;
132 u8 stream_type;
133} __packed;
134
135/*
136 * The TxCaps field specified in the HDCP HDMI, DP specs
137 * This field is big endian as specified in the errata.
138 */
139struct hdcp2_tx_caps {
140 /* Transmitter must set this to 0x2 */
141 u8 version;
142
143 /* Reserved for HDCP and DP Spec. Read as Zero */
144 u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
145} __packed;
146
147/* Main structures for HDCP2.2 protocol communication */
148struct hdcp2_ake_init {
149 u8 msg_id;
150 u8 r_tx[HDCP_2_2_RTX_LEN];
151 struct hdcp2_tx_caps tx_caps;
152} __packed;
153
154struct hdcp2_ake_send_cert {
155 u8 msg_id;
156 struct hdcp2_cert_rx cert_rx;
157 u8 r_rx[HDCP_2_2_RRX_LEN];
158 u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
159} __packed;
160
161struct hdcp2_ake_no_stored_km {
162 u8 msg_id;
163 u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
164} __packed;
165
166struct hdcp2_ake_stored_km {
167 u8 msg_id;
168 u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
169} __packed;
170
171struct hdcp2_ake_send_hprime {
172 u8 msg_id;
173 u8 h_prime[HDCP_2_2_H_PRIME_LEN];
174} __packed;
175
176struct hdcp2_ake_send_pairing_info {
177 u8 msg_id;
178 u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
179} __packed;
180
181struct hdcp2_lc_init {
182 u8 msg_id;
183 u8 r_n[HDCP_2_2_RN_LEN];
184} __packed;
185
186struct hdcp2_lc_send_lprime {
187 u8 msg_id;
188 u8 l_prime[HDCP_2_2_L_PRIME_LEN];
189} __packed;
190
191struct hdcp2_ske_send_eks {
192 u8 msg_id;
193 u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
194 u8 riv[HDCP_2_2_RIV_LEN];
195} __packed;
196
197struct hdcp2_rep_send_receiverid_list {
198 u8 msg_id;
199 u8 rx_info[HDCP_2_2_RXINFO_LEN];
200 u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
201 u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
202 u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
203} __packed;
204
205struct hdcp2_rep_send_ack {
206 u8 msg_id;
207 u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
208} __packed;
209
210struct hdcp2_rep_stream_manage {
211 u8 msg_id;
212 u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
213 __be16 k;
214 struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
215} __packed;
216
217struct hdcp2_rep_stream_ready {
218 u8 msg_id;
219 u8 m_prime[HDCP_2_2_MPRIME_LEN];
220} __packed;
221
222/* HDCP2.2 TIMEOUTs in mSec */
223#define HDCP_2_2_CERT_TIMEOUT_MS 100
224#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
225#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
226#define HDCP_2_2_PAIRING_TIMEOUT_MS 200
227#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
228#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
229#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
230#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
231
232/* HDMI HDCP2.2 Register Offsets */
233#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
234#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
235#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
236#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
237#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
238
239#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
240#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
241#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
242#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
243
244/* Below macros take a byte at a time and mask the bit(s) */
245#define HDCP_2_2_HDMI_RXSTATUS_LEN 2
246#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
247#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
248#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
249
250/*
251 * Helper functions to convert 24bit big endian hdcp sequence number to
252 * host format and back
253 */
254static inline
255u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
256{
257 return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
258}
259
260static inline
261void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
262{
263 seq_num[0] = val >> 16;
264 seq_num[1] = val >> 8;
265 seq_num[2] = val;
266}
267
268#define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024)
269#define DRM_HDCP_1_4_SRM_ID 0x8
270#define DRM_HDCP_SRM_ID_MASK (0xF << 4)
271#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
272#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
273#define DRM_HDCP_2_SRM_ID 0x9
274#define DRM_HDCP_2_INDICATOR 0x1
275#define DRM_HDCP_2_INDICATOR_MASK 0xF
276#define DRM_HDCP_2_VRL_LENGTH_SIZE 3
277#define DRM_HDCP_2_DCP_SIG_SIZE 384
278#define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4
279#define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC) >> 6)
280
281struct hdcp_srm_header {
282 u8 srm_id;
283 u8 reserved;
284 __be16 srm_version;
285 u8 srm_gen_no;
286} __packed;
287
288struct drm_device;
289struct drm_connector;
290
291bool drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
292 u8 *ksvs, u32 ksv_count);
293int drm_connector_attach_content_protection_property(
294 struct drm_connector *connector, bool hdcp_content_type);
295void drm_hdcp_update_content_protection(struct drm_connector *connector,
296 u64 val);
297
298/* Content Type classification for HDCP2.2 vs others */
299#define DRM_MODE_HDCP_CONTENT_TYPE0 0
300#define DRM_MODE_HDCP_CONTENT_TYPE1 1
301
302#endif