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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * platform.c - DesignWare HS OTG Controller platform driver
4 *
5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/slab.h>
11#include <linux/clk.h>
12#include <linux/device.h>
13#include <linux/dma-mapping.h>
14#include <linux/of_device.h>
15#include <linux/mutex.h>
16#include <linux/platform_device.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_data/s3c-hsotg.h>
19#include <linux/reset.h>
20
21#include <linux/usb/of.h>
22
23#include "core.h"
24#include "hcd.h"
25#include "debug.h"
26
27static const char dwc2_driver_name[] = "dwc2";
28
29/*
30 * Check the dr_mode against the module configuration and hardware
31 * capabilities.
32 *
33 * The hardware, module, and dr_mode, can each be set to host, device,
34 * or otg. Check that all these values are compatible and adjust the
35 * value of dr_mode if possible.
36 *
37 * actual
38 * HW MOD dr_mode dr_mode
39 * ------------------------------
40 * HST HST any : HST
41 * HST DEV any : ---
42 * HST OTG any : HST
43 *
44 * DEV HST any : ---
45 * DEV DEV any : DEV
46 * DEV OTG any : DEV
47 *
48 * OTG HST any : HST
49 * OTG DEV any : DEV
50 * OTG OTG any : dr_mode
51 */
52static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
53{
54 enum usb_dr_mode mode;
55
56 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
57 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
58 hsotg->dr_mode = USB_DR_MODE_OTG;
59
60 mode = hsotg->dr_mode;
61
62 if (dwc2_hw_is_device(hsotg)) {
63 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
64 dev_err(hsotg->dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 } else if (dwc2_hw_is_host(hsotg)) {
70 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
71 dev_err(hsotg->dev,
72 "Controller does not support device mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_HOST;
76 } else {
77 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
80 mode = USB_DR_MODE_PERIPHERAL;
81 }
82
83 if (mode != hsotg->dr_mode) {
84 dev_warn(hsotg->dev,
85 "Configuration mismatch. dr_mode forced to %s\n",
86 mode == USB_DR_MODE_HOST ? "host" : "device");
87
88 hsotg->dr_mode = mode;
89 }
90
91 return 0;
92}
93
94static void __dwc2_disable_regulators(void *data)
95{
96 struct dwc2_hsotg *hsotg = data;
97
98 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
99}
100
101static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
102{
103 struct platform_device *pdev = to_platform_device(hsotg->dev);
104 int ret;
105
106 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
107 hsotg->supplies);
108 if (ret)
109 return ret;
110
111 ret = devm_add_action_or_reset(&pdev->dev,
112 __dwc2_disable_regulators, hsotg);
113 if (ret)
114 return ret;
115
116 if (hsotg->clk) {
117 ret = clk_prepare_enable(hsotg->clk);
118 if (ret)
119 return ret;
120 }
121
122 if (hsotg->uphy) {
123 ret = usb_phy_init(hsotg->uphy);
124 } else if (hsotg->plat && hsotg->plat->phy_init) {
125 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
126 } else {
127 ret = phy_init(hsotg->phy);
128 if (ret == 0)
129 ret = phy_power_on(hsotg->phy);
130 }
131
132 return ret;
133}
134
135/**
136 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
137 * @hsotg: The driver state
138 *
139 * A wrapper for platform code responsible for controlling
140 * low-level USB platform resources (phy, clock, regulators)
141 */
142int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
143{
144 int ret = __dwc2_lowlevel_hw_enable(hsotg);
145
146 if (ret == 0)
147 hsotg->ll_hw_enabled = true;
148 return ret;
149}
150
151static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
152{
153 struct platform_device *pdev = to_platform_device(hsotg->dev);
154 int ret = 0;
155
156 if (hsotg->uphy) {
157 usb_phy_shutdown(hsotg->uphy);
158 } else if (hsotg->plat && hsotg->plat->phy_exit) {
159 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
160 } else {
161 ret = phy_power_off(hsotg->phy);
162 if (ret == 0)
163 ret = phy_exit(hsotg->phy);
164 }
165 if (ret)
166 return ret;
167
168 if (hsotg->clk)
169 clk_disable_unprepare(hsotg->clk);
170
171 return 0;
172}
173
174/**
175 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
176 * @hsotg: The driver state
177 *
178 * A wrapper for platform code responsible for controlling
179 * low-level USB platform resources (phy, clock, regulators)
180 */
181int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
182{
183 int ret = __dwc2_lowlevel_hw_disable(hsotg);
184
185 if (ret == 0)
186 hsotg->ll_hw_enabled = false;
187 return ret;
188}
189
190static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
191{
192 int i, ret;
193
194 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
195 if (IS_ERR(hsotg->reset))
196 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset),
197 "error getting reset control\n");
198
199 reset_control_deassert(hsotg->reset);
200
201 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
202 if (IS_ERR(hsotg->reset_ecc))
203 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc),
204 "error getting reset control for ecc\n");
205
206 reset_control_deassert(hsotg->reset_ecc);
207
208 /*
209 * Attempt to find a generic PHY, then look for an old style
210 * USB PHY and then fall back to pdata
211 */
212 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
213 if (IS_ERR(hsotg->phy)) {
214 ret = PTR_ERR(hsotg->phy);
215 switch (ret) {
216 case -ENODEV:
217 case -ENOSYS:
218 hsotg->phy = NULL;
219 break;
220 default:
221 return dev_err_probe(hsotg->dev, ret, "error getting phy\n");
222 }
223 }
224
225 if (!hsotg->phy) {
226 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
227 if (IS_ERR(hsotg->uphy)) {
228 ret = PTR_ERR(hsotg->uphy);
229 switch (ret) {
230 case -ENODEV:
231 case -ENXIO:
232 hsotg->uphy = NULL;
233 break;
234 default:
235 return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n");
236 }
237 }
238 }
239
240 hsotg->plat = dev_get_platdata(hsotg->dev);
241
242 /* Clock */
243 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
244 if (IS_ERR(hsotg->clk))
245 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n");
246
247 /* Regulators */
248 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
249 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
250
251 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
252 hsotg->supplies);
253 if (ret)
254 return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n");
255
256 return 0;
257}
258
259/**
260 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
261 * DWC_otg driver
262 *
263 * @dev: Platform device
264 *
265 * This routine is called, for example, when the rmmod command is executed. The
266 * device may or may not be electrically present. If it is present, the driver
267 * stops device processing. Any resources used on behalf of this device are
268 * freed.
269 */
270static int dwc2_driver_remove(struct platform_device *dev)
271{
272 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
273 struct dwc2_gregs_backup *gr;
274 int ret = 0;
275
276 gr = &hsotg->gr_backup;
277
278 /* Exit Hibernation when driver is removed. */
279 if (hsotg->hibernated) {
280 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
281 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
282 else
283 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
284
285 if (ret)
286 dev_err(hsotg->dev,
287 "exit hibernation failed.\n");
288 }
289
290 /* Exit Partial Power Down when driver is removed. */
291 if (hsotg->in_ppd) {
292 ret = dwc2_exit_partial_power_down(hsotg, 0, true);
293 if (ret)
294 dev_err(hsotg->dev,
295 "exit partial_power_down failed\n");
296 }
297
298 /* Exit clock gating when driver is removed. */
299 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
300 hsotg->bus_suspended) {
301 if (dwc2_is_device_mode(hsotg))
302 dwc2_gadget_exit_clock_gating(hsotg, 0);
303 else
304 dwc2_host_exit_clock_gating(hsotg, 0);
305 }
306
307 dwc2_debugfs_exit(hsotg);
308 if (hsotg->hcd_enabled)
309 dwc2_hcd_remove(hsotg);
310 if (hsotg->gadget_enabled)
311 dwc2_hsotg_remove(hsotg);
312
313 dwc2_drd_exit(hsotg);
314
315 if (hsotg->params.activate_stm_id_vb_detection)
316 regulator_disable(hsotg->usb33d);
317
318 if (hsotg->ll_hw_enabled)
319 dwc2_lowlevel_hw_disable(hsotg);
320
321 reset_control_assert(hsotg->reset);
322 reset_control_assert(hsotg->reset_ecc);
323
324 return 0;
325}
326
327/**
328 * dwc2_driver_shutdown() - Called on device shutdown
329 *
330 * @dev: Platform device
331 *
332 * In specific conditions (involving usb hubs) dwc2 devices can create a
333 * lot of interrupts, even to the point of overwhelming devices running
334 * at low frequencies. Some devices need to do special clock handling
335 * at shutdown-time which may bring the system clock below the threshold
336 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
337 * prevents reboots/poweroffs from getting stuck in such cases.
338 */
339static void dwc2_driver_shutdown(struct platform_device *dev)
340{
341 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
342
343 dwc2_disable_global_interrupts(hsotg);
344 synchronize_irq(hsotg->irq);
345}
346
347/**
348 * dwc2_check_core_endianness() - Returns true if core and AHB have
349 * opposite endianness.
350 * @hsotg: Programming view of the DWC_otg controller.
351 */
352static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
353{
354 u32 snpsid;
355
356 snpsid = ioread32(hsotg->regs + GSNPSID);
357 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
358 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
359 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
360 return false;
361 return true;
362}
363
364/**
365 * dwc2_check_core_version() - Check core version
366 *
367 * @hsotg: Programming view of the DWC_otg controller
368 *
369 */
370int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
371{
372 struct dwc2_hw_params *hw = &hsotg->hw_params;
373
374 /*
375 * Attempt to ensure this device is really a DWC_otg Controller.
376 * Read and verify the GSNPSID register contents. The value should be
377 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
378 */
379
380 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
381 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
382 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
383 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
384 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
385 hw->snpsid);
386 return -ENODEV;
387 }
388
389 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
390 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
391 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
392 return 0;
393}
394
395/**
396 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
397 * driver
398 *
399 * @dev: Platform device
400 *
401 * This routine creates the driver components required to control the device
402 * (core, HCD, and PCD) and initializes the device. The driver components are
403 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
404 * in the device private data. This allows the driver to access the dwc2_hsotg
405 * structure on subsequent calls to driver methods for this device.
406 */
407static int dwc2_driver_probe(struct platform_device *dev)
408{
409 struct dwc2_hsotg *hsotg;
410 struct resource *res;
411 int retval;
412
413 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
414 if (!hsotg)
415 return -ENOMEM;
416
417 hsotg->dev = &dev->dev;
418
419 /*
420 * Use reasonable defaults so platforms don't have to provide these.
421 */
422 if (!dev->dev.dma_mask)
423 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
424 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
425 if (retval) {
426 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
427 return retval;
428 }
429
430 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
431 if (IS_ERR(hsotg->regs))
432 return PTR_ERR(hsotg->regs);
433
434 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
435 (unsigned long)res->start, hsotg->regs);
436
437 retval = dwc2_lowlevel_hw_init(hsotg);
438 if (retval)
439 return retval;
440
441 spin_lock_init(&hsotg->lock);
442
443 hsotg->irq = platform_get_irq(dev, 0);
444 if (hsotg->irq < 0)
445 return hsotg->irq;
446
447 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
448 hsotg->irq);
449 retval = devm_request_irq(hsotg->dev, hsotg->irq,
450 dwc2_handle_common_intr, IRQF_SHARED,
451 dev_name(hsotg->dev), hsotg);
452 if (retval)
453 return retval;
454
455 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
456 if (IS_ERR(hsotg->vbus_supply)) {
457 retval = PTR_ERR(hsotg->vbus_supply);
458 hsotg->vbus_supply = NULL;
459 if (retval != -ENODEV)
460 return retval;
461 }
462
463 retval = dwc2_lowlevel_hw_enable(hsotg);
464 if (retval)
465 return retval;
466
467 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
468
469 retval = dwc2_get_dr_mode(hsotg);
470 if (retval)
471 goto error;
472
473 hsotg->need_phy_for_wake =
474 of_property_read_bool(dev->dev.of_node,
475 "snps,need-phy-for-wake");
476
477 /*
478 * Before performing any core related operations
479 * check core version.
480 */
481 retval = dwc2_check_core_version(hsotg);
482 if (retval)
483 goto error;
484
485 /*
486 * Reset before dwc2_get_hwparams() then it could get power-on real
487 * reset value form registers.
488 */
489 retval = dwc2_core_reset(hsotg, false);
490 if (retval)
491 goto error;
492
493 /* Detect config values from hardware */
494 retval = dwc2_get_hwparams(hsotg);
495 if (retval)
496 goto error;
497
498 /*
499 * For OTG cores, set the force mode bits to reflect the value
500 * of dr_mode. Force mode bits should not be touched at any
501 * other time after this.
502 */
503 dwc2_force_dr_mode(hsotg);
504
505 retval = dwc2_init_params(hsotg);
506 if (retval)
507 goto error;
508
509 if (hsotg->params.activate_stm_id_vb_detection) {
510 u32 ggpio;
511
512 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
513 if (IS_ERR(hsotg->usb33d)) {
514 retval = PTR_ERR(hsotg->usb33d);
515 dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n");
516 goto error;
517 }
518 retval = regulator_enable(hsotg->usb33d);
519 if (retval) {
520 dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n");
521 goto error;
522 }
523
524 ggpio = dwc2_readl(hsotg, GGPIO);
525 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
526 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
527 dwc2_writel(hsotg, ggpio, GGPIO);
528
529 /* ID/VBUS detection startup time */
530 usleep_range(5000, 7000);
531 }
532
533 retval = dwc2_drd_init(hsotg);
534 if (retval) {
535 dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n");
536 goto error_init;
537 }
538
539 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
540 retval = dwc2_gadget_init(hsotg);
541 if (retval)
542 goto error_drd;
543 hsotg->gadget_enabled = 1;
544 }
545
546 /*
547 * If we need PHY for wakeup we must be wakeup capable.
548 * When we have a device that can wake without the PHY we
549 * can adjust this condition.
550 */
551 if (hsotg->need_phy_for_wake)
552 device_set_wakeup_capable(&dev->dev, true);
553
554 hsotg->reset_phy_on_wake =
555 of_property_read_bool(dev->dev.of_node,
556 "snps,reset-phy-on-wake");
557 if (hsotg->reset_phy_on_wake && !hsotg->phy) {
558 dev_warn(hsotg->dev,
559 "Quirk reset-phy-on-wake only supports generic PHYs\n");
560 hsotg->reset_phy_on_wake = false;
561 }
562
563 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
564 retval = dwc2_hcd_init(hsotg);
565 if (retval) {
566 if (hsotg->gadget_enabled)
567 dwc2_hsotg_remove(hsotg);
568 goto error_drd;
569 }
570 hsotg->hcd_enabled = 1;
571 }
572
573 platform_set_drvdata(dev, hsotg);
574 hsotg->hibernated = 0;
575
576 dwc2_debugfs_init(hsotg);
577
578 /* Gadget code manages lowlevel hw on its own */
579 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL ||
580 (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)))
581 dwc2_lowlevel_hw_disable(hsotg);
582
583#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
584 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
585 /* Postponed adding a new gadget to the udc class driver list */
586 if (hsotg->gadget_enabled) {
587 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
588 if (retval) {
589 hsotg->gadget.udc = NULL;
590 dwc2_hsotg_remove(hsotg);
591 goto error_debugfs;
592 }
593 }
594#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
595 return 0;
596
597#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
598 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
599error_debugfs:
600 dwc2_debugfs_exit(hsotg);
601 if (hsotg->hcd_enabled)
602 dwc2_hcd_remove(hsotg);
603#endif
604error_drd:
605 dwc2_drd_exit(hsotg);
606
607error_init:
608 if (hsotg->params.activate_stm_id_vb_detection)
609 regulator_disable(hsotg->usb33d);
610error:
611 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL)
612 dwc2_lowlevel_hw_disable(hsotg);
613 return retval;
614}
615
616static int __maybe_unused dwc2_suspend(struct device *dev)
617{
618 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
619 bool is_device_mode = dwc2_is_device_mode(dwc2);
620 int ret = 0;
621
622 if (is_device_mode)
623 dwc2_hsotg_suspend(dwc2);
624
625 dwc2_drd_suspend(dwc2);
626
627 if (dwc2->params.activate_stm_id_vb_detection) {
628 unsigned long flags;
629 u32 ggpio, gotgctl;
630
631 /*
632 * Need to force the mode to the current mode to avoid Mode
633 * Mismatch Interrupt when ID detection will be disabled.
634 */
635 dwc2_force_mode(dwc2, !is_device_mode);
636
637 spin_lock_irqsave(&dwc2->lock, flags);
638 gotgctl = dwc2_readl(dwc2, GOTGCTL);
639 /* bypass debounce filter, enable overrides */
640 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
641 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
642 /* Force A / B session if needed */
643 if (gotgctl & GOTGCTL_ASESVLD)
644 gotgctl |= GOTGCTL_AVALOVAL;
645 if (gotgctl & GOTGCTL_BSESVLD)
646 gotgctl |= GOTGCTL_BVALOVAL;
647 dwc2_writel(dwc2, gotgctl, GOTGCTL);
648 spin_unlock_irqrestore(&dwc2->lock, flags);
649
650 ggpio = dwc2_readl(dwc2, GGPIO);
651 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
652 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
653 dwc2_writel(dwc2, ggpio, GGPIO);
654
655 regulator_disable(dwc2->usb33d);
656 }
657
658 if (dwc2->ll_hw_enabled &&
659 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
660 ret = __dwc2_lowlevel_hw_disable(dwc2);
661 dwc2->phy_off_for_suspend = true;
662 }
663
664 return ret;
665}
666
667static int __maybe_unused dwc2_resume(struct device *dev)
668{
669 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
670 int ret = 0;
671
672 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
673 ret = __dwc2_lowlevel_hw_enable(dwc2);
674 if (ret)
675 return ret;
676 }
677 dwc2->phy_off_for_suspend = false;
678
679 if (dwc2->params.activate_stm_id_vb_detection) {
680 unsigned long flags;
681 u32 ggpio, gotgctl;
682
683 ret = regulator_enable(dwc2->usb33d);
684 if (ret)
685 return ret;
686
687 ggpio = dwc2_readl(dwc2, GGPIO);
688 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
689 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
690 dwc2_writel(dwc2, ggpio, GGPIO);
691
692 /* ID/VBUS detection startup time */
693 usleep_range(5000, 7000);
694
695 spin_lock_irqsave(&dwc2->lock, flags);
696 gotgctl = dwc2_readl(dwc2, GOTGCTL);
697 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
698 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
699 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
700 dwc2_writel(dwc2, gotgctl, GOTGCTL);
701 spin_unlock_irqrestore(&dwc2->lock, flags);
702 }
703
704 if (!dwc2->role_sw) {
705 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
706 dwc2_force_dr_mode(dwc2);
707 } else {
708 dwc2_drd_resume(dwc2);
709 }
710
711 if (dwc2_is_device_mode(dwc2))
712 ret = dwc2_hsotg_resume(dwc2);
713
714 return ret;
715}
716
717static const struct dev_pm_ops dwc2_dev_pm_ops = {
718 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
719};
720
721static struct platform_driver dwc2_platform_driver = {
722 .driver = {
723 .name = dwc2_driver_name,
724 .of_match_table = dwc2_of_match_table,
725 .acpi_match_table = ACPI_PTR(dwc2_acpi_match),
726 .pm = &dwc2_dev_pm_ops,
727 },
728 .probe = dwc2_driver_probe,
729 .remove = dwc2_driver_remove,
730 .shutdown = dwc2_driver_shutdown,
731};
732
733module_platform_driver(dwc2_platform_driver);
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * platform.c - DesignWare HS OTG Controller platform driver
4 *
5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/slab.h>
41#include <linux/clk.h>
42#include <linux/device.h>
43#include <linux/dma-mapping.h>
44#include <linux/of_device.h>
45#include <linux/mutex.h>
46#include <linux/platform_device.h>
47#include <linux/phy/phy.h>
48#include <linux/platform_data/s3c-hsotg.h>
49#include <linux/reset.h>
50
51#include <linux/usb/of.h>
52
53#include "core.h"
54#include "hcd.h"
55#include "debug.h"
56
57static const char dwc2_driver_name[] = "dwc2";
58
59/*
60 * Check the dr_mode against the module configuration and hardware
61 * capabilities.
62 *
63 * The hardware, module, and dr_mode, can each be set to host, device,
64 * or otg. Check that all these values are compatible and adjust the
65 * value of dr_mode if possible.
66 *
67 * actual
68 * HW MOD dr_mode dr_mode
69 * ------------------------------
70 * HST HST any : HST
71 * HST DEV any : ---
72 * HST OTG any : HST
73 *
74 * DEV HST any : ---
75 * DEV DEV any : DEV
76 * DEV OTG any : DEV
77 *
78 * OTG HST any : HST
79 * OTG DEV any : DEV
80 * OTG OTG any : dr_mode
81 */
82static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
83{
84 enum usb_dr_mode mode;
85
86 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
87 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
88 hsotg->dr_mode = USB_DR_MODE_OTG;
89
90 mode = hsotg->dr_mode;
91
92 if (dwc2_hw_is_device(hsotg)) {
93 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
94 dev_err(hsotg->dev,
95 "Controller does not support host mode.\n");
96 return -EINVAL;
97 }
98 mode = USB_DR_MODE_PERIPHERAL;
99 } else if (dwc2_hw_is_host(hsotg)) {
100 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
101 dev_err(hsotg->dev,
102 "Controller does not support device mode.\n");
103 return -EINVAL;
104 }
105 mode = USB_DR_MODE_HOST;
106 } else {
107 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
108 mode = USB_DR_MODE_HOST;
109 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
110 mode = USB_DR_MODE_PERIPHERAL;
111 }
112
113 if (mode != hsotg->dr_mode) {
114 dev_warn(hsotg->dev,
115 "Configuration mismatch. dr_mode forced to %s\n",
116 mode == USB_DR_MODE_HOST ? "host" : "device");
117
118 hsotg->dr_mode = mode;
119 }
120
121 return 0;
122}
123
124static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
125{
126 struct platform_device *pdev = to_platform_device(hsotg->dev);
127 int ret;
128
129 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
130 hsotg->supplies);
131 if (ret)
132 return ret;
133
134 if (hsotg->clk) {
135 ret = clk_prepare_enable(hsotg->clk);
136 if (ret)
137 return ret;
138 }
139
140 if (hsotg->uphy) {
141 ret = usb_phy_init(hsotg->uphy);
142 } else if (hsotg->plat && hsotg->plat->phy_init) {
143 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
144 } else {
145 ret = phy_power_on(hsotg->phy);
146 if (ret == 0)
147 ret = phy_init(hsotg->phy);
148 }
149
150 return ret;
151}
152
153/**
154 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
155 * @hsotg: The driver state
156 *
157 * A wrapper for platform code responsible for controlling
158 * low-level USB platform resources (phy, clock, regulators)
159 */
160int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
161{
162 int ret = __dwc2_lowlevel_hw_enable(hsotg);
163
164 if (ret == 0)
165 hsotg->ll_hw_enabled = true;
166 return ret;
167}
168
169static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
170{
171 struct platform_device *pdev = to_platform_device(hsotg->dev);
172 int ret = 0;
173
174 if (hsotg->uphy) {
175 usb_phy_shutdown(hsotg->uphy);
176 } else if (hsotg->plat && hsotg->plat->phy_exit) {
177 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
178 } else {
179 ret = phy_exit(hsotg->phy);
180 if (ret == 0)
181 ret = phy_power_off(hsotg->phy);
182 }
183 if (ret)
184 return ret;
185
186 if (hsotg->clk)
187 clk_disable_unprepare(hsotg->clk);
188
189 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
190 hsotg->supplies);
191
192 return ret;
193}
194
195/**
196 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
197 * @hsotg: The driver state
198 *
199 * A wrapper for platform code responsible for controlling
200 * low-level USB platform resources (phy, clock, regulators)
201 */
202int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
203{
204 int ret = __dwc2_lowlevel_hw_disable(hsotg);
205
206 if (ret == 0)
207 hsotg->ll_hw_enabled = false;
208 return ret;
209}
210
211static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
212{
213 int i, ret;
214
215 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
216 if (IS_ERR(hsotg->reset)) {
217 ret = PTR_ERR(hsotg->reset);
218 dev_err(hsotg->dev, "error getting reset control %d\n", ret);
219 return ret;
220 }
221
222 reset_control_deassert(hsotg->reset);
223
224 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
225 if (IS_ERR(hsotg->reset_ecc)) {
226 ret = PTR_ERR(hsotg->reset_ecc);
227 dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
228 return ret;
229 }
230
231 reset_control_deassert(hsotg->reset_ecc);
232
233 /*
234 * Attempt to find a generic PHY, then look for an old style
235 * USB PHY and then fall back to pdata
236 */
237 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
238 if (IS_ERR(hsotg->phy)) {
239 ret = PTR_ERR(hsotg->phy);
240 switch (ret) {
241 case -ENODEV:
242 case -ENOSYS:
243 hsotg->phy = NULL;
244 break;
245 case -EPROBE_DEFER:
246 return ret;
247 default:
248 dev_err(hsotg->dev, "error getting phy %d\n", ret);
249 return ret;
250 }
251 }
252
253 if (!hsotg->phy) {
254 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
255 if (IS_ERR(hsotg->uphy)) {
256 ret = PTR_ERR(hsotg->uphy);
257 switch (ret) {
258 case -ENODEV:
259 case -ENXIO:
260 hsotg->uphy = NULL;
261 break;
262 case -EPROBE_DEFER:
263 return ret;
264 default:
265 dev_err(hsotg->dev, "error getting usb phy %d\n",
266 ret);
267 return ret;
268 }
269 }
270 }
271
272 hsotg->plat = dev_get_platdata(hsotg->dev);
273
274 /* Clock */
275 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
276 if (IS_ERR(hsotg->clk)) {
277 dev_err(hsotg->dev, "cannot get otg clock\n");
278 return PTR_ERR(hsotg->clk);
279 }
280
281 /* Regulators */
282 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
283 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
284
285 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
286 hsotg->supplies);
287 if (ret) {
288 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
289 return ret;
290 }
291 return 0;
292}
293
294/**
295 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
296 * DWC_otg driver
297 *
298 * @dev: Platform device
299 *
300 * This routine is called, for example, when the rmmod command is executed. The
301 * device may or may not be electrically present. If it is present, the driver
302 * stops device processing. Any resources used on behalf of this device are
303 * freed.
304 */
305static int dwc2_driver_remove(struct platform_device *dev)
306{
307 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
308
309 dwc2_debugfs_exit(hsotg);
310 if (hsotg->hcd_enabled)
311 dwc2_hcd_remove(hsotg);
312 if (hsotg->gadget_enabled)
313 dwc2_hsotg_remove(hsotg);
314
315 if (hsotg->ll_hw_enabled)
316 dwc2_lowlevel_hw_disable(hsotg);
317
318 reset_control_assert(hsotg->reset);
319 reset_control_assert(hsotg->reset_ecc);
320
321 return 0;
322}
323
324/**
325 * dwc2_driver_shutdown() - Called on device shutdown
326 *
327 * @dev: Platform device
328 *
329 * In specific conditions (involving usb hubs) dwc2 devices can create a
330 * lot of interrupts, even to the point of overwhelming devices running
331 * at low frequencies. Some devices need to do special clock handling
332 * at shutdown-time which may bring the system clock below the threshold
333 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
334 * prevents reboots/poweroffs from getting stuck in such cases.
335 */
336static void dwc2_driver_shutdown(struct platform_device *dev)
337{
338 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
339
340 disable_irq(hsotg->irq);
341}
342
343/**
344 * dwc2_check_core_endianness() - Returns true if core and AHB have
345 * opposite endianness.
346 * @hsotg: Programming view of the DWC_otg controller.
347 */
348static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
349{
350 u32 snpsid;
351
352 snpsid = ioread32(hsotg->regs + GSNPSID);
353 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
354 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
355 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
356 return false;
357 return true;
358}
359
360/**
361 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
362 * driver
363 *
364 * @dev: Platform device
365 *
366 * This routine creates the driver components required to control the device
367 * (core, HCD, and PCD) and initializes the device. The driver components are
368 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
369 * in the device private data. This allows the driver to access the dwc2_hsotg
370 * structure on subsequent calls to driver methods for this device.
371 */
372static int dwc2_driver_probe(struct platform_device *dev)
373{
374 struct dwc2_hsotg *hsotg;
375 struct resource *res;
376 int retval;
377
378 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
379 if (!hsotg)
380 return -ENOMEM;
381
382 hsotg->dev = &dev->dev;
383
384 /*
385 * Use reasonable defaults so platforms don't have to provide these.
386 */
387 if (!dev->dev.dma_mask)
388 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
389 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
390 if (retval) {
391 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
392 return retval;
393 }
394
395 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
396 hsotg->regs = devm_ioremap_resource(&dev->dev, res);
397 if (IS_ERR(hsotg->regs))
398 return PTR_ERR(hsotg->regs);
399
400 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
401 (unsigned long)res->start, hsotg->regs);
402
403 retval = dwc2_lowlevel_hw_init(hsotg);
404 if (retval)
405 return retval;
406
407 spin_lock_init(&hsotg->lock);
408
409 hsotg->irq = platform_get_irq(dev, 0);
410 if (hsotg->irq < 0)
411 return hsotg->irq;
412
413 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
414 hsotg->irq);
415 retval = devm_request_irq(hsotg->dev, hsotg->irq,
416 dwc2_handle_common_intr, IRQF_SHARED,
417 dev_name(hsotg->dev), hsotg);
418 if (retval)
419 return retval;
420
421 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
422 if (IS_ERR(hsotg->vbus_supply)) {
423 retval = PTR_ERR(hsotg->vbus_supply);
424 hsotg->vbus_supply = NULL;
425 if (retval != -ENODEV)
426 return retval;
427 }
428
429 retval = dwc2_lowlevel_hw_enable(hsotg);
430 if (retval)
431 return retval;
432
433 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
434
435 retval = dwc2_get_dr_mode(hsotg);
436 if (retval)
437 goto error;
438
439 hsotg->need_phy_for_wake =
440 of_property_read_bool(dev->dev.of_node,
441 "snps,need-phy-for-wake");
442
443 /*
444 * Reset before dwc2_get_hwparams() then it could get power-on real
445 * reset value form registers.
446 */
447 retval = dwc2_core_reset(hsotg, false);
448 if (retval)
449 goto error;
450
451 /* Detect config values from hardware */
452 retval = dwc2_get_hwparams(hsotg);
453 if (retval)
454 goto error;
455
456 /*
457 * For OTG cores, set the force mode bits to reflect the value
458 * of dr_mode. Force mode bits should not be touched at any
459 * other time after this.
460 */
461 dwc2_force_dr_mode(hsotg);
462
463 retval = dwc2_init_params(hsotg);
464 if (retval)
465 goto error;
466
467 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
468 retval = dwc2_gadget_init(hsotg);
469 if (retval)
470 goto error;
471 hsotg->gadget_enabled = 1;
472 }
473
474 /*
475 * If we need PHY for wakeup we must be wakeup capable.
476 * When we have a device that can wake without the PHY we
477 * can adjust this condition.
478 */
479 if (hsotg->need_phy_for_wake)
480 device_set_wakeup_capable(&dev->dev, true);
481
482 hsotg->reset_phy_on_wake =
483 of_property_read_bool(dev->dev.of_node,
484 "snps,reset-phy-on-wake");
485 if (hsotg->reset_phy_on_wake && !hsotg->phy) {
486 dev_warn(hsotg->dev,
487 "Quirk reset-phy-on-wake only supports generic PHYs\n");
488 hsotg->reset_phy_on_wake = false;
489 }
490
491 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
492 retval = dwc2_hcd_init(hsotg);
493 if (retval) {
494 if (hsotg->gadget_enabled)
495 dwc2_hsotg_remove(hsotg);
496 goto error;
497 }
498 hsotg->hcd_enabled = 1;
499 }
500
501 platform_set_drvdata(dev, hsotg);
502 hsotg->hibernated = 0;
503
504 dwc2_debugfs_init(hsotg);
505
506 /* Gadget code manages lowlevel hw on its own */
507 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
508 dwc2_lowlevel_hw_disable(hsotg);
509
510 return 0;
511
512error:
513 dwc2_lowlevel_hw_disable(hsotg);
514 return retval;
515}
516
517static int __maybe_unused dwc2_suspend(struct device *dev)
518{
519 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
520 bool is_device_mode = dwc2_is_device_mode(dwc2);
521 int ret = 0;
522
523 if (is_device_mode)
524 dwc2_hsotg_suspend(dwc2);
525
526 if (dwc2->ll_hw_enabled &&
527 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
528 ret = __dwc2_lowlevel_hw_disable(dwc2);
529 dwc2->phy_off_for_suspend = true;
530 }
531
532 return ret;
533}
534
535static int __maybe_unused dwc2_resume(struct device *dev)
536{
537 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
538 int ret = 0;
539
540 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
541 ret = __dwc2_lowlevel_hw_enable(dwc2);
542 if (ret)
543 return ret;
544 }
545 dwc2->phy_off_for_suspend = false;
546
547 if (dwc2_is_device_mode(dwc2))
548 ret = dwc2_hsotg_resume(dwc2);
549
550 return ret;
551}
552
553static const struct dev_pm_ops dwc2_dev_pm_ops = {
554 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
555};
556
557static struct platform_driver dwc2_platform_driver = {
558 .driver = {
559 .name = dwc2_driver_name,
560 .of_match_table = dwc2_of_match_table,
561 .pm = &dwc2_dev_pm_ops,
562 },
563 .probe = dwc2_driver_probe,
564 .remove = dwc2_driver_remove,
565 .shutdown = dwc2_driver_shutdown,
566};
567
568module_platform_driver(dwc2_platform_driver);
569
570MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
571MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
572MODULE_LICENSE("Dual BSD/GPL");