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1/*
2 * TXx9 SPI controller driver.
3 *
4 * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 *
14 * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
15 */
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/spi/spi.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/gpio.h>
30
31
32#define SPI_FIFO_SIZE 4
33#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
34#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
35
36#define TXx9_SPMCR 0x00
37#define TXx9_SPCR0 0x04
38#define TXx9_SPCR1 0x08
39#define TXx9_SPFS 0x0c
40#define TXx9_SPSR 0x14
41#define TXx9_SPDR 0x18
42
43/* SPMCR : SPI Master Control */
44#define TXx9_SPMCR_OPMODE 0xc0
45#define TXx9_SPMCR_CONFIG 0x40
46#define TXx9_SPMCR_ACTIVE 0x80
47#define TXx9_SPMCR_SPSTP 0x02
48#define TXx9_SPMCR_BCLR 0x01
49
50/* SPCR0 : SPI Control 0 */
51#define TXx9_SPCR0_TXIFL_MASK 0xc000
52#define TXx9_SPCR0_RXIFL_MASK 0x3000
53#define TXx9_SPCR0_SIDIE 0x0800
54#define TXx9_SPCR0_SOEIE 0x0400
55#define TXx9_SPCR0_RBSIE 0x0200
56#define TXx9_SPCR0_TBSIE 0x0100
57#define TXx9_SPCR0_IFSPSE 0x0010
58#define TXx9_SPCR0_SBOS 0x0004
59#define TXx9_SPCR0_SPHA 0x0002
60#define TXx9_SPCR0_SPOL 0x0001
61
62/* SPSR : SPI Status */
63#define TXx9_SPSR_TBSI 0x8000
64#define TXx9_SPSR_RBSI 0x4000
65#define TXx9_SPSR_TBS_MASK 0x3800
66#define TXx9_SPSR_RBS_MASK 0x0700
67#define TXx9_SPSR_SPOE 0x0080
68#define TXx9_SPSR_IFSD 0x0008
69#define TXx9_SPSR_SIDLE 0x0004
70#define TXx9_SPSR_STRDY 0x0002
71#define TXx9_SPSR_SRRDY 0x0001
72
73
74struct txx9spi {
75 struct work_struct work;
76 spinlock_t lock; /* protect 'queue' */
77 struct list_head queue;
78 wait_queue_head_t waitq;
79 void __iomem *membase;
80 int baseclk;
81 struct clk *clk;
82 int last_chipselect;
83 int last_chipselect_val;
84};
85
86static u32 txx9spi_rd(struct txx9spi *c, int reg)
87{
88 return __raw_readl(c->membase + reg);
89}
90static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
91{
92 __raw_writel(val, c->membase + reg);
93}
94
95static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
96 int on, unsigned int cs_delay)
97{
98 int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
99
100 if (on) {
101 /* deselect the chip with cs_change hint in last transfer */
102 if (c->last_chipselect >= 0)
103 gpio_set_value(c->last_chipselect,
104 !c->last_chipselect_val);
105 c->last_chipselect = spi->chip_select;
106 c->last_chipselect_val = val;
107 } else {
108 c->last_chipselect = -1;
109 ndelay(cs_delay); /* CS Hold Time */
110 }
111 gpio_set_value(spi->chip_select, val);
112 ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
113}
114
115static int txx9spi_setup(struct spi_device *spi)
116{
117 struct txx9spi *c = spi_master_get_devdata(spi->master);
118
119 if (!spi->max_speed_hz)
120 return -EINVAL;
121
122 if (gpio_direction_output(spi->chip_select,
123 !(spi->mode & SPI_CS_HIGH))) {
124 dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
125 return -EINVAL;
126 }
127
128 /* deselect chip */
129 spin_lock(&c->lock);
130 txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
131 spin_unlock(&c->lock);
132
133 return 0;
134}
135
136static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
137{
138 struct txx9spi *c = dev_id;
139
140 /* disable rx intr */
141 txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
142 TXx9_SPCR0);
143 wake_up(&c->waitq);
144 return IRQ_HANDLED;
145}
146
147static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
148{
149 struct spi_device *spi = m->spi;
150 struct spi_transfer *t;
151 unsigned int cs_delay;
152 unsigned int cs_change = 1;
153 int status = 0;
154 u32 mcr;
155 u32 prev_speed_hz = 0;
156 u8 prev_bits_per_word = 0;
157
158 /* CS setup/hold/recovery time in nsec */
159 cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
160
161 mcr = txx9spi_rd(c, TXx9_SPMCR);
162 if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
163 dev_err(&spi->dev, "Bad mode.\n");
164 status = -EIO;
165 goto exit;
166 }
167 mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
168
169 /* enter config mode */
170 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
171 txx9spi_wr(c, TXx9_SPCR0_SBOS
172 | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
173 | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
174 | 0x08,
175 TXx9_SPCR0);
176
177 list_for_each_entry(t, &m->transfers, transfer_list) {
178 const void *txbuf = t->tx_buf;
179 void *rxbuf = t->rx_buf;
180 u32 data;
181 unsigned int len = t->len;
182 unsigned int wsize;
183 u32 speed_hz = t->speed_hz;
184 u8 bits_per_word = t->bits_per_word;
185
186 wsize = bits_per_word >> 3; /* in bytes */
187
188 if (prev_speed_hz != speed_hz
189 || prev_bits_per_word != bits_per_word) {
190 int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
191
192 n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
193 /* enter config mode */
194 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
195 TXx9_SPMCR);
196 txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
197 /* enter active mode */
198 txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
199
200 prev_speed_hz = speed_hz;
201 prev_bits_per_word = bits_per_word;
202 }
203
204 if (cs_change)
205 txx9spi_cs_func(spi, c, 1, cs_delay);
206 cs_change = t->cs_change;
207 while (len) {
208 unsigned int count = SPI_FIFO_SIZE;
209 int i;
210 u32 cr0;
211
212 if (len < count * wsize)
213 count = len / wsize;
214 /* now tx must be idle... */
215 while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
216 cpu_relax();
217 cr0 = txx9spi_rd(c, TXx9_SPCR0);
218 cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
219 cr0 |= (count - 1) << 12;
220 /* enable rx intr */
221 cr0 |= TXx9_SPCR0_RBSIE;
222 txx9spi_wr(c, cr0, TXx9_SPCR0);
223 /* send */
224 for (i = 0; i < count; i++) {
225 if (txbuf) {
226 data = (wsize == 1)
227 ? *(const u8 *)txbuf
228 : *(const u16 *)txbuf;
229 txx9spi_wr(c, data, TXx9_SPDR);
230 txbuf += wsize;
231 } else
232 txx9spi_wr(c, 0, TXx9_SPDR);
233 }
234 /* wait all rx data */
235 wait_event(c->waitq,
236 txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
237 /* receive */
238 for (i = 0; i < count; i++) {
239 data = txx9spi_rd(c, TXx9_SPDR);
240 if (rxbuf) {
241 if (wsize == 1)
242 *(u8 *)rxbuf = data;
243 else
244 *(u16 *)rxbuf = data;
245 rxbuf += wsize;
246 }
247 }
248 len -= count * wsize;
249 }
250 m->actual_length += t->len;
251 if (t->delay_usecs)
252 udelay(t->delay_usecs);
253
254 if (!cs_change)
255 continue;
256 if (t->transfer_list.next == &m->transfers)
257 break;
258 /* sometimes a short mid-message deselect of the chip
259 * may be needed to terminate a mode or command
260 */
261 txx9spi_cs_func(spi, c, 0, cs_delay);
262 }
263
264exit:
265 m->status = status;
266 if (m->complete)
267 m->complete(m->context);
268
269 /* normally deactivate chipselect ... unless no error and
270 * cs_change has hinted that the next message will probably
271 * be for this chip too.
272 */
273 if (!(status == 0 && cs_change))
274 txx9spi_cs_func(spi, c, 0, cs_delay);
275
276 /* enter config mode */
277 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
278}
279
280static void txx9spi_work(struct work_struct *work)
281{
282 struct txx9spi *c = container_of(work, struct txx9spi, work);
283 unsigned long flags;
284
285 spin_lock_irqsave(&c->lock, flags);
286 while (!list_empty(&c->queue)) {
287 struct spi_message *m;
288
289 m = container_of(c->queue.next, struct spi_message, queue);
290 list_del_init(&m->queue);
291 spin_unlock_irqrestore(&c->lock, flags);
292
293 txx9spi_work_one(c, m);
294
295 spin_lock_irqsave(&c->lock, flags);
296 }
297 spin_unlock_irqrestore(&c->lock, flags);
298}
299
300static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
301{
302 struct spi_master *master = spi->master;
303 struct txx9spi *c = spi_master_get_devdata(master);
304 struct spi_transfer *t;
305 unsigned long flags;
306
307 m->actual_length = 0;
308
309 /* check each transfer's parameters */
310 list_for_each_entry(t, &m->transfers, transfer_list) {
311 if (!t->tx_buf && !t->rx_buf && t->len)
312 return -EINVAL;
313 }
314
315 spin_lock_irqsave(&c->lock, flags);
316 list_add_tail(&m->queue, &c->queue);
317 schedule_work(&c->work);
318 spin_unlock_irqrestore(&c->lock, flags);
319
320 return 0;
321}
322
323static int txx9spi_probe(struct platform_device *dev)
324{
325 struct spi_master *master;
326 struct txx9spi *c;
327 struct resource *res;
328 int ret = -ENODEV;
329 u32 mcr;
330 int irq;
331
332 master = spi_alloc_master(&dev->dev, sizeof(*c));
333 if (!master)
334 return ret;
335 c = spi_master_get_devdata(master);
336 platform_set_drvdata(dev, master);
337
338 INIT_WORK(&c->work, txx9spi_work);
339 spin_lock_init(&c->lock);
340 INIT_LIST_HEAD(&c->queue);
341 init_waitqueue_head(&c->waitq);
342
343 c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
344 if (IS_ERR(c->clk)) {
345 ret = PTR_ERR(c->clk);
346 c->clk = NULL;
347 goto exit;
348 }
349 ret = clk_prepare_enable(c->clk);
350 if (ret) {
351 c->clk = NULL;
352 goto exit;
353 }
354 c->baseclk = clk_get_rate(c->clk);
355 master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
356 master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
357
358 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
359 c->membase = devm_ioremap_resource(&dev->dev, res);
360 if (IS_ERR(c->membase))
361 goto exit_busy;
362
363 /* enter config mode */
364 mcr = txx9spi_rd(c, TXx9_SPMCR);
365 mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
366 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
367
368 irq = platform_get_irq(dev, 0);
369 if (irq < 0)
370 goto exit_busy;
371 ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
372 "spi_txx9", c);
373 if (ret)
374 goto exit;
375
376 c->last_chipselect = -1;
377
378 dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
379 (unsigned long long)res->start, irq,
380 (c->baseclk + 500000) / 1000000);
381
382 /* the spi->mode bits understood by this driver: */
383 master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
384
385 master->bus_num = dev->id;
386 master->setup = txx9spi_setup;
387 master->transfer = txx9spi_transfer;
388 master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
389 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
390
391 ret = devm_spi_register_master(&dev->dev, master);
392 if (ret)
393 goto exit;
394 return 0;
395exit_busy:
396 ret = -EBUSY;
397exit:
398 clk_disable_unprepare(c->clk);
399 spi_master_put(master);
400 return ret;
401}
402
403static int txx9spi_remove(struct platform_device *dev)
404{
405 struct spi_master *master = platform_get_drvdata(dev);
406 struct txx9spi *c = spi_master_get_devdata(master);
407
408 flush_work(&c->work);
409 clk_disable_unprepare(c->clk);
410 return 0;
411}
412
413/* work with hotplug and coldplug */
414MODULE_ALIAS("platform:spi_txx9");
415
416static struct platform_driver txx9spi_driver = {
417 .probe = txx9spi_probe,
418 .remove = txx9spi_remove,
419 .driver = {
420 .name = "spi_txx9",
421 },
422};
423
424static int __init txx9spi_init(void)
425{
426 return platform_driver_register(&txx9spi_driver);
427}
428subsys_initcall(txx9spi_init);
429
430static void __exit txx9spi_exit(void)
431{
432 platform_driver_unregister(&txx9spi_driver);
433}
434module_exit(txx9spi_exit);
435
436MODULE_DESCRIPTION("TXx9 SPI Driver");
437MODULE_LICENSE("GPL");