1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2004 Fetron GmbH
 4 *
 5 * S3C2410 SPI register definition
 6 */
 7
 8#ifndef __SPI_S3C2410_H
 9#define __SPI_S3C2410_H
10
11#define S3C2410_SPCON		(0x00)
12
13#define S3C2410_SPCON_SMOD_DMA	(2 << 5)	/* DMA mode */
14#define S3C2410_SPCON_SMOD_INT	(1 << 5)	/* interrupt mode */
15#define S3C2410_SPCON_SMOD_POLL	(0 << 5)	/* polling mode */
16#define S3C2410_SPCON_ENSCK	(1 << 4)	/* Enable SCK */
17#define S3C2410_SPCON_MSTR	(1 << 3)	/* Master:1, Slave:0 select */
18#define S3C2410_SPCON_CPOL_HIGH	(1 << 2)	/* Clock polarity select */
19#define S3C2410_SPCON_CPOL_LOW	(0 << 2)	/* Clock polarity select */
20
21#define S3C2410_SPCON_CPHA_FMTB	(1 << 1)	/* Clock Phase Select */
22#define S3C2410_SPCON_CPHA_FMTA	(0 << 1)	/* Clock Phase Select */
23
24#define S3C2410_SPSTA		(0x04)
25
26#define S3C2410_SPSTA_DCOL	(1 << 2)	/* Data Collision Error */
27#define S3C2410_SPSTA_MULD	(1 << 1)	/* Multi Master Error */
28#define S3C2410_SPSTA_READY	(1 << 0)	/* Data Tx/Rx ready */
29#define S3C2412_SPSTA_READY_ORG	(1 << 3)
30
31#define S3C2410_SPPIN		(0x08)
32
33#define S3C2410_SPPIN_ENMUL	(1 << 2)	/* Multi Master Error detect */
34#define S3C2410_SPPIN_RESERVED	(1 << 1)
35#define S3C2410_SPPIN_KEEP	(1 << 0)	/* Master Out keep */
36
37#define S3C2410_SPPRE		(0x0C)
38#define S3C2410_SPTDAT		(0x10)
39#define S3C2410_SPRDAT		(0x14)
40
41#endif /* __SPI_S3C2410_H */