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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OMAP7xx SPI 100k controller driver
4 * Author: Fabrice Crohas <fcrohas@gmail.com>
5 * from original omap1_mcspi driver
6 *
7 * Copyright (C) 2005, 2006 Nokia Corporation
8 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
9 * Juha Yrjola <juha.yrjola@nokia.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/device.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include <linux/spi/spi.h>
25
26#define OMAP1_SPI100K_MAX_FREQ 48000000
27
28#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
29
30#define SPI_SETUP1 0x00
31#define SPI_SETUP2 0x02
32#define SPI_CTRL 0x04
33#define SPI_STATUS 0x06
34#define SPI_TX_LSB 0x08
35#define SPI_TX_MSB 0x0a
36#define SPI_RX_LSB 0x0c
37#define SPI_RX_MSB 0x0e
38
39#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
40#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
41#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
42#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
43
44#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
45#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
46#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
47#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
48#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
49#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
50
51#define SPI_CTRL_SEN(x) ((x) << 7)
52#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
53#define SPI_CTRL_WR (1UL << 1)
54#define SPI_CTRL_RD (1UL << 0)
55
56#define SPI_STATUS_WE (1UL << 1)
57#define SPI_STATUS_RD (1UL << 0)
58
59/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
60 * cache operations; better heuristics consider wordsize and bitrate.
61 */
62#define DMA_MIN_BYTES 8
63
64#define SPI_RUNNING 0
65#define SPI_SHUTDOWN 1
66
67struct omap1_spi100k {
68 struct clk *ick;
69 struct clk *fck;
70
71 /* Virtual base address of the controller */
72 void __iomem *base;
73};
74
75struct omap1_spi100k_cs {
76 void __iomem *base;
77 int word_len;
78};
79
80static void spi100k_enable_clock(struct spi_master *master)
81{
82 unsigned int val;
83 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
84
85 /* enable SPI */
86 val = readw(spi100k->base + SPI_SETUP1);
87 val |= SPI_SETUP1_CLOCK_ENABLE;
88 writew(val, spi100k->base + SPI_SETUP1);
89}
90
91static void spi100k_disable_clock(struct spi_master *master)
92{
93 unsigned int val;
94 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
95
96 /* disable SPI */
97 val = readw(spi100k->base + SPI_SETUP1);
98 val &= ~SPI_SETUP1_CLOCK_ENABLE;
99 writew(val, spi100k->base + SPI_SETUP1);
100}
101
102static void spi100k_write_data(struct spi_master *master, int len, int data)
103{
104 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
105
106 /* write 16-bit word, shifting 8-bit data if necessary */
107 if (len <= 8) {
108 data <<= 8;
109 len = 16;
110 }
111
112 spi100k_enable_clock(master);
113 writew(data, spi100k->base + SPI_TX_MSB);
114
115 writew(SPI_CTRL_SEN(0) |
116 SPI_CTRL_WORD_SIZE(len) |
117 SPI_CTRL_WR,
118 spi100k->base + SPI_CTRL);
119
120 /* Wait for bit ack send change */
121 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
122 ;
123 udelay(1000);
124
125 spi100k_disable_clock(master);
126}
127
128static int spi100k_read_data(struct spi_master *master, int len)
129{
130 int dataL;
131 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
132
133 /* Always do at least 16 bits */
134 if (len <= 8)
135 len = 16;
136
137 spi100k_enable_clock(master);
138 writew(SPI_CTRL_SEN(0) |
139 SPI_CTRL_WORD_SIZE(len) |
140 SPI_CTRL_RD,
141 spi100k->base + SPI_CTRL);
142
143 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
144 ;
145 udelay(1000);
146
147 dataL = readw(spi100k->base + SPI_RX_LSB);
148 readw(spi100k->base + SPI_RX_MSB);
149 spi100k_disable_clock(master);
150
151 return dataL;
152}
153
154static void spi100k_open(struct spi_master *master)
155{
156 /* get control of SPI */
157 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
158
159 writew(SPI_SETUP1_INT_READ_ENABLE |
160 SPI_SETUP1_INT_WRITE_ENABLE |
161 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
162
163 /* configure clock and interrupts */
164 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
165 SPI_SETUP2_NEGATIVE_LEVEL |
166 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
167}
168
169static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
170{
171 if (enable)
172 writew(0x05fc, spi100k->base + SPI_CTRL);
173 else
174 writew(0x05fd, spi100k->base + SPI_CTRL);
175}
176
177static unsigned
178omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
179{
180 struct omap1_spi100k_cs *cs = spi->controller_state;
181 unsigned int count, c;
182 int word_len;
183
184 count = xfer->len;
185 c = count;
186 word_len = cs->word_len;
187
188 if (word_len <= 8) {
189 u8 *rx;
190 const u8 *tx;
191
192 rx = xfer->rx_buf;
193 tx = xfer->tx_buf;
194 do {
195 c -= 1;
196 if (xfer->tx_buf != NULL)
197 spi100k_write_data(spi->master, word_len, *tx++);
198 if (xfer->rx_buf != NULL)
199 *rx++ = spi100k_read_data(spi->master, word_len);
200 } while (c);
201 } else if (word_len <= 16) {
202 u16 *rx;
203 const u16 *tx;
204
205 rx = xfer->rx_buf;
206 tx = xfer->tx_buf;
207 do {
208 c -= 2;
209 if (xfer->tx_buf != NULL)
210 spi100k_write_data(spi->master, word_len, *tx++);
211 if (xfer->rx_buf != NULL)
212 *rx++ = spi100k_read_data(spi->master, word_len);
213 } while (c);
214 } else if (word_len <= 32) {
215 u32 *rx;
216 const u32 *tx;
217
218 rx = xfer->rx_buf;
219 tx = xfer->tx_buf;
220 do {
221 c -= 4;
222 if (xfer->tx_buf != NULL)
223 spi100k_write_data(spi->master, word_len, *tx);
224 if (xfer->rx_buf != NULL)
225 *rx = spi100k_read_data(spi->master, word_len);
226 } while (c);
227 }
228 return count - c;
229}
230
231/* called only when no transfer is active to this device */
232static int omap1_spi100k_setup_transfer(struct spi_device *spi,
233 struct spi_transfer *t)
234{
235 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
236 struct omap1_spi100k_cs *cs = spi->controller_state;
237 u8 word_len;
238
239 if (t != NULL)
240 word_len = t->bits_per_word;
241 else
242 word_len = spi->bits_per_word;
243
244 if (word_len > 32)
245 return -EINVAL;
246 cs->word_len = word_len;
247
248 /* SPI init before transfer */
249 writew(0x3e, spi100k->base + SPI_SETUP1);
250 writew(0x00, spi100k->base + SPI_STATUS);
251 writew(0x3e, spi100k->base + SPI_CTRL);
252
253 return 0;
254}
255
256/* the spi->mode bits understood by this driver: */
257#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
258
259static int omap1_spi100k_setup(struct spi_device *spi)
260{
261 int ret;
262 struct omap1_spi100k *spi100k;
263 struct omap1_spi100k_cs *cs = spi->controller_state;
264
265 spi100k = spi_master_get_devdata(spi->master);
266
267 if (!cs) {
268 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
269 if (!cs)
270 return -ENOMEM;
271 cs->base = spi100k->base + spi->chip_select * 0x14;
272 spi->controller_state = cs;
273 }
274
275 spi100k_open(spi->master);
276
277 clk_prepare_enable(spi100k->ick);
278 clk_prepare_enable(spi100k->fck);
279
280 ret = omap1_spi100k_setup_transfer(spi, NULL);
281
282 clk_disable_unprepare(spi100k->ick);
283 clk_disable_unprepare(spi100k->fck);
284
285 return ret;
286}
287
288static int omap1_spi100k_transfer_one_message(struct spi_master *master,
289 struct spi_message *m)
290{
291 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
292 struct spi_device *spi = m->spi;
293 struct spi_transfer *t = NULL;
294 int cs_active = 0;
295 int status = 0;
296
297 list_for_each_entry(t, &m->transfers, transfer_list) {
298 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
299 break;
300 }
301 status = omap1_spi100k_setup_transfer(spi, t);
302 if (status < 0)
303 break;
304
305 if (!cs_active) {
306 omap1_spi100k_force_cs(spi100k, 1);
307 cs_active = 1;
308 }
309
310 if (t->len) {
311 unsigned count;
312
313 count = omap1_spi100k_txrx_pio(spi, t);
314 m->actual_length += count;
315
316 if (count != t->len) {
317 break;
318 }
319 }
320
321 spi_transfer_delay_exec(t);
322
323 /* ignore the "leave it on after last xfer" hint */
324
325 if (t->cs_change) {
326 omap1_spi100k_force_cs(spi100k, 0);
327 cs_active = 0;
328 }
329 }
330
331 status = omap1_spi100k_setup_transfer(spi, NULL);
332
333 if (cs_active)
334 omap1_spi100k_force_cs(spi100k, 0);
335
336 m->status = status;
337
338 spi_finalize_current_message(master);
339
340 return status;
341}
342
343static int omap1_spi100k_probe(struct platform_device *pdev)
344{
345 struct spi_master *master;
346 struct omap1_spi100k *spi100k;
347 int status = 0;
348
349 if (!pdev->id)
350 return -EINVAL;
351
352 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
353 if (master == NULL) {
354 dev_dbg(&pdev->dev, "master allocation failed\n");
355 return -ENOMEM;
356 }
357
358 if (pdev->id != -1)
359 master->bus_num = pdev->id;
360
361 master->setup = omap1_spi100k_setup;
362 master->transfer_one_message = omap1_spi100k_transfer_one_message;
363 master->num_chipselect = 2;
364 master->mode_bits = MODEBITS;
365 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
366 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
367 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
368 master->auto_runtime_pm = true;
369
370 spi100k = spi_master_get_devdata(master);
371
372 /*
373 * The memory region base address is taken as the platform_data.
374 * You should allocate this with ioremap() before initializing
375 * the SPI.
376 */
377 spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
378
379 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
380 if (IS_ERR(spi100k->ick)) {
381 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
382 status = PTR_ERR(spi100k->ick);
383 goto err;
384 }
385
386 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
387 if (IS_ERR(spi100k->fck)) {
388 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
389 status = PTR_ERR(spi100k->fck);
390 goto err;
391 }
392
393 status = clk_prepare_enable(spi100k->ick);
394 if (status != 0) {
395 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
396 goto err;
397 }
398
399 status = clk_prepare_enable(spi100k->fck);
400 if (status != 0) {
401 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
402 goto err_ick;
403 }
404
405 pm_runtime_enable(&pdev->dev);
406 pm_runtime_set_active(&pdev->dev);
407
408 status = devm_spi_register_master(&pdev->dev, master);
409 if (status < 0)
410 goto err_fck;
411
412 return status;
413
414err_fck:
415 pm_runtime_disable(&pdev->dev);
416 clk_disable_unprepare(spi100k->fck);
417err_ick:
418 clk_disable_unprepare(spi100k->ick);
419err:
420 spi_master_put(master);
421 return status;
422}
423
424static int omap1_spi100k_remove(struct platform_device *pdev)
425{
426 struct spi_master *master = platform_get_drvdata(pdev);
427 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
428
429 pm_runtime_disable(&pdev->dev);
430
431 clk_disable_unprepare(spi100k->fck);
432 clk_disable_unprepare(spi100k->ick);
433
434 return 0;
435}
436
437#ifdef CONFIG_PM
438static int omap1_spi100k_runtime_suspend(struct device *dev)
439{
440 struct spi_master *master = dev_get_drvdata(dev);
441 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
442
443 clk_disable_unprepare(spi100k->ick);
444 clk_disable_unprepare(spi100k->fck);
445
446 return 0;
447}
448
449static int omap1_spi100k_runtime_resume(struct device *dev)
450{
451 struct spi_master *master = dev_get_drvdata(dev);
452 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
453 int ret;
454
455 ret = clk_prepare_enable(spi100k->ick);
456 if (ret != 0) {
457 dev_err(dev, "Failed to enable ick: %d\n", ret);
458 return ret;
459 }
460
461 ret = clk_prepare_enable(spi100k->fck);
462 if (ret != 0) {
463 dev_err(dev, "Failed to enable fck: %d\n", ret);
464 clk_disable_unprepare(spi100k->ick);
465 return ret;
466 }
467
468 return 0;
469}
470#endif
471
472static const struct dev_pm_ops omap1_spi100k_pm = {
473 SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
474 omap1_spi100k_runtime_resume, NULL)
475};
476
477static struct platform_driver omap1_spi100k_driver = {
478 .driver = {
479 .name = "omap1_spi100k",
480 .pm = &omap1_spi100k_pm,
481 },
482 .probe = omap1_spi100k_probe,
483 .remove = omap1_spi100k_remove,
484};
485
486module_platform_driver(omap1_spi100k_driver);
487
488MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
489MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
490MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OMAP7xx SPI 100k controller driver
4 * Author: Fabrice Crohas <fcrohas@gmail.com>
5 * from original omap1_mcspi driver
6 *
7 * Copyright (C) 2005, 2006 Nokia Corporation
8 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
9 * Juha Yrj�l� <juha.yrjola@nokia.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/device.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/slab.h>
24
25#include <linux/spi/spi.h>
26
27#define OMAP1_SPI100K_MAX_FREQ 48000000
28
29#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
30
31#define SPI_SETUP1 0x00
32#define SPI_SETUP2 0x02
33#define SPI_CTRL 0x04
34#define SPI_STATUS 0x06
35#define SPI_TX_LSB 0x08
36#define SPI_TX_MSB 0x0a
37#define SPI_RX_LSB 0x0c
38#define SPI_RX_MSB 0x0e
39
40#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
41#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
42#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
43#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
44
45#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
46#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
47#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
48#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
49#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
50#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
51
52#define SPI_CTRL_SEN(x) ((x) << 7)
53#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
54#define SPI_CTRL_WR (1UL << 1)
55#define SPI_CTRL_RD (1UL << 0)
56
57#define SPI_STATUS_WE (1UL << 1)
58#define SPI_STATUS_RD (1UL << 0)
59
60/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
61 * cache operations; better heuristics consider wordsize and bitrate.
62 */
63#define DMA_MIN_BYTES 8
64
65#define SPI_RUNNING 0
66#define SPI_SHUTDOWN 1
67
68struct omap1_spi100k {
69 struct clk *ick;
70 struct clk *fck;
71
72 /* Virtual base address of the controller */
73 void __iomem *base;
74};
75
76struct omap1_spi100k_cs {
77 void __iomem *base;
78 int word_len;
79};
80
81static void spi100k_enable_clock(struct spi_master *master)
82{
83 unsigned int val;
84 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
85
86 /* enable SPI */
87 val = readw(spi100k->base + SPI_SETUP1);
88 val |= SPI_SETUP1_CLOCK_ENABLE;
89 writew(val, spi100k->base + SPI_SETUP1);
90}
91
92static void spi100k_disable_clock(struct spi_master *master)
93{
94 unsigned int val;
95 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
96
97 /* disable SPI */
98 val = readw(spi100k->base + SPI_SETUP1);
99 val &= ~SPI_SETUP1_CLOCK_ENABLE;
100 writew(val, spi100k->base + SPI_SETUP1);
101}
102
103static void spi100k_write_data(struct spi_master *master, int len, int data)
104{
105 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
106
107 /* write 16-bit word, shifting 8-bit data if necessary */
108 if (len <= 8) {
109 data <<= 8;
110 len = 16;
111 }
112
113 spi100k_enable_clock(master);
114 writew(data , spi100k->base + SPI_TX_MSB);
115
116 writew(SPI_CTRL_SEN(0) |
117 SPI_CTRL_WORD_SIZE(len) |
118 SPI_CTRL_WR,
119 spi100k->base + SPI_CTRL);
120
121 /* Wait for bit ack send change */
122 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
123 ;
124 udelay(1000);
125
126 spi100k_disable_clock(master);
127}
128
129static int spi100k_read_data(struct spi_master *master, int len)
130{
131 int dataH, dataL;
132 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
133
134 /* Always do at least 16 bits */
135 if (len <= 8)
136 len = 16;
137
138 spi100k_enable_clock(master);
139 writew(SPI_CTRL_SEN(0) |
140 SPI_CTRL_WORD_SIZE(len) |
141 SPI_CTRL_RD,
142 spi100k->base + SPI_CTRL);
143
144 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
145 ;
146 udelay(1000);
147
148 dataL = readw(spi100k->base + SPI_RX_LSB);
149 dataH = readw(spi100k->base + SPI_RX_MSB);
150 spi100k_disable_clock(master);
151
152 return dataL;
153}
154
155static void spi100k_open(struct spi_master *master)
156{
157 /* get control of SPI */
158 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
159
160 writew(SPI_SETUP1_INT_READ_ENABLE |
161 SPI_SETUP1_INT_WRITE_ENABLE |
162 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
163
164 /* configure clock and interrupts */
165 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
166 SPI_SETUP2_NEGATIVE_LEVEL |
167 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
168}
169
170static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
171{
172 if (enable)
173 writew(0x05fc, spi100k->base + SPI_CTRL);
174 else
175 writew(0x05fd, spi100k->base + SPI_CTRL);
176}
177
178static unsigned
179omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
180{
181 struct omap1_spi100k_cs *cs = spi->controller_state;
182 unsigned int count, c;
183 int word_len;
184
185 count = xfer->len;
186 c = count;
187 word_len = cs->word_len;
188
189 if (word_len <= 8) {
190 u8 *rx;
191 const u8 *tx;
192
193 rx = xfer->rx_buf;
194 tx = xfer->tx_buf;
195 do {
196 c -= 1;
197 if (xfer->tx_buf != NULL)
198 spi100k_write_data(spi->master, word_len, *tx++);
199 if (xfer->rx_buf != NULL)
200 *rx++ = spi100k_read_data(spi->master, word_len);
201 } while (c);
202 } else if (word_len <= 16) {
203 u16 *rx;
204 const u16 *tx;
205
206 rx = xfer->rx_buf;
207 tx = xfer->tx_buf;
208 do {
209 c -= 2;
210 if (xfer->tx_buf != NULL)
211 spi100k_write_data(spi->master, word_len, *tx++);
212 if (xfer->rx_buf != NULL)
213 *rx++ = spi100k_read_data(spi->master, word_len);
214 } while (c);
215 } else if (word_len <= 32) {
216 u32 *rx;
217 const u32 *tx;
218
219 rx = xfer->rx_buf;
220 tx = xfer->tx_buf;
221 do {
222 c -= 4;
223 if (xfer->tx_buf != NULL)
224 spi100k_write_data(spi->master, word_len, *tx);
225 if (xfer->rx_buf != NULL)
226 *rx = spi100k_read_data(spi->master, word_len);
227 } while (c);
228 }
229 return count - c;
230}
231
232/* called only when no transfer is active to this device */
233static int omap1_spi100k_setup_transfer(struct spi_device *spi,
234 struct spi_transfer *t)
235{
236 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
237 struct omap1_spi100k_cs *cs = spi->controller_state;
238 u8 word_len;
239
240 if (t != NULL)
241 word_len = t->bits_per_word;
242 else
243 word_len = spi->bits_per_word;
244
245 if (spi->bits_per_word > 32)
246 return -EINVAL;
247 cs->word_len = word_len;
248
249 /* SPI init before transfer */
250 writew(0x3e , spi100k->base + SPI_SETUP1);
251 writew(0x00 , spi100k->base + SPI_STATUS);
252 writew(0x3e , spi100k->base + SPI_CTRL);
253
254 return 0;
255}
256
257/* the spi->mode bits understood by this driver: */
258#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
259
260static int omap1_spi100k_setup(struct spi_device *spi)
261{
262 int ret;
263 struct omap1_spi100k *spi100k;
264 struct omap1_spi100k_cs *cs = spi->controller_state;
265
266 spi100k = spi_master_get_devdata(spi->master);
267
268 if (!cs) {
269 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
270 if (!cs)
271 return -ENOMEM;
272 cs->base = spi100k->base + spi->chip_select * 0x14;
273 spi->controller_state = cs;
274 }
275
276 spi100k_open(spi->master);
277
278 clk_prepare_enable(spi100k->ick);
279 clk_prepare_enable(spi100k->fck);
280
281 ret = omap1_spi100k_setup_transfer(spi, NULL);
282
283 clk_disable_unprepare(spi100k->ick);
284 clk_disable_unprepare(spi100k->fck);
285
286 return ret;
287}
288
289static int omap1_spi100k_transfer_one_message(struct spi_master *master,
290 struct spi_message *m)
291{
292 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
293 struct spi_device *spi = m->spi;
294 struct spi_transfer *t = NULL;
295 int cs_active = 0;
296 int status = 0;
297
298 list_for_each_entry(t, &m->transfers, transfer_list) {
299 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
300 status = -EINVAL;
301 break;
302 }
303 status = omap1_spi100k_setup_transfer(spi, t);
304 if (status < 0)
305 break;
306
307 if (!cs_active) {
308 omap1_spi100k_force_cs(spi100k, 1);
309 cs_active = 1;
310 }
311
312 if (t->len) {
313 unsigned count;
314
315 count = omap1_spi100k_txrx_pio(spi, t);
316 m->actual_length += count;
317
318 if (count != t->len) {
319 status = -EIO;
320 break;
321 }
322 }
323
324 if (t->delay_usecs)
325 udelay(t->delay_usecs);
326
327 /* ignore the "leave it on after last xfer" hint */
328
329 if (t->cs_change) {
330 omap1_spi100k_force_cs(spi100k, 0);
331 cs_active = 0;
332 }
333 }
334
335 status = omap1_spi100k_setup_transfer(spi, NULL);
336
337 if (cs_active)
338 omap1_spi100k_force_cs(spi100k, 0);
339
340 m->status = status;
341
342 spi_finalize_current_message(master);
343
344 return status;
345}
346
347static int omap1_spi100k_probe(struct platform_device *pdev)
348{
349 struct spi_master *master;
350 struct omap1_spi100k *spi100k;
351 int status = 0;
352
353 if (!pdev->id)
354 return -EINVAL;
355
356 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
357 if (master == NULL) {
358 dev_dbg(&pdev->dev, "master allocation failed\n");
359 return -ENOMEM;
360 }
361
362 if (pdev->id != -1)
363 master->bus_num = pdev->id;
364
365 master->setup = omap1_spi100k_setup;
366 master->transfer_one_message = omap1_spi100k_transfer_one_message;
367 master->num_chipselect = 2;
368 master->mode_bits = MODEBITS;
369 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
370 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
371 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
372 master->auto_runtime_pm = true;
373
374 spi100k = spi_master_get_devdata(master);
375
376 /*
377 * The memory region base address is taken as the platform_data.
378 * You should allocate this with ioremap() before initializing
379 * the SPI.
380 */
381 spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
382
383 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
384 if (IS_ERR(spi100k->ick)) {
385 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
386 status = PTR_ERR(spi100k->ick);
387 goto err;
388 }
389
390 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
391 if (IS_ERR(spi100k->fck)) {
392 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
393 status = PTR_ERR(spi100k->fck);
394 goto err;
395 }
396
397 status = clk_prepare_enable(spi100k->ick);
398 if (status != 0) {
399 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
400 goto err;
401 }
402
403 status = clk_prepare_enable(spi100k->fck);
404 if (status != 0) {
405 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
406 goto err_ick;
407 }
408
409 pm_runtime_enable(&pdev->dev);
410 pm_runtime_set_active(&pdev->dev);
411
412 status = devm_spi_register_master(&pdev->dev, master);
413 if (status < 0)
414 goto err_fck;
415
416 return status;
417
418err_fck:
419 clk_disable_unprepare(spi100k->fck);
420err_ick:
421 clk_disable_unprepare(spi100k->ick);
422err:
423 spi_master_put(master);
424 return status;
425}
426
427static int omap1_spi100k_remove(struct platform_device *pdev)
428{
429 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
430 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
431
432 pm_runtime_disable(&pdev->dev);
433
434 clk_disable_unprepare(spi100k->fck);
435 clk_disable_unprepare(spi100k->ick);
436
437 return 0;
438}
439
440#ifdef CONFIG_PM
441static int omap1_spi100k_runtime_suspend(struct device *dev)
442{
443 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
444 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
445
446 clk_disable_unprepare(spi100k->ick);
447 clk_disable_unprepare(spi100k->fck);
448
449 return 0;
450}
451
452static int omap1_spi100k_runtime_resume(struct device *dev)
453{
454 struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
455 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
456 int ret;
457
458 ret = clk_prepare_enable(spi100k->ick);
459 if (ret != 0) {
460 dev_err(dev, "Failed to enable ick: %d\n", ret);
461 return ret;
462 }
463
464 ret = clk_prepare_enable(spi100k->fck);
465 if (ret != 0) {
466 dev_err(dev, "Failed to enable fck: %d\n", ret);
467 clk_disable_unprepare(spi100k->ick);
468 return ret;
469 }
470
471 return 0;
472}
473#endif
474
475static const struct dev_pm_ops omap1_spi100k_pm = {
476 SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
477 omap1_spi100k_runtime_resume, NULL)
478};
479
480static struct platform_driver omap1_spi100k_driver = {
481 .driver = {
482 .name = "omap1_spi100k",
483 .pm = &omap1_spi100k_pm,
484 },
485 .probe = omap1_spi100k_probe,
486 .remove = omap1_spi100k_remove,
487};
488
489module_platform_driver(omap1_spi100k_driver);
490
491MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
492MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
493MODULE_LICENSE("GPL");