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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SPI_DW_H__
3#define __SPI_DW_H__
4
5#include <linux/bits.h>
6#include <linux/completion.h>
7#include <linux/debugfs.h>
8#include <linux/irqreturn.h>
9#include <linux/io.h>
10#include <linux/scatterlist.h>
11#include <linux/spi/spi-mem.h>
12#include <linux/bitfield.h>
13
14/* Synopsys DW SSI IP-core virtual IDs */
15#define DW_PSSI_ID 0
16#define DW_HSSI_ID 1
17
18/* Synopsys DW SSI component versions (FourCC sequence) */
19#define DW_HSSI_102A 0x3130322a
20
21/* DW SSI IP-core ID and version check helpers */
22#define dw_spi_ip_is(_dws, _ip) \
23 ((_dws)->ip == DW_ ## _ip ## _ID)
24
25#define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
27
28#define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
29
30#define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)
31
32/* DW SPI controller capabilities */
33#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
34#define DW_SPI_CAP_DFS32 BIT(1)
35
36/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
37#define DW_SPI_CTRLR0 0x00
38#define DW_SPI_CTRLR1 0x04
39#define DW_SPI_SSIENR 0x08
40#define DW_SPI_MWCR 0x0c
41#define DW_SPI_SER 0x10
42#define DW_SPI_BAUDR 0x14
43#define DW_SPI_TXFTLR 0x18
44#define DW_SPI_RXFTLR 0x1c
45#define DW_SPI_TXFLR 0x20
46#define DW_SPI_RXFLR 0x24
47#define DW_SPI_SR 0x28
48#define DW_SPI_IMR 0x2c
49#define DW_SPI_ISR 0x30
50#define DW_SPI_RISR 0x34
51#define DW_SPI_TXOICR 0x38
52#define DW_SPI_RXOICR 0x3c
53#define DW_SPI_RXUICR 0x40
54#define DW_SPI_MSTICR 0x44
55#define DW_SPI_ICR 0x48
56#define DW_SPI_DMACR 0x4c
57#define DW_SPI_DMATDLR 0x50
58#define DW_SPI_DMARDLR 0x54
59#define DW_SPI_IDR 0x58
60#define DW_SPI_VERSION 0x5c
61#define DW_SPI_DR 0x60
62#define DW_SPI_RX_SAMPLE_DLY 0xf0
63#define DW_SPI_CS_OVERRIDE 0xf4
64
65/* Bit fields in CTRLR0 (DWC APB SSI) */
66#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
67#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
68
69#define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4)
70#define DW_SPI_CTRLR0_FRF_MOTO_SPI 0x0
71#define DW_SPI_CTRLR0_FRF_TI_SSP 0x1
72#define DW_SPI_CTRLR0_FRF_NS_MICROWIRE 0x2
73#define DW_SPI_CTRLR0_FRF_RESV 0x3
74
75#define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6)
76#define DW_PSSI_CTRLR0_SCPHA BIT(6)
77#define DW_PSSI_CTRLR0_SCPOL BIT(7)
78
79#define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8)
80#define DW_SPI_CTRLR0_TMOD_TR 0x0 /* xmit & recv */
81#define DW_SPI_CTRLR0_TMOD_TO 0x1 /* xmit only */
82#define DW_SPI_CTRLR0_TMOD_RO 0x2 /* recv only */
83#define DW_SPI_CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
84
85#define DW_PSSI_CTRLR0_SLV_OE BIT(10)
86#define DW_PSSI_CTRLR0_SRL BIT(11)
87#define DW_PSSI_CTRLR0_CFS BIT(12)
88
89/* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
90#define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0)
91#define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6)
92#define DW_HSSI_CTRLR0_SCPHA BIT(8)
93#define DW_HSSI_CTRLR0_SCPOL BIT(9)
94#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
95#define DW_HSSI_CTRLR0_SRL BIT(13)
96#define DW_HSSI_CTRLR0_MST BIT(31)
97
98/* Bit fields in CTRLR1 */
99#define DW_SPI_NDF_MASK GENMASK(15, 0)
100
101/* Bit fields in SR, 7 bits */
102#define DW_SPI_SR_MASK GENMASK(6, 0)
103#define DW_SPI_SR_BUSY BIT(0)
104#define DW_SPI_SR_TF_NOT_FULL BIT(1)
105#define DW_SPI_SR_TF_EMPT BIT(2)
106#define DW_SPI_SR_RF_NOT_EMPT BIT(3)
107#define DW_SPI_SR_RF_FULL BIT(4)
108#define DW_SPI_SR_TX_ERR BIT(5)
109#define DW_SPI_SR_DCOL BIT(6)
110
111/* Bit fields in ISR, IMR, RISR, 7 bits */
112#define DW_SPI_INT_MASK GENMASK(5, 0)
113#define DW_SPI_INT_TXEI BIT(0)
114#define DW_SPI_INT_TXOI BIT(1)
115#define DW_SPI_INT_RXUI BIT(2)
116#define DW_SPI_INT_RXOI BIT(3)
117#define DW_SPI_INT_RXFI BIT(4)
118#define DW_SPI_INT_MSTI BIT(5)
119
120/* Bit fields in DMACR */
121#define DW_SPI_DMACR_RDMAE BIT(0)
122#define DW_SPI_DMACR_TDMAE BIT(1)
123
124/* Mem/DMA operations helpers */
125#define DW_SPI_WAIT_RETRIES 5
126#define DW_SPI_BUF_SIZE \
127 (sizeof_field(struct spi_mem_op, cmd.opcode) + \
128 sizeof_field(struct spi_mem_op, addr.val) + 256)
129#define DW_SPI_GET_BYTE(_val, _idx) \
130 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
131
132/* Slave spi_transfer/spi_mem_op related */
133struct dw_spi_cfg {
134 u8 tmode;
135 u8 dfs;
136 u32 ndf;
137 u32 freq;
138};
139
140struct dw_spi;
141struct dw_spi_dma_ops {
142 int (*dma_init)(struct device *dev, struct dw_spi *dws);
143 void (*dma_exit)(struct dw_spi *dws);
144 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
145 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
146 struct spi_transfer *xfer);
147 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
148 void (*dma_stop)(struct dw_spi *dws);
149};
150
151struct dw_spi {
152 struct spi_controller *master;
153
154 u32 ip; /* Synopsys DW SSI IP-core ID */
155 u32 ver; /* Synopsys component version */
156 u32 caps; /* DW SPI capabilities */
157
158 void __iomem *regs;
159 unsigned long paddr;
160 int irq;
161 u32 fifo_len; /* depth of the FIFO buffer */
162 unsigned int dfs_offset; /* CTRLR0 DFS field offset */
163 u32 max_mem_freq; /* max mem-ops bus freq */
164 u32 max_freq; /* max bus freq supported */
165
166 u32 reg_io_width; /* DR I/O width in bytes */
167 u16 bus_num;
168 u16 num_cs; /* supported slave numbers */
169 void (*set_cs)(struct spi_device *spi, bool enable);
170
171 /* Current message transfer state info */
172 void *tx;
173 unsigned int tx_len;
174 void *rx;
175 unsigned int rx_len;
176 u8 buf[DW_SPI_BUF_SIZE];
177 int dma_mapped;
178 u8 n_bytes; /* current is a 1/2 bytes op */
179 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
180 u32 current_freq; /* frequency in hz */
181 u32 cur_rx_sample_dly;
182 u32 def_rx_sample_dly_ns;
183
184 /* Custom memory operations */
185 struct spi_controller_mem_ops mem_ops;
186
187 /* DMA info */
188 struct dma_chan *txchan;
189 u32 txburst;
190 struct dma_chan *rxchan;
191 u32 rxburst;
192 u32 dma_sg_burst;
193 unsigned long dma_chan_busy;
194 dma_addr_t dma_addr; /* phy address of the Data register */
195 const struct dw_spi_dma_ops *dma_ops;
196 struct completion dma_completion;
197
198#ifdef CONFIG_DEBUG_FS
199 struct dentry *debugfs;
200 struct debugfs_regset32 regset;
201#endif
202};
203
204static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
205{
206 return __raw_readl(dws->regs + offset);
207}
208
209static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
210{
211 __raw_writel(val, dws->regs + offset);
212}
213
214static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
215{
216 switch (dws->reg_io_width) {
217 case 2:
218 return readw_relaxed(dws->regs + offset);
219 case 4:
220 default:
221 return readl_relaxed(dws->regs + offset);
222 }
223}
224
225static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
226{
227 switch (dws->reg_io_width) {
228 case 2:
229 writew_relaxed(val, dws->regs + offset);
230 break;
231 case 4:
232 default:
233 writel_relaxed(val, dws->regs + offset);
234 break;
235 }
236}
237
238static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
239{
240 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
241}
242
243static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
244{
245 dw_writel(dws, DW_SPI_BAUDR, div);
246}
247
248/* Disable IRQ bits */
249static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
250{
251 u32 new_mask;
252
253 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
254 dw_writel(dws, DW_SPI_IMR, new_mask);
255}
256
257/* Enable IRQ bits */
258static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
259{
260 u32 new_mask;
261
262 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
263 dw_writel(dws, DW_SPI_IMR, new_mask);
264}
265
266/*
267 * This disables the SPI controller, interrupts, clears the interrupts status
268 * and CS, then re-enables the controller back. Transmit and receive FIFO
269 * buffers are cleared when the device is disabled.
270 */
271static inline void dw_spi_reset_chip(struct dw_spi *dws)
272{
273 dw_spi_enable_chip(dws, 0);
274 dw_spi_mask_intr(dws, 0xff);
275 dw_readl(dws, DW_SPI_ICR);
276 dw_writel(dws, DW_SPI_SER, 0);
277 dw_spi_enable_chip(dws, 1);
278}
279
280static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
281{
282 dw_spi_enable_chip(dws, 0);
283 dw_spi_set_clk(dws, 0);
284}
285
286extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
287extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
288 struct dw_spi_cfg *cfg);
289extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
290extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
291extern void dw_spi_remove_host(struct dw_spi *dws);
292extern int dw_spi_suspend_host(struct dw_spi *dws);
293extern int dw_spi_resume_host(struct dw_spi *dws);
294
295#ifdef CONFIG_SPI_DW_DMA
296
297extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
298extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
299
300#else
301
302static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
303static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
304
305#endif /* !CONFIG_SPI_DW_DMA */
306
307#endif /* __SPI_DW_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DW_SPI_HEADER_H
3#define DW_SPI_HEADER_H
4
5#include <linux/io.h>
6#include <linux/scatterlist.h>
7#include <linux/gpio.h>
8
9/* Register offsets */
10#define DW_SPI_CTRL0 0x00
11#define DW_SPI_CTRL1 0x04
12#define DW_SPI_SSIENR 0x08
13#define DW_SPI_MWCR 0x0c
14#define DW_SPI_SER 0x10
15#define DW_SPI_BAUDR 0x14
16#define DW_SPI_TXFLTR 0x18
17#define DW_SPI_RXFLTR 0x1c
18#define DW_SPI_TXFLR 0x20
19#define DW_SPI_RXFLR 0x24
20#define DW_SPI_SR 0x28
21#define DW_SPI_IMR 0x2c
22#define DW_SPI_ISR 0x30
23#define DW_SPI_RISR 0x34
24#define DW_SPI_TXOICR 0x38
25#define DW_SPI_RXOICR 0x3c
26#define DW_SPI_RXUICR 0x40
27#define DW_SPI_MSTICR 0x44
28#define DW_SPI_ICR 0x48
29#define DW_SPI_DMACR 0x4c
30#define DW_SPI_DMATDLR 0x50
31#define DW_SPI_DMARDLR 0x54
32#define DW_SPI_IDR 0x58
33#define DW_SPI_VERSION 0x5c
34#define DW_SPI_DR 0x60
35#define DW_SPI_CS_OVERRIDE 0xf4
36
37/* Bit fields in CTRLR0 */
38#define SPI_DFS_OFFSET 0
39
40#define SPI_FRF_OFFSET 4
41#define SPI_FRF_SPI 0x0
42#define SPI_FRF_SSP 0x1
43#define SPI_FRF_MICROWIRE 0x2
44#define SPI_FRF_RESV 0x3
45
46#define SPI_MODE_OFFSET 6
47#define SPI_SCPH_OFFSET 6
48#define SPI_SCOL_OFFSET 7
49
50#define SPI_TMOD_OFFSET 8
51#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
52#define SPI_TMOD_TR 0x0 /* xmit & recv */
53#define SPI_TMOD_TO 0x1 /* xmit only */
54#define SPI_TMOD_RO 0x2 /* recv only */
55#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
56
57#define SPI_SLVOE_OFFSET 10
58#define SPI_SRL_OFFSET 11
59#define SPI_CFS_OFFSET 12
60
61/* Bit fields in SR, 7 bits */
62#define SR_MASK 0x7f /* cover 7 bits */
63#define SR_BUSY (1 << 0)
64#define SR_TF_NOT_FULL (1 << 1)
65#define SR_TF_EMPT (1 << 2)
66#define SR_RF_NOT_EMPT (1 << 3)
67#define SR_RF_FULL (1 << 4)
68#define SR_TX_ERR (1 << 5)
69#define SR_DCOL (1 << 6)
70
71/* Bit fields in ISR, IMR, RISR, 7 bits */
72#define SPI_INT_TXEI (1 << 0)
73#define SPI_INT_TXOI (1 << 1)
74#define SPI_INT_RXUI (1 << 2)
75#define SPI_INT_RXOI (1 << 3)
76#define SPI_INT_RXFI (1 << 4)
77#define SPI_INT_MSTI (1 << 5)
78
79/* Bit fields in DMACR */
80#define SPI_DMA_RDMAE (1 << 0)
81#define SPI_DMA_TDMAE (1 << 1)
82
83/* TX RX interrupt level threshold, max can be 256 */
84#define SPI_INT_THRESHOLD 32
85
86enum dw_ssi_type {
87 SSI_MOTO_SPI = 0,
88 SSI_TI_SSP,
89 SSI_NS_MICROWIRE,
90};
91
92struct dw_spi;
93struct dw_spi_dma_ops {
94 int (*dma_init)(struct dw_spi *dws);
95 void (*dma_exit)(struct dw_spi *dws);
96 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
97 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
98 struct spi_transfer *xfer);
99 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
100 void (*dma_stop)(struct dw_spi *dws);
101};
102
103struct dw_spi {
104 struct spi_controller *master;
105 enum dw_ssi_type type;
106
107 void __iomem *regs;
108 unsigned long paddr;
109 int irq;
110 u32 fifo_len; /* depth of the FIFO buffer */
111 u32 max_freq; /* max bus freq supported */
112
113 int cs_override;
114 u32 reg_io_width; /* DR I/O width in bytes */
115 u16 bus_num;
116 u16 num_cs; /* supported slave numbers */
117 void (*set_cs)(struct spi_device *spi, bool enable);
118
119 /* Current message transfer state info */
120 size_t len;
121 void *tx;
122 void *tx_end;
123 void *rx;
124 void *rx_end;
125 int dma_mapped;
126 u8 n_bytes; /* current is a 1/2 bytes op */
127 u32 dma_width;
128 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
129 u32 current_freq; /* frequency in hz */
130
131 /* DMA info */
132 int dma_inited;
133 struct dma_chan *txchan;
134 struct dma_chan *rxchan;
135 unsigned long dma_chan_busy;
136 dma_addr_t dma_addr; /* phy address of the Data register */
137 const struct dw_spi_dma_ops *dma_ops;
138 void *dma_tx;
139 void *dma_rx;
140
141 /* Bus interface info */
142 void *priv;
143#ifdef CONFIG_DEBUG_FS
144 struct dentry *debugfs;
145#endif
146};
147
148static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
149{
150 return __raw_readl(dws->regs + offset);
151}
152
153static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
154{
155 return __raw_readw(dws->regs + offset);
156}
157
158static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
159{
160 __raw_writel(val, dws->regs + offset);
161}
162
163static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
164{
165 __raw_writew(val, dws->regs + offset);
166}
167
168static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
169{
170 switch (dws->reg_io_width) {
171 case 2:
172 return dw_readw(dws, offset);
173 case 4:
174 default:
175 return dw_readl(dws, offset);
176 }
177}
178
179static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
180{
181 switch (dws->reg_io_width) {
182 case 2:
183 dw_writew(dws, offset, val);
184 break;
185 case 4:
186 default:
187 dw_writel(dws, offset, val);
188 break;
189 }
190}
191
192static inline void spi_enable_chip(struct dw_spi *dws, int enable)
193{
194 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
195}
196
197static inline void spi_set_clk(struct dw_spi *dws, u16 div)
198{
199 dw_writel(dws, DW_SPI_BAUDR, div);
200}
201
202/* Disable IRQ bits */
203static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
204{
205 u32 new_mask;
206
207 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
208 dw_writel(dws, DW_SPI_IMR, new_mask);
209}
210
211/* Enable IRQ bits */
212static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
213{
214 u32 new_mask;
215
216 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
217 dw_writel(dws, DW_SPI_IMR, new_mask);
218}
219
220/*
221 * This does disable the SPI controller, interrupts, and re-enable the
222 * controller back. Transmit and receive FIFO buffers are cleared when the
223 * device is disabled.
224 */
225static inline void spi_reset_chip(struct dw_spi *dws)
226{
227 spi_enable_chip(dws, 0);
228 spi_mask_intr(dws, 0xff);
229 spi_enable_chip(dws, 1);
230}
231
232static inline void spi_shutdown_chip(struct dw_spi *dws)
233{
234 spi_enable_chip(dws, 0);
235 spi_set_clk(dws, 0);
236}
237
238/*
239 * Each SPI slave device to work with dw_api controller should
240 * has such a structure claiming its working mode (poll or PIO/DMA),
241 * which can be save in the "controller_data" member of the
242 * struct spi_device.
243 */
244struct dw_spi_chip {
245 u8 poll_mode; /* 1 for controller polling mode */
246 u8 type; /* SPI/SSP/MicroWire */
247 void (*cs_control)(u32 command);
248};
249
250extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
251extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
252extern void dw_spi_remove_host(struct dw_spi *dws);
253extern int dw_spi_suspend_host(struct dw_spi *dws);
254extern int dw_spi_resume_host(struct dw_spi *dws);
255
256/* platform related setup */
257extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
258#endif /* DW_SPI_HEADER_H */