1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Meson G12A MIPI DSI Analog PHY
  4 *
  5 * Copyright (C) 2018 Amlogic, Inc. All rights reserved
  6 * Copyright (C) 2022 BayLibre, SAS
  7 * Author: Neil Armstrong <narmstrong@baylibre.com>
  8 */
  9#include <linux/bitfield.h>
 10#include <linux/bitops.h>
 11#include <linux/module.h>
 12#include <linux/phy/phy.h>
 13#include <linux/regmap.h>
 14#include <linux/delay.h>
 15#include <linux/mfd/syscon.h>
 16#include <linux/platform_device.h>
 17#include <dt-bindings/phy/phy.h>
 18
 19#define HHI_MIPI_CNTL0 0x00
 20#define		HHI_MIPI_CNTL0_DIF_REF_CTL1	GENMASK(31, 16)
 21#define		HHI_MIPI_CNTL0_DIF_REF_CTL0	GENMASK(15, 0)
 22
 23#define HHI_MIPI_CNTL1 0x04
 24#define		HHI_MIPI_CNTL1_BANDGAP		BIT(16)
 25#define		HHI_MIPI_CNTL2_DIF_REF_CTL2	GENMASK(15, 0)
 26
 27#define HHI_MIPI_CNTL2 0x08
 28#define		HHI_MIPI_CNTL2_DIF_TX_CTL1	GENMASK(31, 16)
 29#define		HHI_MIPI_CNTL2_CH_EN		GENMASK(15, 11)
 30#define		HHI_MIPI_CNTL2_DIF_TX_CTL0	GENMASK(10, 0)
 31
 32#define DSI_LANE_0				BIT(4)
 33#define DSI_LANE_1				BIT(3)
 34#define DSI_LANE_CLK				BIT(2)
 35#define DSI_LANE_2				BIT(1)
 36#define DSI_LANE_3				BIT(0)
 37
 38struct phy_g12a_mipi_dphy_analog_priv {
 39	struct phy *phy;
 40	struct regmap *regmap;
 41	struct phy_configure_opts_mipi_dphy config;
 42};
 43
 44static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
 45					       union phy_configure_opts *opts)
 46{
 47	struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
 48	int ret;
 49
 50	ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
 51	if (ret)
 52		return ret;
 53
 54	memcpy(&priv->config, opts, sizeof(priv->config));
 55
 56	return 0;
 57}
 58
 59static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
 60{
 61	struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
 62	unsigned int reg;
 63
 64	regmap_write(priv->regmap, HHI_MIPI_CNTL0,
 65		     FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
 66		     FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
 67
 68	regmap_write(priv->regmap, HHI_MIPI_CNTL1,
 69		     FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
 70		     HHI_MIPI_CNTL1_BANDGAP);
 71
 72	regmap_write(priv->regmap, HHI_MIPI_CNTL2,
 73		     FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
 74		     FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
 75
 76	reg = DSI_LANE_CLK;
 77	switch (priv->config.lanes) {
 78	case 4:
 79		reg |= DSI_LANE_3;
 80		fallthrough;
 81	case 3:
 82		reg |= DSI_LANE_2;
 83		fallthrough;
 84	case 2:
 85		reg |= DSI_LANE_1;
 86		fallthrough;
 87	case 1:
 88		reg |= DSI_LANE_0;
 89		break;
 90	default:
 91		reg = 0;
 92	}
 93
 94	regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
 95			   HHI_MIPI_CNTL2_CH_EN,
 96			   FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
 97
 98	return 0;
 99}
100
101static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
102{
103	struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
104
105	regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
106	regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
107	regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
108
109	return 0;
110}
111
112static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
113	.configure = phy_g12a_mipi_dphy_analog_configure,
114	.power_on = phy_g12a_mipi_dphy_analog_power_on,
115	.power_off = phy_g12a_mipi_dphy_analog_power_off,
116	.owner = THIS_MODULE,
117};
118
119static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
120{
121	struct phy_provider *phy;
122	struct device *dev = &pdev->dev;
123	struct phy_g12a_mipi_dphy_analog_priv *priv;
124	struct device_node *np = dev->of_node, *parent_np;
125	struct regmap *map;
126
127	priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
128	if (!priv)
129		return -ENOMEM;
130
131	/* Get the hhi system controller node */
132	parent_np = of_get_parent(np);
133	map = syscon_node_to_regmap(parent_np);
134	of_node_put(parent_np);
135	if (IS_ERR(map))
136		return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
137
138	priv->regmap = map;
139
140	priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
141	if (IS_ERR(priv->phy))
142		return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
143
144	phy_set_drvdata(priv->phy, priv);
145	dev_set_drvdata(dev, priv);
146
147	phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
148
149	return PTR_ERR_OR_ZERO(phy);
150}
151
152static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
153	{
154		.compatible = "amlogic,g12a-mipi-dphy-analog",
155	},
156	{ /* sentinel */ }
157};
158MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
159
160static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
161	.probe = phy_g12a_mipi_dphy_analog_probe,
162	.driver = {
163		.name = "phy-meson-g12a-mipi-dphy-analog",
164		.of_match_table = phy_g12a_mipi_dphy_analog_of_match,
165	},
166};
167module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
168
169MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
170MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
171MODULE_LICENSE("GPL v2");