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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3#include <linux/types.h>
4#include <linux/kernel.h>
5
6#include "lan966x_vcap_ag_api.h"
7
8/* keyfields */
9static const struct vcap_field is2_mac_etype_keyfield[] = {
10 [VCAP_KF_TYPE] = {
11 .type = VCAP_FIELD_U32,
12 .offset = 0,
13 .width = 4,
14 },
15 [VCAP_KF_LOOKUP_FIRST_IS] = {
16 .type = VCAP_FIELD_BIT,
17 .offset = 4,
18 .width = 1,
19 },
20 [VCAP_KF_LOOKUP_PAG] = {
21 .type = VCAP_FIELD_U32,
22 .offset = 5,
23 .width = 8,
24 },
25 [VCAP_KF_IF_IGR_PORT_MASK] = {
26 .type = VCAP_FIELD_U32,
27 .offset = 13,
28 .width = 9,
29 },
30 [VCAP_KF_ISDX_GT0_IS] = {
31 .type = VCAP_FIELD_BIT,
32 .offset = 22,
33 .width = 1,
34 },
35 [VCAP_KF_HOST_MATCH] = {
36 .type = VCAP_FIELD_BIT,
37 .offset = 23,
38 .width = 1,
39 },
40 [VCAP_KF_L2_MC_IS] = {
41 .type = VCAP_FIELD_BIT,
42 .offset = 24,
43 .width = 1,
44 },
45 [VCAP_KF_L2_BC_IS] = {
46 .type = VCAP_FIELD_BIT,
47 .offset = 25,
48 .width = 1,
49 },
50 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
51 .type = VCAP_FIELD_BIT,
52 .offset = 26,
53 .width = 1,
54 },
55 [VCAP_KF_8021Q_VID_CLS] = {
56 .type = VCAP_FIELD_U32,
57 .offset = 27,
58 .width = 12,
59 },
60 [VCAP_KF_8021Q_DEI_CLS] = {
61 .type = VCAP_FIELD_BIT,
62 .offset = 39,
63 .width = 1,
64 },
65 [VCAP_KF_8021Q_PCP_CLS] = {
66 .type = VCAP_FIELD_U32,
67 .offset = 40,
68 .width = 3,
69 },
70 [VCAP_KF_L2_DMAC] = {
71 .type = VCAP_FIELD_U48,
72 .offset = 43,
73 .width = 48,
74 },
75 [VCAP_KF_L2_SMAC] = {
76 .type = VCAP_FIELD_U48,
77 .offset = 91,
78 .width = 48,
79 },
80 [VCAP_KF_ETYPE] = {
81 .type = VCAP_FIELD_U32,
82 .offset = 139,
83 .width = 16,
84 },
85 [VCAP_KF_L2_FRM_TYPE] = {
86 .type = VCAP_FIELD_U32,
87 .offset = 155,
88 .width = 4,
89 },
90 [VCAP_KF_L2_PAYLOAD0] = {
91 .type = VCAP_FIELD_U32,
92 .offset = 159,
93 .width = 16,
94 },
95 [VCAP_KF_L2_PAYLOAD1] = {
96 .type = VCAP_FIELD_U32,
97 .offset = 175,
98 .width = 8,
99 },
100 [VCAP_KF_L2_PAYLOAD2] = {
101 .type = VCAP_FIELD_U32,
102 .offset = 183,
103 .width = 3,
104 },
105};
106
107static const struct vcap_field is2_mac_llc_keyfield[] = {
108 [VCAP_KF_TYPE] = {
109 .type = VCAP_FIELD_U32,
110 .offset = 0,
111 .width = 4,
112 },
113 [VCAP_KF_LOOKUP_FIRST_IS] = {
114 .type = VCAP_FIELD_BIT,
115 .offset = 4,
116 .width = 1,
117 },
118 [VCAP_KF_LOOKUP_PAG] = {
119 .type = VCAP_FIELD_U32,
120 .offset = 5,
121 .width = 8,
122 },
123 [VCAP_KF_IF_IGR_PORT_MASK] = {
124 .type = VCAP_FIELD_U32,
125 .offset = 13,
126 .width = 9,
127 },
128 [VCAP_KF_ISDX_GT0_IS] = {
129 .type = VCAP_FIELD_BIT,
130 .offset = 22,
131 .width = 1,
132 },
133 [VCAP_KF_HOST_MATCH] = {
134 .type = VCAP_FIELD_BIT,
135 .offset = 23,
136 .width = 1,
137 },
138 [VCAP_KF_L2_MC_IS] = {
139 .type = VCAP_FIELD_BIT,
140 .offset = 24,
141 .width = 1,
142 },
143 [VCAP_KF_L2_BC_IS] = {
144 .type = VCAP_FIELD_BIT,
145 .offset = 25,
146 .width = 1,
147 },
148 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
149 .type = VCAP_FIELD_BIT,
150 .offset = 26,
151 .width = 1,
152 },
153 [VCAP_KF_8021Q_VID_CLS] = {
154 .type = VCAP_FIELD_U32,
155 .offset = 27,
156 .width = 12,
157 },
158 [VCAP_KF_8021Q_DEI_CLS] = {
159 .type = VCAP_FIELD_BIT,
160 .offset = 39,
161 .width = 1,
162 },
163 [VCAP_KF_8021Q_PCP_CLS] = {
164 .type = VCAP_FIELD_U32,
165 .offset = 40,
166 .width = 3,
167 },
168 [VCAP_KF_L2_DMAC] = {
169 .type = VCAP_FIELD_U48,
170 .offset = 43,
171 .width = 48,
172 },
173 [VCAP_KF_L2_SMAC] = {
174 .type = VCAP_FIELD_U48,
175 .offset = 91,
176 .width = 48,
177 },
178 [VCAP_KF_L2_LLC] = {
179 .type = VCAP_FIELD_U48,
180 .offset = 139,
181 .width = 40,
182 },
183};
184
185static const struct vcap_field is2_mac_snap_keyfield[] = {
186 [VCAP_KF_TYPE] = {
187 .type = VCAP_FIELD_U32,
188 .offset = 0,
189 .width = 4,
190 },
191 [VCAP_KF_LOOKUP_FIRST_IS] = {
192 .type = VCAP_FIELD_BIT,
193 .offset = 4,
194 .width = 1,
195 },
196 [VCAP_KF_LOOKUP_PAG] = {
197 .type = VCAP_FIELD_U32,
198 .offset = 5,
199 .width = 8,
200 },
201 [VCAP_KF_IF_IGR_PORT_MASK] = {
202 .type = VCAP_FIELD_U32,
203 .offset = 13,
204 .width = 9,
205 },
206 [VCAP_KF_ISDX_GT0_IS] = {
207 .type = VCAP_FIELD_BIT,
208 .offset = 22,
209 .width = 1,
210 },
211 [VCAP_KF_HOST_MATCH] = {
212 .type = VCAP_FIELD_BIT,
213 .offset = 23,
214 .width = 1,
215 },
216 [VCAP_KF_L2_MC_IS] = {
217 .type = VCAP_FIELD_BIT,
218 .offset = 24,
219 .width = 1,
220 },
221 [VCAP_KF_L2_BC_IS] = {
222 .type = VCAP_FIELD_BIT,
223 .offset = 25,
224 .width = 1,
225 },
226 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
227 .type = VCAP_FIELD_BIT,
228 .offset = 26,
229 .width = 1,
230 },
231 [VCAP_KF_8021Q_VID_CLS] = {
232 .type = VCAP_FIELD_U32,
233 .offset = 27,
234 .width = 12,
235 },
236 [VCAP_KF_8021Q_DEI_CLS] = {
237 .type = VCAP_FIELD_BIT,
238 .offset = 39,
239 .width = 1,
240 },
241 [VCAP_KF_8021Q_PCP_CLS] = {
242 .type = VCAP_FIELD_U32,
243 .offset = 40,
244 .width = 3,
245 },
246 [VCAP_KF_L2_DMAC] = {
247 .type = VCAP_FIELD_U48,
248 .offset = 43,
249 .width = 48,
250 },
251 [VCAP_KF_L2_SMAC] = {
252 .type = VCAP_FIELD_U48,
253 .offset = 91,
254 .width = 48,
255 },
256 [VCAP_KF_L2_SNAP] = {
257 .type = VCAP_FIELD_U48,
258 .offset = 139,
259 .width = 40,
260 },
261};
262
263static const struct vcap_field is2_arp_keyfield[] = {
264 [VCAP_KF_TYPE] = {
265 .type = VCAP_FIELD_U32,
266 .offset = 0,
267 .width = 4,
268 },
269 [VCAP_KF_LOOKUP_FIRST_IS] = {
270 .type = VCAP_FIELD_BIT,
271 .offset = 4,
272 .width = 1,
273 },
274 [VCAP_KF_LOOKUP_PAG] = {
275 .type = VCAP_FIELD_U32,
276 .offset = 5,
277 .width = 8,
278 },
279 [VCAP_KF_IF_IGR_PORT_MASK] = {
280 .type = VCAP_FIELD_U32,
281 .offset = 13,
282 .width = 9,
283 },
284 [VCAP_KF_ISDX_GT0_IS] = {
285 .type = VCAP_FIELD_BIT,
286 .offset = 22,
287 .width = 1,
288 },
289 [VCAP_KF_HOST_MATCH] = {
290 .type = VCAP_FIELD_BIT,
291 .offset = 23,
292 .width = 1,
293 },
294 [VCAP_KF_L2_MC_IS] = {
295 .type = VCAP_FIELD_BIT,
296 .offset = 24,
297 .width = 1,
298 },
299 [VCAP_KF_L2_BC_IS] = {
300 .type = VCAP_FIELD_BIT,
301 .offset = 25,
302 .width = 1,
303 },
304 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
305 .type = VCAP_FIELD_BIT,
306 .offset = 26,
307 .width = 1,
308 },
309 [VCAP_KF_8021Q_VID_CLS] = {
310 .type = VCAP_FIELD_U32,
311 .offset = 27,
312 .width = 12,
313 },
314 [VCAP_KF_8021Q_DEI_CLS] = {
315 .type = VCAP_FIELD_BIT,
316 .offset = 39,
317 .width = 1,
318 },
319 [VCAP_KF_8021Q_PCP_CLS] = {
320 .type = VCAP_FIELD_U32,
321 .offset = 40,
322 .width = 3,
323 },
324 [VCAP_KF_L2_SMAC] = {
325 .type = VCAP_FIELD_U48,
326 .offset = 43,
327 .width = 48,
328 },
329 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
330 .type = VCAP_FIELD_BIT,
331 .offset = 91,
332 .width = 1,
333 },
334 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
335 .type = VCAP_FIELD_BIT,
336 .offset = 92,
337 .width = 1,
338 },
339 [VCAP_KF_ARP_LEN_OK_IS] = {
340 .type = VCAP_FIELD_BIT,
341 .offset = 93,
342 .width = 1,
343 },
344 [VCAP_KF_ARP_TGT_MATCH_IS] = {
345 .type = VCAP_FIELD_BIT,
346 .offset = 94,
347 .width = 1,
348 },
349 [VCAP_KF_ARP_SENDER_MATCH_IS] = {
350 .type = VCAP_FIELD_BIT,
351 .offset = 95,
352 .width = 1,
353 },
354 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
355 .type = VCAP_FIELD_BIT,
356 .offset = 96,
357 .width = 1,
358 },
359 [VCAP_KF_ARP_OPCODE] = {
360 .type = VCAP_FIELD_U32,
361 .offset = 97,
362 .width = 2,
363 },
364 [VCAP_KF_L3_IP4_DIP] = {
365 .type = VCAP_FIELD_U32,
366 .offset = 99,
367 .width = 32,
368 },
369 [VCAP_KF_L3_IP4_SIP] = {
370 .type = VCAP_FIELD_U32,
371 .offset = 131,
372 .width = 32,
373 },
374 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
375 .type = VCAP_FIELD_BIT,
376 .offset = 163,
377 .width = 1,
378 },
379};
380
381static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
382 [VCAP_KF_TYPE] = {
383 .type = VCAP_FIELD_U32,
384 .offset = 0,
385 .width = 4,
386 },
387 [VCAP_KF_LOOKUP_FIRST_IS] = {
388 .type = VCAP_FIELD_BIT,
389 .offset = 4,
390 .width = 1,
391 },
392 [VCAP_KF_LOOKUP_PAG] = {
393 .type = VCAP_FIELD_U32,
394 .offset = 5,
395 .width = 8,
396 },
397 [VCAP_KF_IF_IGR_PORT_MASK] = {
398 .type = VCAP_FIELD_U32,
399 .offset = 13,
400 .width = 9,
401 },
402 [VCAP_KF_ISDX_GT0_IS] = {
403 .type = VCAP_FIELD_BIT,
404 .offset = 22,
405 .width = 1,
406 },
407 [VCAP_KF_HOST_MATCH] = {
408 .type = VCAP_FIELD_BIT,
409 .offset = 23,
410 .width = 1,
411 },
412 [VCAP_KF_L2_MC_IS] = {
413 .type = VCAP_FIELD_BIT,
414 .offset = 24,
415 .width = 1,
416 },
417 [VCAP_KF_L2_BC_IS] = {
418 .type = VCAP_FIELD_BIT,
419 .offset = 25,
420 .width = 1,
421 },
422 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
423 .type = VCAP_FIELD_BIT,
424 .offset = 26,
425 .width = 1,
426 },
427 [VCAP_KF_8021Q_VID_CLS] = {
428 .type = VCAP_FIELD_U32,
429 .offset = 27,
430 .width = 12,
431 },
432 [VCAP_KF_8021Q_DEI_CLS] = {
433 .type = VCAP_FIELD_BIT,
434 .offset = 39,
435 .width = 1,
436 },
437 [VCAP_KF_8021Q_PCP_CLS] = {
438 .type = VCAP_FIELD_U32,
439 .offset = 40,
440 .width = 3,
441 },
442 [VCAP_KF_IP4_IS] = {
443 .type = VCAP_FIELD_BIT,
444 .offset = 43,
445 .width = 1,
446 },
447 [VCAP_KF_L3_FRAGMENT] = {
448 .type = VCAP_FIELD_BIT,
449 .offset = 44,
450 .width = 1,
451 },
452 [VCAP_KF_L3_FRAG_OFS_GT0] = {
453 .type = VCAP_FIELD_BIT,
454 .offset = 45,
455 .width = 1,
456 },
457 [VCAP_KF_L3_OPTIONS_IS] = {
458 .type = VCAP_FIELD_BIT,
459 .offset = 46,
460 .width = 1,
461 },
462 [VCAP_KF_L3_TTL_GT0] = {
463 .type = VCAP_FIELD_BIT,
464 .offset = 47,
465 .width = 1,
466 },
467 [VCAP_KF_L3_TOS] = {
468 .type = VCAP_FIELD_U32,
469 .offset = 48,
470 .width = 8,
471 },
472 [VCAP_KF_L3_IP4_DIP] = {
473 .type = VCAP_FIELD_U32,
474 .offset = 56,
475 .width = 32,
476 },
477 [VCAP_KF_L3_IP4_SIP] = {
478 .type = VCAP_FIELD_U32,
479 .offset = 88,
480 .width = 32,
481 },
482 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
483 .type = VCAP_FIELD_BIT,
484 .offset = 120,
485 .width = 1,
486 },
487 [VCAP_KF_TCP_IS] = {
488 .type = VCAP_FIELD_BIT,
489 .offset = 121,
490 .width = 1,
491 },
492 [VCAP_KF_L4_DPORT] = {
493 .type = VCAP_FIELD_U32,
494 .offset = 122,
495 .width = 16,
496 },
497 [VCAP_KF_L4_SPORT] = {
498 .type = VCAP_FIELD_U32,
499 .offset = 138,
500 .width = 16,
501 },
502 [VCAP_KF_L4_RNG] = {
503 .type = VCAP_FIELD_U32,
504 .offset = 154,
505 .width = 8,
506 },
507 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
508 .type = VCAP_FIELD_BIT,
509 .offset = 162,
510 .width = 1,
511 },
512 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
513 .type = VCAP_FIELD_BIT,
514 .offset = 163,
515 .width = 1,
516 },
517 [VCAP_KF_L4_FIN] = {
518 .type = VCAP_FIELD_BIT,
519 .offset = 164,
520 .width = 1,
521 },
522 [VCAP_KF_L4_SYN] = {
523 .type = VCAP_FIELD_BIT,
524 .offset = 165,
525 .width = 1,
526 },
527 [VCAP_KF_L4_RST] = {
528 .type = VCAP_FIELD_BIT,
529 .offset = 166,
530 .width = 1,
531 },
532 [VCAP_KF_L4_PSH] = {
533 .type = VCAP_FIELD_BIT,
534 .offset = 167,
535 .width = 1,
536 },
537 [VCAP_KF_L4_ACK] = {
538 .type = VCAP_FIELD_BIT,
539 .offset = 168,
540 .width = 1,
541 },
542 [VCAP_KF_L4_URG] = {
543 .type = VCAP_FIELD_BIT,
544 .offset = 169,
545 .width = 1,
546 },
547 [VCAP_KF_L4_1588_DOM] = {
548 .type = VCAP_FIELD_U32,
549 .offset = 170,
550 .width = 8,
551 },
552 [VCAP_KF_L4_1588_VER] = {
553 .type = VCAP_FIELD_U32,
554 .offset = 178,
555 .width = 4,
556 },
557};
558
559static const struct vcap_field is2_ip4_other_keyfield[] = {
560 [VCAP_KF_TYPE] = {
561 .type = VCAP_FIELD_U32,
562 .offset = 0,
563 .width = 4,
564 },
565 [VCAP_KF_LOOKUP_FIRST_IS] = {
566 .type = VCAP_FIELD_BIT,
567 .offset = 4,
568 .width = 1,
569 },
570 [VCAP_KF_LOOKUP_PAG] = {
571 .type = VCAP_FIELD_U32,
572 .offset = 5,
573 .width = 8,
574 },
575 [VCAP_KF_IF_IGR_PORT_MASK] = {
576 .type = VCAP_FIELD_U32,
577 .offset = 13,
578 .width = 9,
579 },
580 [VCAP_KF_ISDX_GT0_IS] = {
581 .type = VCAP_FIELD_BIT,
582 .offset = 22,
583 .width = 1,
584 },
585 [VCAP_KF_HOST_MATCH] = {
586 .type = VCAP_FIELD_BIT,
587 .offset = 23,
588 .width = 1,
589 },
590 [VCAP_KF_L2_MC_IS] = {
591 .type = VCAP_FIELD_BIT,
592 .offset = 24,
593 .width = 1,
594 },
595 [VCAP_KF_L2_BC_IS] = {
596 .type = VCAP_FIELD_BIT,
597 .offset = 25,
598 .width = 1,
599 },
600 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
601 .type = VCAP_FIELD_BIT,
602 .offset = 26,
603 .width = 1,
604 },
605 [VCAP_KF_8021Q_VID_CLS] = {
606 .type = VCAP_FIELD_U32,
607 .offset = 27,
608 .width = 12,
609 },
610 [VCAP_KF_8021Q_DEI_CLS] = {
611 .type = VCAP_FIELD_BIT,
612 .offset = 39,
613 .width = 1,
614 },
615 [VCAP_KF_8021Q_PCP_CLS] = {
616 .type = VCAP_FIELD_U32,
617 .offset = 40,
618 .width = 3,
619 },
620 [VCAP_KF_IP4_IS] = {
621 .type = VCAP_FIELD_BIT,
622 .offset = 43,
623 .width = 1,
624 },
625 [VCAP_KF_L3_FRAGMENT] = {
626 .type = VCAP_FIELD_BIT,
627 .offset = 44,
628 .width = 1,
629 },
630 [VCAP_KF_L3_FRAG_OFS_GT0] = {
631 .type = VCAP_FIELD_BIT,
632 .offset = 45,
633 .width = 1,
634 },
635 [VCAP_KF_L3_OPTIONS_IS] = {
636 .type = VCAP_FIELD_BIT,
637 .offset = 46,
638 .width = 1,
639 },
640 [VCAP_KF_L3_TTL_GT0] = {
641 .type = VCAP_FIELD_BIT,
642 .offset = 47,
643 .width = 1,
644 },
645 [VCAP_KF_L3_TOS] = {
646 .type = VCAP_FIELD_U32,
647 .offset = 48,
648 .width = 8,
649 },
650 [VCAP_KF_L3_IP4_DIP] = {
651 .type = VCAP_FIELD_U32,
652 .offset = 56,
653 .width = 32,
654 },
655 [VCAP_KF_L3_IP4_SIP] = {
656 .type = VCAP_FIELD_U32,
657 .offset = 88,
658 .width = 32,
659 },
660 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
661 .type = VCAP_FIELD_BIT,
662 .offset = 120,
663 .width = 1,
664 },
665 [VCAP_KF_L3_IP_PROTO] = {
666 .type = VCAP_FIELD_U32,
667 .offset = 121,
668 .width = 8,
669 },
670 [VCAP_KF_L3_PAYLOAD] = {
671 .type = VCAP_FIELD_U56,
672 .offset = 129,
673 .width = 56,
674 },
675};
676
677static const struct vcap_field is2_ip6_std_keyfield[] = {
678 [VCAP_KF_TYPE] = {
679 .type = VCAP_FIELD_U32,
680 .offset = 0,
681 .width = 4,
682 },
683 [VCAP_KF_LOOKUP_FIRST_IS] = {
684 .type = VCAP_FIELD_BIT,
685 .offset = 4,
686 .width = 1,
687 },
688 [VCAP_KF_LOOKUP_PAG] = {
689 .type = VCAP_FIELD_U32,
690 .offset = 5,
691 .width = 8,
692 },
693 [VCAP_KF_IF_IGR_PORT_MASK] = {
694 .type = VCAP_FIELD_U32,
695 .offset = 13,
696 .width = 9,
697 },
698 [VCAP_KF_ISDX_GT0_IS] = {
699 .type = VCAP_FIELD_BIT,
700 .offset = 22,
701 .width = 1,
702 },
703 [VCAP_KF_HOST_MATCH] = {
704 .type = VCAP_FIELD_BIT,
705 .offset = 23,
706 .width = 1,
707 },
708 [VCAP_KF_L2_MC_IS] = {
709 .type = VCAP_FIELD_BIT,
710 .offset = 24,
711 .width = 1,
712 },
713 [VCAP_KF_L2_BC_IS] = {
714 .type = VCAP_FIELD_BIT,
715 .offset = 25,
716 .width = 1,
717 },
718 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
719 .type = VCAP_FIELD_BIT,
720 .offset = 26,
721 .width = 1,
722 },
723 [VCAP_KF_8021Q_VID_CLS] = {
724 .type = VCAP_FIELD_U32,
725 .offset = 27,
726 .width = 12,
727 },
728 [VCAP_KF_8021Q_DEI_CLS] = {
729 .type = VCAP_FIELD_BIT,
730 .offset = 39,
731 .width = 1,
732 },
733 [VCAP_KF_8021Q_PCP_CLS] = {
734 .type = VCAP_FIELD_U32,
735 .offset = 40,
736 .width = 3,
737 },
738 [VCAP_KF_L3_TTL_GT0] = {
739 .type = VCAP_FIELD_BIT,
740 .offset = 43,
741 .width = 1,
742 },
743 [VCAP_KF_L3_IP6_SIP] = {
744 .type = VCAP_FIELD_U128,
745 .offset = 44,
746 .width = 128,
747 },
748 [VCAP_KF_L3_IP_PROTO] = {
749 .type = VCAP_FIELD_U32,
750 .offset = 172,
751 .width = 8,
752 },
753};
754
755static const struct vcap_field is2_oam_keyfield[] = {
756 [VCAP_KF_TYPE] = {
757 .type = VCAP_FIELD_U32,
758 .offset = 0,
759 .width = 4,
760 },
761 [VCAP_KF_LOOKUP_FIRST_IS] = {
762 .type = VCAP_FIELD_BIT,
763 .offset = 4,
764 .width = 1,
765 },
766 [VCAP_KF_LOOKUP_PAG] = {
767 .type = VCAP_FIELD_U32,
768 .offset = 5,
769 .width = 8,
770 },
771 [VCAP_KF_IF_IGR_PORT_MASK] = {
772 .type = VCAP_FIELD_U32,
773 .offset = 13,
774 .width = 9,
775 },
776 [VCAP_KF_ISDX_GT0_IS] = {
777 .type = VCAP_FIELD_BIT,
778 .offset = 22,
779 .width = 1,
780 },
781 [VCAP_KF_HOST_MATCH] = {
782 .type = VCAP_FIELD_BIT,
783 .offset = 23,
784 .width = 1,
785 },
786 [VCAP_KF_L2_MC_IS] = {
787 .type = VCAP_FIELD_BIT,
788 .offset = 24,
789 .width = 1,
790 },
791 [VCAP_KF_L2_BC_IS] = {
792 .type = VCAP_FIELD_BIT,
793 .offset = 25,
794 .width = 1,
795 },
796 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
797 .type = VCAP_FIELD_BIT,
798 .offset = 26,
799 .width = 1,
800 },
801 [VCAP_KF_8021Q_VID_CLS] = {
802 .type = VCAP_FIELD_U32,
803 .offset = 27,
804 .width = 12,
805 },
806 [VCAP_KF_8021Q_DEI_CLS] = {
807 .type = VCAP_FIELD_BIT,
808 .offset = 39,
809 .width = 1,
810 },
811 [VCAP_KF_8021Q_PCP_CLS] = {
812 .type = VCAP_FIELD_U32,
813 .offset = 40,
814 .width = 3,
815 },
816 [VCAP_KF_L2_DMAC] = {
817 .type = VCAP_FIELD_U48,
818 .offset = 43,
819 .width = 48,
820 },
821 [VCAP_KF_L2_SMAC] = {
822 .type = VCAP_FIELD_U48,
823 .offset = 91,
824 .width = 48,
825 },
826 [VCAP_KF_OAM_MEL_FLAGS] = {
827 .type = VCAP_FIELD_U32,
828 .offset = 139,
829 .width = 7,
830 },
831 [VCAP_KF_OAM_VER] = {
832 .type = VCAP_FIELD_U32,
833 .offset = 146,
834 .width = 5,
835 },
836 [VCAP_KF_OAM_OPCODE] = {
837 .type = VCAP_FIELD_U32,
838 .offset = 151,
839 .width = 8,
840 },
841 [VCAP_KF_OAM_FLAGS] = {
842 .type = VCAP_FIELD_U32,
843 .offset = 159,
844 .width = 8,
845 },
846 [VCAP_KF_OAM_MEPID] = {
847 .type = VCAP_FIELD_U32,
848 .offset = 167,
849 .width = 16,
850 },
851 [VCAP_KF_OAM_CCM_CNTS_EQ0] = {
852 .type = VCAP_FIELD_BIT,
853 .offset = 183,
854 .width = 1,
855 },
856 [VCAP_KF_OAM_Y1731_IS] = {
857 .type = VCAP_FIELD_BIT,
858 .offset = 184,
859 .width = 1,
860 },
861 [VCAP_KF_OAM_DETECTED] = {
862 .type = VCAP_FIELD_BIT,
863 .offset = 185,
864 .width = 1,
865 },
866};
867
868static const struct vcap_field is2_ip6_tcp_udp_keyfield[] = {
869 [VCAP_KF_TYPE] = {
870 .type = VCAP_FIELD_U32,
871 .offset = 0,
872 .width = 2,
873 },
874 [VCAP_KF_LOOKUP_FIRST_IS] = {
875 .type = VCAP_FIELD_BIT,
876 .offset = 2,
877 .width = 1,
878 },
879 [VCAP_KF_LOOKUP_PAG] = {
880 .type = VCAP_FIELD_U32,
881 .offset = 3,
882 .width = 8,
883 },
884 [VCAP_KF_IF_IGR_PORT_MASK] = {
885 .type = VCAP_FIELD_U32,
886 .offset = 11,
887 .width = 9,
888 },
889 [VCAP_KF_ISDX_GT0_IS] = {
890 .type = VCAP_FIELD_BIT,
891 .offset = 20,
892 .width = 1,
893 },
894 [VCAP_KF_HOST_MATCH] = {
895 .type = VCAP_FIELD_BIT,
896 .offset = 21,
897 .width = 1,
898 },
899 [VCAP_KF_L2_MC_IS] = {
900 .type = VCAP_FIELD_BIT,
901 .offset = 22,
902 .width = 1,
903 },
904 [VCAP_KF_L2_BC_IS] = {
905 .type = VCAP_FIELD_BIT,
906 .offset = 23,
907 .width = 1,
908 },
909 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
910 .type = VCAP_FIELD_BIT,
911 .offset = 24,
912 .width = 1,
913 },
914 [VCAP_KF_8021Q_VID_CLS] = {
915 .type = VCAP_FIELD_U32,
916 .offset = 25,
917 .width = 12,
918 },
919 [VCAP_KF_8021Q_DEI_CLS] = {
920 .type = VCAP_FIELD_BIT,
921 .offset = 37,
922 .width = 1,
923 },
924 [VCAP_KF_8021Q_PCP_CLS] = {
925 .type = VCAP_FIELD_U32,
926 .offset = 38,
927 .width = 3,
928 },
929 [VCAP_KF_L3_TTL_GT0] = {
930 .type = VCAP_FIELD_BIT,
931 .offset = 41,
932 .width = 1,
933 },
934 [VCAP_KF_L3_TOS] = {
935 .type = VCAP_FIELD_U32,
936 .offset = 42,
937 .width = 8,
938 },
939 [VCAP_KF_L3_IP6_DIP] = {
940 .type = VCAP_FIELD_U128,
941 .offset = 50,
942 .width = 128,
943 },
944 [VCAP_KF_L3_IP6_SIP] = {
945 .type = VCAP_FIELD_U128,
946 .offset = 178,
947 .width = 128,
948 },
949 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
950 .type = VCAP_FIELD_BIT,
951 .offset = 306,
952 .width = 1,
953 },
954 [VCAP_KF_TCP_IS] = {
955 .type = VCAP_FIELD_BIT,
956 .offset = 307,
957 .width = 1,
958 },
959 [VCAP_KF_L4_DPORT] = {
960 .type = VCAP_FIELD_U32,
961 .offset = 308,
962 .width = 16,
963 },
964 [VCAP_KF_L4_SPORT] = {
965 .type = VCAP_FIELD_U32,
966 .offset = 324,
967 .width = 16,
968 },
969 [VCAP_KF_L4_RNG] = {
970 .type = VCAP_FIELD_U32,
971 .offset = 340,
972 .width = 8,
973 },
974 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
975 .type = VCAP_FIELD_BIT,
976 .offset = 348,
977 .width = 1,
978 },
979 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
980 .type = VCAP_FIELD_BIT,
981 .offset = 349,
982 .width = 1,
983 },
984 [VCAP_KF_L4_FIN] = {
985 .type = VCAP_FIELD_BIT,
986 .offset = 350,
987 .width = 1,
988 },
989 [VCAP_KF_L4_SYN] = {
990 .type = VCAP_FIELD_BIT,
991 .offset = 351,
992 .width = 1,
993 },
994 [VCAP_KF_L4_RST] = {
995 .type = VCAP_FIELD_BIT,
996 .offset = 352,
997 .width = 1,
998 },
999 [VCAP_KF_L4_PSH] = {
1000 .type = VCAP_FIELD_BIT,
1001 .offset = 353,
1002 .width = 1,
1003 },
1004 [VCAP_KF_L4_ACK] = {
1005 .type = VCAP_FIELD_BIT,
1006 .offset = 354,
1007 .width = 1,
1008 },
1009 [VCAP_KF_L4_URG] = {
1010 .type = VCAP_FIELD_BIT,
1011 .offset = 355,
1012 .width = 1,
1013 },
1014 [VCAP_KF_L4_1588_DOM] = {
1015 .type = VCAP_FIELD_U32,
1016 .offset = 356,
1017 .width = 8,
1018 },
1019 [VCAP_KF_L4_1588_VER] = {
1020 .type = VCAP_FIELD_U32,
1021 .offset = 364,
1022 .width = 4,
1023 },
1024};
1025
1026static const struct vcap_field is2_ip6_other_keyfield[] = {
1027 [VCAP_KF_TYPE] = {
1028 .type = VCAP_FIELD_U32,
1029 .offset = 0,
1030 .width = 2,
1031 },
1032 [VCAP_KF_LOOKUP_FIRST_IS] = {
1033 .type = VCAP_FIELD_BIT,
1034 .offset = 2,
1035 .width = 1,
1036 },
1037 [VCAP_KF_LOOKUP_PAG] = {
1038 .type = VCAP_FIELD_U32,
1039 .offset = 3,
1040 .width = 8,
1041 },
1042 [VCAP_KF_IF_IGR_PORT_MASK] = {
1043 .type = VCAP_FIELD_U32,
1044 .offset = 11,
1045 .width = 9,
1046 },
1047 [VCAP_KF_ISDX_GT0_IS] = {
1048 .type = VCAP_FIELD_BIT,
1049 .offset = 20,
1050 .width = 1,
1051 },
1052 [VCAP_KF_HOST_MATCH] = {
1053 .type = VCAP_FIELD_BIT,
1054 .offset = 21,
1055 .width = 1,
1056 },
1057 [VCAP_KF_L2_MC_IS] = {
1058 .type = VCAP_FIELD_BIT,
1059 .offset = 22,
1060 .width = 1,
1061 },
1062 [VCAP_KF_L2_BC_IS] = {
1063 .type = VCAP_FIELD_BIT,
1064 .offset = 23,
1065 .width = 1,
1066 },
1067 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
1068 .type = VCAP_FIELD_BIT,
1069 .offset = 24,
1070 .width = 1,
1071 },
1072 [VCAP_KF_8021Q_VID_CLS] = {
1073 .type = VCAP_FIELD_U32,
1074 .offset = 25,
1075 .width = 12,
1076 },
1077 [VCAP_KF_8021Q_DEI_CLS] = {
1078 .type = VCAP_FIELD_BIT,
1079 .offset = 37,
1080 .width = 1,
1081 },
1082 [VCAP_KF_8021Q_PCP_CLS] = {
1083 .type = VCAP_FIELD_U32,
1084 .offset = 38,
1085 .width = 3,
1086 },
1087 [VCAP_KF_L3_TTL_GT0] = {
1088 .type = VCAP_FIELD_BIT,
1089 .offset = 41,
1090 .width = 1,
1091 },
1092 [VCAP_KF_L3_TOS] = {
1093 .type = VCAP_FIELD_U32,
1094 .offset = 42,
1095 .width = 8,
1096 },
1097 [VCAP_KF_L3_IP6_DIP] = {
1098 .type = VCAP_FIELD_U128,
1099 .offset = 50,
1100 .width = 128,
1101 },
1102 [VCAP_KF_L3_IP6_SIP] = {
1103 .type = VCAP_FIELD_U128,
1104 .offset = 178,
1105 .width = 128,
1106 },
1107 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
1108 .type = VCAP_FIELD_BIT,
1109 .offset = 306,
1110 .width = 1,
1111 },
1112 [VCAP_KF_L3_IP_PROTO] = {
1113 .type = VCAP_FIELD_U32,
1114 .offset = 307,
1115 .width = 8,
1116 },
1117 [VCAP_KF_L3_PAYLOAD] = {
1118 .type = VCAP_FIELD_U56,
1119 .offset = 315,
1120 .width = 56,
1121 },
1122};
1123
1124static const struct vcap_field is2_smac_sip4_keyfield[] = {
1125 [VCAP_KF_IF_IGR_PORT] = {
1126 .type = VCAP_FIELD_U32,
1127 .offset = 0,
1128 .width = 4,
1129 },
1130 [VCAP_KF_L2_SMAC] = {
1131 .type = VCAP_FIELD_U48,
1132 .offset = 4,
1133 .width = 48,
1134 },
1135 [VCAP_KF_L3_IP4_SIP] = {
1136 .type = VCAP_FIELD_U32,
1137 .offset = 52,
1138 .width = 32,
1139 },
1140};
1141
1142static const struct vcap_field is2_smac_sip6_keyfield[] = {
1143 [VCAP_KF_TYPE] = {
1144 .type = VCAP_FIELD_U32,
1145 .offset = 0,
1146 .width = 4,
1147 },
1148 [VCAP_KF_IF_IGR_PORT] = {
1149 .type = VCAP_FIELD_U32,
1150 .offset = 4,
1151 .width = 4,
1152 },
1153 [VCAP_KF_L2_SMAC] = {
1154 .type = VCAP_FIELD_U48,
1155 .offset = 8,
1156 .width = 48,
1157 },
1158 [VCAP_KF_L3_IP6_SIP] = {
1159 .type = VCAP_FIELD_U128,
1160 .offset = 56,
1161 .width = 128,
1162 },
1163};
1164
1165/* keyfield_set */
1166static const struct vcap_set is2_keyfield_set[] = {
1167 [VCAP_KFS_MAC_ETYPE] = {
1168 .type_id = 0,
1169 .sw_per_item = 2,
1170 .sw_cnt = 2,
1171 },
1172 [VCAP_KFS_MAC_LLC] = {
1173 .type_id = 1,
1174 .sw_per_item = 2,
1175 .sw_cnt = 2,
1176 },
1177 [VCAP_KFS_MAC_SNAP] = {
1178 .type_id = 2,
1179 .sw_per_item = 2,
1180 .sw_cnt = 2,
1181 },
1182 [VCAP_KFS_ARP] = {
1183 .type_id = 3,
1184 .sw_per_item = 2,
1185 .sw_cnt = 2,
1186 },
1187 [VCAP_KFS_IP4_TCP_UDP] = {
1188 .type_id = 4,
1189 .sw_per_item = 2,
1190 .sw_cnt = 2,
1191 },
1192 [VCAP_KFS_IP4_OTHER] = {
1193 .type_id = 5,
1194 .sw_per_item = 2,
1195 .sw_cnt = 2,
1196 },
1197 [VCAP_KFS_IP6_STD] = {
1198 .type_id = 6,
1199 .sw_per_item = 2,
1200 .sw_cnt = 2,
1201 },
1202 [VCAP_KFS_OAM] = {
1203 .type_id = 7,
1204 .sw_per_item = 2,
1205 .sw_cnt = 2,
1206 },
1207 [VCAP_KFS_IP6_TCP_UDP] = {
1208 .type_id = 0,
1209 .sw_per_item = 4,
1210 .sw_cnt = 1,
1211 },
1212 [VCAP_KFS_IP6_OTHER] = {
1213 .type_id = 1,
1214 .sw_per_item = 4,
1215 .sw_cnt = 1,
1216 },
1217 [VCAP_KFS_SMAC_SIP4] = {
1218 .type_id = -1,
1219 .sw_per_item = 1,
1220 .sw_cnt = 4,
1221 },
1222 [VCAP_KFS_SMAC_SIP6] = {
1223 .type_id = 8,
1224 .sw_per_item = 2,
1225 .sw_cnt = 2,
1226 },
1227};
1228
1229/* keyfield_set map */
1230static const struct vcap_field *is2_keyfield_set_map[] = {
1231 [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
1232 [VCAP_KFS_MAC_LLC] = is2_mac_llc_keyfield,
1233 [VCAP_KFS_MAC_SNAP] = is2_mac_snap_keyfield,
1234 [VCAP_KFS_ARP] = is2_arp_keyfield,
1235 [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
1236 [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
1237 [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
1238 [VCAP_KFS_OAM] = is2_oam_keyfield,
1239 [VCAP_KFS_IP6_TCP_UDP] = is2_ip6_tcp_udp_keyfield,
1240 [VCAP_KFS_IP6_OTHER] = is2_ip6_other_keyfield,
1241 [VCAP_KFS_SMAC_SIP4] = is2_smac_sip4_keyfield,
1242 [VCAP_KFS_SMAC_SIP6] = is2_smac_sip6_keyfield,
1243};
1244
1245/* keyfield_set map sizes */
1246static int is2_keyfield_set_map_size[] = {
1247 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
1248 [VCAP_KFS_MAC_LLC] = ARRAY_SIZE(is2_mac_llc_keyfield),
1249 [VCAP_KFS_MAC_SNAP] = ARRAY_SIZE(is2_mac_snap_keyfield),
1250 [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
1251 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
1252 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
1253 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
1254 [VCAP_KFS_OAM] = ARRAY_SIZE(is2_oam_keyfield),
1255 [VCAP_KFS_IP6_TCP_UDP] = ARRAY_SIZE(is2_ip6_tcp_udp_keyfield),
1256 [VCAP_KFS_IP6_OTHER] = ARRAY_SIZE(is2_ip6_other_keyfield),
1257 [VCAP_KFS_SMAC_SIP4] = ARRAY_SIZE(is2_smac_sip4_keyfield),
1258 [VCAP_KFS_SMAC_SIP6] = ARRAY_SIZE(is2_smac_sip6_keyfield),
1259};
1260
1261/* actionfields */
1262static const struct vcap_field is2_base_type_actionfield[] = {
1263 [VCAP_AF_HIT_ME_ONCE] = {
1264 .type = VCAP_FIELD_BIT,
1265 .offset = 0,
1266 .width = 1,
1267 },
1268 [VCAP_AF_CPU_COPY_ENA] = {
1269 .type = VCAP_FIELD_BIT,
1270 .offset = 1,
1271 .width = 1,
1272 },
1273 [VCAP_AF_CPU_QUEUE_NUM] = {
1274 .type = VCAP_FIELD_U32,
1275 .offset = 2,
1276 .width = 3,
1277 },
1278 [VCAP_AF_MASK_MODE] = {
1279 .type = VCAP_FIELD_U32,
1280 .offset = 5,
1281 .width = 2,
1282 },
1283 [VCAP_AF_MIRROR_ENA] = {
1284 .type = VCAP_FIELD_BIT,
1285 .offset = 7,
1286 .width = 1,
1287 },
1288 [VCAP_AF_LRN_DIS] = {
1289 .type = VCAP_FIELD_BIT,
1290 .offset = 8,
1291 .width = 1,
1292 },
1293 [VCAP_AF_POLICE_ENA] = {
1294 .type = VCAP_FIELD_BIT,
1295 .offset = 9,
1296 .width = 1,
1297 },
1298 [VCAP_AF_POLICE_IDX] = {
1299 .type = VCAP_FIELD_U32,
1300 .offset = 10,
1301 .width = 9,
1302 },
1303 [VCAP_AF_POLICE_VCAP_ONLY] = {
1304 .type = VCAP_FIELD_BIT,
1305 .offset = 19,
1306 .width = 1,
1307 },
1308 [VCAP_AF_PORT_MASK] = {
1309 .type = VCAP_FIELD_U32,
1310 .offset = 20,
1311 .width = 8,
1312 },
1313 [VCAP_AF_REW_OP] = {
1314 .type = VCAP_FIELD_U32,
1315 .offset = 28,
1316 .width = 16,
1317 },
1318 [VCAP_AF_ISDX_ENA] = {
1319 .type = VCAP_FIELD_BIT,
1320 .offset = 44,
1321 .width = 1,
1322 },
1323 [VCAP_AF_ACL_ID] = {
1324 .type = VCAP_FIELD_U32,
1325 .offset = 45,
1326 .width = 6,
1327 },
1328};
1329
1330static const struct vcap_field is2_smac_sip_actionfield[] = {
1331 [VCAP_AF_CPU_COPY_ENA] = {
1332 .type = VCAP_FIELD_BIT,
1333 .offset = 0,
1334 .width = 1,
1335 },
1336 [VCAP_AF_CPU_QUEUE_NUM] = {
1337 .type = VCAP_FIELD_U32,
1338 .offset = 1,
1339 .width = 3,
1340 },
1341 [VCAP_AF_FWD_KILL_ENA] = {
1342 .type = VCAP_FIELD_BIT,
1343 .offset = 4,
1344 .width = 1,
1345 },
1346 [VCAP_AF_HOST_MATCH] = {
1347 .type = VCAP_FIELD_BIT,
1348 .offset = 5,
1349 .width = 1,
1350 },
1351};
1352
1353/* actionfield_set */
1354static const struct vcap_set is2_actionfield_set[] = {
1355 [VCAP_AFS_BASE_TYPE] = {
1356 .type_id = -1,
1357 .sw_per_item = 2,
1358 .sw_cnt = 2,
1359 },
1360 [VCAP_AFS_SMAC_SIP] = {
1361 .type_id = -1,
1362 .sw_per_item = 1,
1363 .sw_cnt = 4,
1364 },
1365};
1366
1367/* actionfield_set map */
1368static const struct vcap_field *is2_actionfield_set_map[] = {
1369 [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
1370 [VCAP_AFS_SMAC_SIP] = is2_smac_sip_actionfield,
1371};
1372
1373/* actionfield_set map size */
1374static int is2_actionfield_set_map_size[] = {
1375 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
1376 [VCAP_AFS_SMAC_SIP] = ARRAY_SIZE(is2_smac_sip_actionfield),
1377};
1378
1379/* Type Groups */
1380static const struct vcap_typegroup is2_x4_keyfield_set_typegroups[] = {
1381 {
1382 .offset = 0,
1383 .width = 3,
1384 .value = 4,
1385 },
1386 {
1387 .offset = 96,
1388 .width = 1,
1389 .value = 0,
1390 },
1391 {
1392 .offset = 192,
1393 .width = 2,
1394 .value = 0,
1395 },
1396 {
1397 .offset = 288,
1398 .width = 1,
1399 .value = 0,
1400 },
1401 {}
1402};
1403
1404static const struct vcap_typegroup is2_x2_keyfield_set_typegroups[] = {
1405 {
1406 .offset = 0,
1407 .width = 2,
1408 .value = 2,
1409 },
1410 {
1411 .offset = 96,
1412 .width = 1,
1413 .value = 0,
1414 },
1415 {}
1416};
1417
1418static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
1419 {
1420 .offset = 0,
1421 .width = 1,
1422 .value = 1,
1423 },
1424 {}
1425};
1426
1427static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
1428 [4] = is2_x4_keyfield_set_typegroups,
1429 [2] = is2_x2_keyfield_set_typegroups,
1430 [1] = is2_x1_keyfield_set_typegroups,
1431 [5] = NULL,
1432};
1433
1434static const struct vcap_typegroup is2_x2_actionfield_set_typegroups[] = {
1435 {
1436 .offset = 0,
1437 .width = 2,
1438 .value = 2,
1439 },
1440 {
1441 .offset = 31,
1442 .width = 1,
1443 .value = 0,
1444 },
1445 {}
1446};
1447
1448static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
1449 {
1450 .offset = 0,
1451 .width = 1,
1452 .value = 1,
1453 },
1454 {}
1455};
1456
1457static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
1458 [2] = is2_x2_actionfield_set_typegroups,
1459 [1] = is2_x1_actionfield_set_typegroups,
1460 [5] = NULL,
1461};
1462
1463/* Keyfieldset names */
1464static const char * const vcap_keyfield_set_names[] = {
1465 [VCAP_KFS_NO_VALUE] = "(None)",
1466 [VCAP_KFS_ARP] = "VCAP_KFS_ARP",
1467 [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",
1468 [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",
1469 [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER",
1470 [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD",
1471 [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP",
1472 [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE",
1473 [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC",
1474 [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP",
1475 [VCAP_KFS_OAM] = "VCAP_KFS_OAM",
1476 [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4",
1477 [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6",
1478};
1479
1480/* Actionfieldset names */
1481static const char * const vcap_actionfield_set_names[] = {
1482 [VCAP_AFS_NO_VALUE] = "(None)",
1483 [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",
1484 [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP",
1485};
1486
1487/* Keyfield names */
1488static const char * const vcap_keyfield_names[] = {
1489 [VCAP_KF_NO_VALUE] = "(None)",
1490 [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS",
1491 [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS",
1492 [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS",
1493 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",
1494 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",
1495 [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",
1496 [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",
1497 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS",
1498 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS",
1499 [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",
1500 [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",
1501 [VCAP_KF_ETYPE] = "ETYPE",
1502 [VCAP_KF_HOST_MATCH] = "HOST_MATCH",
1503 [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT",
1504 [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK",
1505 [VCAP_KF_IP4_IS] = "IP4_IS",
1506 [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS",
1507 [VCAP_KF_L2_BC_IS] = "L2_BC_IS",
1508 [VCAP_KF_L2_DMAC] = "L2_DMAC",
1509 [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE",
1510 [VCAP_KF_L2_LLC] = "L2_LLC",
1511 [VCAP_KF_L2_MC_IS] = "L2_MC_IS",
1512 [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0",
1513 [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1",
1514 [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2",
1515 [VCAP_KF_L2_SMAC] = "L2_SMAC",
1516 [VCAP_KF_L2_SNAP] = "L2_SNAP",
1517 [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS",
1518 [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT",
1519 [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0",
1520 [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP",
1521 [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP",
1522 [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP",
1523 [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP",
1524 [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO",
1525 [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS",
1526 [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD",
1527 [VCAP_KF_L3_TOS] = "L3_TOS",
1528 [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0",
1529 [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM",
1530 [VCAP_KF_L4_1588_VER] = "L4_1588_VER",
1531 [VCAP_KF_L4_ACK] = "L4_ACK",
1532 [VCAP_KF_L4_DPORT] = "L4_DPORT",
1533 [VCAP_KF_L4_FIN] = "L4_FIN",
1534 [VCAP_KF_L4_PSH] = "L4_PSH",
1535 [VCAP_KF_L4_RNG] = "L4_RNG",
1536 [VCAP_KF_L4_RST] = "L4_RST",
1537 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS",
1538 [VCAP_KF_L4_SPORT] = "L4_SPORT",
1539 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS",
1540 [VCAP_KF_L4_SYN] = "L4_SYN",
1541 [VCAP_KF_L4_URG] = "L4_URG",
1542 [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS",
1543 [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG",
1544 [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0",
1545 [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED",
1546 [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS",
1547 [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS",
1548 [VCAP_KF_OAM_MEPID] = "OAM_MEPID",
1549 [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE",
1550 [VCAP_KF_OAM_VER] = "OAM_VER",
1551 [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS",
1552 [VCAP_KF_TCP_IS] = "TCP_IS",
1553 [VCAP_KF_TYPE] = "TYPE",
1554};
1555
1556/* Actionfield names */
1557static const char * const vcap_actionfield_names[] = {
1558 [VCAP_AF_NO_VALUE] = "(None)",
1559 [VCAP_AF_ACL_ID] = "ACL_ID",
1560 [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA",
1561 [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM",
1562 [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA",
1563 [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE",
1564 [VCAP_AF_HOST_MATCH] = "HOST_MATCH",
1565 [VCAP_AF_ISDX_ENA] = "ISDX_ENA",
1566 [VCAP_AF_LRN_DIS] = "LRN_DIS",
1567 [VCAP_AF_MASK_MODE] = "MASK_MODE",
1568 [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA",
1569 [VCAP_AF_POLICE_ENA] = "POLICE_ENA",
1570 [VCAP_AF_POLICE_IDX] = "POLICE_IDX",
1571 [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY",
1572 [VCAP_AF_PORT_MASK] = "PORT_MASK",
1573 [VCAP_AF_REW_OP] = "REW_OP",
1574};
1575
1576/* VCAPs */
1577const struct vcap_info lan966x_vcaps[] = {
1578 [VCAP_TYPE_IS2] = {
1579 .name = "is2",
1580 .rows = 64,
1581 .sw_count = 4,
1582 .sw_width = 96,
1583 .sticky_width = 32,
1584 .act_width = 31,
1585 .default_cnt = 11,
1586 .require_cnt_dis = 1,
1587 .version = 1,
1588 .keyfield_set = is2_keyfield_set,
1589 .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
1590 .actionfield_set = is2_actionfield_set,
1591 .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
1592 .keyfield_set_map = is2_keyfield_set_map,
1593 .keyfield_set_map_size = is2_keyfield_set_map_size,
1594 .actionfield_set_map = is2_actionfield_set_map,
1595 .actionfield_set_map_size = is2_actionfield_set_map_size,
1596 .keyfield_set_typegroups = is2_keyfield_set_typegroups,
1597 .actionfield_set_typegroups = is2_actionfield_set_typegroups,
1598 },
1599};
1600
1601const struct vcap_statistics lan966x_vcap_stats = {
1602 .name = "lan966x",
1603 .count = 1,
1604 .keyfield_set_names = vcap_keyfield_set_names,
1605 .actionfield_set_names = vcap_actionfield_set_names,
1606 .keyfield_names = vcap_keyfield_names,
1607 .actionfield_names = vcap_actionfield_names,
1608};