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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
4 */
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/gpio/consumer.h>
8#include <linux/regmap.h>
9#include <linux/mutex.h>
10#include <linux/mii.h>
11#include <linux/phy.h>
12#include <linux/if_bridge.h>
13#include <linux/if_vlan.h>
14#include <linux/etherdevice.h>
15
16#include "lan9303.h"
17
18#define LAN9303_NUM_PORTS 3
19
20/* 13.2 System Control and Status Registers
21 * Multiply register number by 4 to get address offset.
22 */
23#define LAN9303_CHIP_REV 0x14
24# define LAN9303_CHIP_ID 0x9303
25# define LAN9352_CHIP_ID 0x9352
26# define LAN9353_CHIP_ID 0x9353
27# define LAN9354_CHIP_ID 0x9354
28# define LAN9355_CHIP_ID 0x9355
29#define LAN9303_IRQ_CFG 0x15
30# define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
31# define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
32# define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
33#define LAN9303_INT_STS 0x16
34# define LAN9303_INT_STS_PHY_INT2 BIT(27)
35# define LAN9303_INT_STS_PHY_INT1 BIT(26)
36#define LAN9303_INT_EN 0x17
37# define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
38# define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
39#define LAN9303_BYTE_ORDER 0x19
40#define LAN9303_HW_CFG 0x1D
41# define LAN9303_HW_CFG_READY BIT(27)
42# define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
43# define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
44#define LAN9303_PMI_DATA 0x29
45#define LAN9303_PMI_ACCESS 0x2A
46# define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
47# define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
48# define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
49# define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
50#define LAN9303_MANUAL_FC_1 0x68
51#define LAN9303_MANUAL_FC_2 0x69
52#define LAN9303_MANUAL_FC_0 0x6a
53#define LAN9303_SWITCH_CSR_DATA 0x6b
54#define LAN9303_SWITCH_CSR_CMD 0x6c
55#define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
56#define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
57#define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
58#define LAN9303_VIRT_PHY_BASE 0x70
59#define LAN9303_VIRT_SPECIAL_CTRL 0x77
60#define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
61
62/*13.4 Switch Fabric Control and Status Registers
63 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
64 */
65#define LAN9303_SW_DEV_ID 0x0000
66#define LAN9303_SW_RESET 0x0001
67#define LAN9303_SW_RESET_RESET BIT(0)
68#define LAN9303_SW_IMR 0x0004
69#define LAN9303_SW_IPR 0x0005
70#define LAN9303_MAC_VER_ID_0 0x0400
71#define LAN9303_MAC_RX_CFG_0 0x0401
72# define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
73# define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
74#define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
75#define LAN9303_MAC_RX_64_CNT_0 0x0411
76#define LAN9303_MAC_RX_127_CNT_0 0x0412
77#define LAN9303_MAC_RX_255_CNT_0 0x413
78#define LAN9303_MAC_RX_511_CNT_0 0x0414
79#define LAN9303_MAC_RX_1023_CNT_0 0x0415
80#define LAN9303_MAC_RX_MAX_CNT_0 0x0416
81#define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
82#define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
83#define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
84#define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
85#define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
86#define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
87#define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
88#define LAN9303_MAC_RX_JABB_CNT_0 0x041e
89#define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
90#define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
91#define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
92#define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
93#define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
94
95#define LAN9303_MAC_TX_CFG_0 0x0440
96# define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
97# define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
98# define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
99#define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
100#define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
101#define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
102#define LAN9303_MAC_TX_64_CNT_0 0x0454
103#define LAN9303_MAC_TX_127_CNT_0 0x0455
104#define LAN9303_MAC_TX_255_CNT_0 0x0456
105#define LAN9303_MAC_TX_511_CNT_0 0x0457
106#define LAN9303_MAC_TX_1023_CNT_0 0x0458
107#define LAN9303_MAC_TX_MAX_CNT_0 0x0459
108#define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
109#define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
110#define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
111#define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
112#define LAN9303_MAC_TX_LATECOL_0 0x045f
113#define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
114#define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
115#define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
116#define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
117
118#define LAN9303_MAC_VER_ID_1 0x0800
119#define LAN9303_MAC_RX_CFG_1 0x0801
120#define LAN9303_MAC_TX_CFG_1 0x0840
121#define LAN9303_MAC_VER_ID_2 0x0c00
122#define LAN9303_MAC_RX_CFG_2 0x0c01
123#define LAN9303_MAC_TX_CFG_2 0x0c40
124#define LAN9303_SWE_ALR_CMD 0x1800
125# define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
126# define LAN9303_ALR_CMD_GET_FIRST BIT(1)
127# define LAN9303_ALR_CMD_GET_NEXT BIT(0)
128#define LAN9303_SWE_ALR_WR_DAT_0 0x1801
129#define LAN9303_SWE_ALR_WR_DAT_1 0x1802
130# define LAN9303_ALR_DAT1_VALID BIT(26)
131# define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
132# define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
133# define LAN9303_ALR_DAT1_STATIC BIT(24)
134# define LAN9303_ALR_DAT1_PORT_BITOFFS 16
135# define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
136#define LAN9303_SWE_ALR_RD_DAT_0 0x1805
137#define LAN9303_SWE_ALR_RD_DAT_1 0x1806
138#define LAN9303_SWE_ALR_CMD_STS 0x1808
139# define ALR_STS_MAKE_PEND BIT(0)
140#define LAN9303_SWE_VLAN_CMD 0x180b
141# define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
142# define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
143#define LAN9303_SWE_VLAN_WR_DATA 0x180c
144#define LAN9303_SWE_VLAN_RD_DATA 0x180e
145# define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
146# define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
147# define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
148# define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
149# define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
150# define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
151#define LAN9303_SWE_VLAN_CMD_STS 0x1810
152#define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
153# define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
154# define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
155#define LAN9303_SWE_PORT_STATE 0x1843
156# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
157# define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
158# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
159# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
160# define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
161# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
162# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
163# define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
164# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
165# define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
166#define LAN9303_SWE_PORT_MIRROR 0x1846
167# define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
168# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
169# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
170# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
171# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
172# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
173# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
174# define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
175# define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
176# define LAN9303_SWE_PORT_MIRROR_DISABLED 0
177#define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
178#define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
179#define LAN9303_BM_CFG 0x1c00
180#define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
181# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
182# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
183# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
184
185#define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
186
187/* the built-in PHYs are of type LAN911X */
188#define MII_LAN911X_SPECIAL_MODES 0x12
189#define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
190
191static const struct regmap_range lan9303_valid_regs[] = {
192 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
193 regmap_reg_range(0x19, 0x19), /* endian test */
194 regmap_reg_range(0x1d, 0x1d), /* hardware config */
195 regmap_reg_range(0x23, 0x24), /* general purpose timer */
196 regmap_reg_range(0x27, 0x27), /* counter */
197 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
198 regmap_reg_range(0x68, 0x6a), /* flow control */
199 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
200 regmap_reg_range(0x6d, 0x6f), /* misc */
201 regmap_reg_range(0x70, 0x77), /* virtual phy */
202 regmap_reg_range(0x78, 0x7a), /* GPIO */
203 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
204 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
205};
206
207static const struct regmap_range lan9303_reserved_ranges[] = {
208 regmap_reg_range(0x00, 0x13),
209 regmap_reg_range(0x18, 0x18),
210 regmap_reg_range(0x1a, 0x1c),
211 regmap_reg_range(0x1e, 0x22),
212 regmap_reg_range(0x25, 0x26),
213 regmap_reg_range(0x28, 0x28),
214 regmap_reg_range(0x2b, 0x67),
215 regmap_reg_range(0x7b, 0x7b),
216 regmap_reg_range(0x7f, 0x7f),
217 regmap_reg_range(0xb8, 0xff),
218};
219
220const struct regmap_access_table lan9303_register_set = {
221 .yes_ranges = lan9303_valid_regs,
222 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
223 .no_ranges = lan9303_reserved_ranges,
224 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
225};
226EXPORT_SYMBOL(lan9303_register_set);
227
228static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
229{
230 int ret, i;
231
232 /* we can lose arbitration for the I2C case, because the device
233 * tries to detect and read an external EEPROM after reset and acts as
234 * a master on the shared I2C bus itself. This conflicts with our
235 * attempts to access the device as a slave at the same moment.
236 */
237 for (i = 0; i < 5; i++) {
238 ret = regmap_read(regmap, offset, reg);
239 if (!ret)
240 return 0;
241 if (ret != -EAGAIN)
242 break;
243 msleep(500);
244 }
245
246 return -EIO;
247}
248
249static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
250{
251 int i;
252
253 for (i = 0; i < 25; i++) {
254 u32 reg;
255 int ret;
256
257 ret = lan9303_read(chip->regmap, offset, ®);
258 if (ret) {
259 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
260 __func__, offset, ret);
261 return ret;
262 }
263 if (!(reg & mask))
264 return 0;
265 usleep_range(1000, 2000);
266 }
267
268 return -ETIMEDOUT;
269}
270
271static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
272{
273 int ret;
274 u32 val;
275
276 if (regnum > MII_EXPANSION)
277 return -EINVAL;
278
279 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
280 if (ret)
281 return ret;
282
283 return val & 0xffff;
284}
285
286static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
287{
288 if (regnum > MII_EXPANSION)
289 return -EINVAL;
290
291 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
292}
293
294static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
295{
296 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
297 LAN9303_PMI_ACCESS_MII_BUSY);
298}
299
300static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
301{
302 int ret;
303 u32 val;
304
305 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
306 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
307
308 mutex_lock(&chip->indirect_mutex);
309
310 ret = lan9303_indirect_phy_wait_for_completion(chip);
311 if (ret)
312 goto on_error;
313
314 /* start the MII read cycle */
315 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
316 if (ret)
317 goto on_error;
318
319 ret = lan9303_indirect_phy_wait_for_completion(chip);
320 if (ret)
321 goto on_error;
322
323 /* read the result of this operation */
324 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
325 if (ret)
326 goto on_error;
327
328 mutex_unlock(&chip->indirect_mutex);
329
330 return val & 0xffff;
331
332on_error:
333 mutex_unlock(&chip->indirect_mutex);
334 return ret;
335}
336
337static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
338 int regnum, u16 val)
339{
340 int ret;
341 u32 reg;
342
343 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
344 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
345 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
346
347 mutex_lock(&chip->indirect_mutex);
348
349 ret = lan9303_indirect_phy_wait_for_completion(chip);
350 if (ret)
351 goto on_error;
352
353 /* write the data first... */
354 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
355 if (ret)
356 goto on_error;
357
358 /* ...then start the MII write cycle */
359 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
360
361on_error:
362 mutex_unlock(&chip->indirect_mutex);
363 return ret;
364}
365
366const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
367 .phy_read = lan9303_indirect_phy_read,
368 .phy_write = lan9303_indirect_phy_write,
369};
370EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
371
372static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
373{
374 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
375 LAN9303_SWITCH_CSR_CMD_BUSY);
376}
377
378static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
379{
380 u32 reg;
381 int ret;
382
383 reg = regnum;
384 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
385 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
386
387 mutex_lock(&chip->indirect_mutex);
388
389 ret = lan9303_switch_wait_for_completion(chip);
390 if (ret)
391 goto on_error;
392
393 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
394 if (ret) {
395 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
396 goto on_error;
397 }
398
399 /* trigger write */
400 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
401 if (ret)
402 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
403 ret);
404
405on_error:
406 mutex_unlock(&chip->indirect_mutex);
407 return ret;
408}
409
410static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
411{
412 u32 reg;
413 int ret;
414
415 reg = regnum;
416 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
417 reg |= LAN9303_SWITCH_CSR_CMD_RW;
418 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
419
420 mutex_lock(&chip->indirect_mutex);
421
422 ret = lan9303_switch_wait_for_completion(chip);
423 if (ret)
424 goto on_error;
425
426 /* trigger read */
427 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
428 if (ret) {
429 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
430 ret);
431 goto on_error;
432 }
433
434 ret = lan9303_switch_wait_for_completion(chip);
435 if (ret)
436 goto on_error;
437
438 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
439 if (ret)
440 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
441on_error:
442 mutex_unlock(&chip->indirect_mutex);
443 return ret;
444}
445
446static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
447 u32 val, u32 mask)
448{
449 int ret;
450 u32 reg;
451
452 ret = lan9303_read_switch_reg(chip, regnum, ®);
453 if (ret)
454 return ret;
455
456 reg = (reg & ~mask) | val;
457
458 return lan9303_write_switch_reg(chip, regnum, reg);
459}
460
461static int lan9303_write_switch_port(struct lan9303 *chip, int port,
462 u16 regnum, u32 val)
463{
464 return lan9303_write_switch_reg(
465 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
466}
467
468static int lan9303_read_switch_port(struct lan9303 *chip, int port,
469 u16 regnum, u32 *val)
470{
471 return lan9303_read_switch_reg(
472 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
473}
474
475static int lan9303_detect_phy_setup(struct lan9303 *chip)
476{
477 int reg;
478
479 /* Calculate chip->phy_addr_base:
480 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
481 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
482 * 'phy_addr_sel_strap' setting directly, so we need a test, which
483 * configuration is active:
484 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
485 * and the IDs are 0-1-2, else it contains something different from
486 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
487 * 0xffff is returned on MDIO read with no response.
488 */
489 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
490 if (reg < 0) {
491 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
492 return reg;
493 }
494
495 chip->phy_addr_base = reg != 0 && reg != 0xffff;
496
497 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
498 chip->phy_addr_base ? "1-2-3" : "0-1-2");
499
500 return 0;
501}
502
503/* Map ALR-port bits to port bitmap, and back */
504static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
505static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
506
507/* Return pointer to first free ALR cache entry, return NULL if none */
508static struct lan9303_alr_cache_entry *
509lan9303_alr_cache_find_free(struct lan9303 *chip)
510{
511 int i;
512 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
513
514 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
515 if (entr->port_map == 0)
516 return entr;
517
518 return NULL;
519}
520
521/* Return pointer to ALR cache entry matching MAC address */
522static struct lan9303_alr_cache_entry *
523lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
524{
525 int i;
526 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
527
528 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
529 "ether_addr_equal require u16 alignment");
530
531 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
532 if (ether_addr_equal(entr->mac_addr, mac_addr))
533 return entr;
534
535 return NULL;
536}
537
538static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
539{
540 int i;
541
542 for (i = 0; i < 25; i++) {
543 u32 reg;
544
545 lan9303_read_switch_reg(chip, regno, ®);
546 if (!(reg & mask))
547 return 0;
548 usleep_range(1000, 2000);
549 }
550
551 return -ETIMEDOUT;
552}
553
554static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
555{
556 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
557 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
558 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
559 LAN9303_ALR_CMD_MAKE_ENTRY);
560 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
561 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
562
563 return 0;
564}
565
566typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
567 int portmap, void *ctx);
568
569static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
570{
571 int ret = 0, i;
572
573 mutex_lock(&chip->alr_mutex);
574 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
575 LAN9303_ALR_CMD_GET_FIRST);
576 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
577
578 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
579 u32 dat0, dat1;
580 int alrport, portmap;
581
582 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
583 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
584 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
585 break;
586
587 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
588 LAN9303_ALR_DAT1_PORT_BITOFFS;
589 portmap = alrport_2_portmap[alrport];
590
591 ret = cb(chip, dat0, dat1, portmap, ctx);
592 if (ret)
593 break;
594
595 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
596 LAN9303_ALR_CMD_GET_NEXT);
597 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
598 }
599 mutex_unlock(&chip->alr_mutex);
600
601 return ret;
602}
603
604static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
605{
606 mac[0] = (dat0 >> 0) & 0xff;
607 mac[1] = (dat0 >> 8) & 0xff;
608 mac[2] = (dat0 >> 16) & 0xff;
609 mac[3] = (dat0 >> 24) & 0xff;
610 mac[4] = (dat1 >> 0) & 0xff;
611 mac[5] = (dat1 >> 8) & 0xff;
612}
613
614struct del_port_learned_ctx {
615 int port;
616};
617
618/* Clear learned (non-static) entry on given port */
619static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
620 u32 dat1, int portmap, void *ctx)
621{
622 struct del_port_learned_ctx *del_ctx = ctx;
623 int port = del_ctx->port;
624
625 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
626 return 0;
627
628 /* learned entries has only one port, we can just delete */
629 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
630 lan9303_alr_make_entry_raw(chip, dat0, dat1);
631
632 return 0;
633}
634
635struct port_fdb_dump_ctx {
636 int port;
637 void *data;
638 dsa_fdb_dump_cb_t *cb;
639};
640
641static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
642 u32 dat1, int portmap, void *ctx)
643{
644 struct port_fdb_dump_ctx *dump_ctx = ctx;
645 u8 mac[ETH_ALEN];
646 bool is_static;
647
648 if ((BIT(dump_ctx->port) & portmap) == 0)
649 return 0;
650
651 alr_reg_to_mac(dat0, dat1, mac);
652 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
653 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
654}
655
656/* Set a static ALR entry. Delete entry if port_map is zero */
657static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
658 u8 port_map, bool stp_override)
659{
660 u32 dat0, dat1, alr_port;
661
662 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
663 dat1 = LAN9303_ALR_DAT1_STATIC;
664 if (port_map)
665 dat1 |= LAN9303_ALR_DAT1_VALID;
666 /* otherwise no ports: delete entry */
667 if (stp_override)
668 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
669
670 alr_port = portmap_2_alrport[port_map & 7];
671 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
672 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
673
674 dat0 = 0;
675 dat0 |= (mac[0] << 0);
676 dat0 |= (mac[1] << 8);
677 dat0 |= (mac[2] << 16);
678 dat0 |= (mac[3] << 24);
679
680 dat1 |= (mac[4] << 0);
681 dat1 |= (mac[5] << 8);
682
683 lan9303_alr_make_entry_raw(chip, dat0, dat1);
684}
685
686/* Add port to static ALR entry, create new static entry if needed */
687static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
688 bool stp_override)
689{
690 struct lan9303_alr_cache_entry *entr;
691
692 mutex_lock(&chip->alr_mutex);
693 entr = lan9303_alr_cache_find_mac(chip, mac);
694 if (!entr) { /*New entry */
695 entr = lan9303_alr_cache_find_free(chip);
696 if (!entr) {
697 mutex_unlock(&chip->alr_mutex);
698 return -ENOSPC;
699 }
700 ether_addr_copy(entr->mac_addr, mac);
701 }
702 entr->port_map |= BIT(port);
703 entr->stp_override = stp_override;
704 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
705 mutex_unlock(&chip->alr_mutex);
706
707 return 0;
708}
709
710/* Delete static port from ALR entry, delete entry if last port */
711static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
712{
713 struct lan9303_alr_cache_entry *entr;
714
715 mutex_lock(&chip->alr_mutex);
716 entr = lan9303_alr_cache_find_mac(chip, mac);
717 if (!entr)
718 goto out; /* no static entry found */
719
720 entr->port_map &= ~BIT(port);
721 if (entr->port_map == 0) /* zero means its free again */
722 eth_zero_addr(entr->mac_addr);
723 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
724
725out:
726 mutex_unlock(&chip->alr_mutex);
727 return 0;
728}
729
730static int lan9303_disable_processing_port(struct lan9303 *chip,
731 unsigned int port)
732{
733 int ret;
734
735 /* disable RX, but keep register reset default values else */
736 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
737 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
738 if (ret)
739 return ret;
740
741 /* disable TX, but keep register reset default values else */
742 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
743 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
744 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
745}
746
747static int lan9303_enable_processing_port(struct lan9303 *chip,
748 unsigned int port)
749{
750 int ret;
751
752 /* enable RX and keep register reset default values else */
753 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
754 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
755 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
756 if (ret)
757 return ret;
758
759 /* enable TX and keep register reset default values else */
760 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
761 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
762 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
763 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
764}
765
766/* forward special tagged packets from port 0 to port 1 *or* port 2 */
767static int lan9303_setup_tagging(struct lan9303 *chip)
768{
769 int ret;
770 u32 val;
771 /* enable defining the destination port via special VLAN tagging
772 * for port 0
773 */
774 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
775 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
776 if (ret)
777 return ret;
778
779 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
780 * able to discover their source port
781 */
782 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
783 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
784}
785
786/* We want a special working switch:
787 * - do not forward packets between port 1 and 2
788 * - forward everything from port 1 to port 0
789 * - forward everything from port 2 to port 0
790 */
791static int lan9303_separate_ports(struct lan9303 *chip)
792{
793 int ret;
794
795 lan9303_alr_del_port(chip, eth_stp_addr, 0);
796 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
797 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
798 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
799 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
800 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
801 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
802 if (ret)
803 return ret;
804
805 /* prevent port 1 and 2 from forwarding packets by their own */
806 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
807 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
808 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
809 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
810}
811
812static void lan9303_bridge_ports(struct lan9303 *chip)
813{
814 /* ports bridged: remove mirroring */
815 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
816 LAN9303_SWE_PORT_MIRROR_DISABLED);
817
818 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
819 chip->swe_port_state);
820 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
821}
822
823static void lan9303_handle_reset(struct lan9303 *chip)
824{
825 if (!chip->reset_gpio)
826 return;
827
828 if (chip->reset_duration != 0)
829 msleep(chip->reset_duration);
830
831 /* release (deassert) reset and activate the device */
832 gpiod_set_value_cansleep(chip->reset_gpio, 0);
833}
834
835/* stop processing packets for all ports */
836static int lan9303_disable_processing(struct lan9303 *chip)
837{
838 int p;
839
840 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
841 int ret = lan9303_disable_processing_port(chip, p);
842
843 if (ret)
844 return ret;
845 }
846
847 return 0;
848}
849
850static int lan9303_check_device(struct lan9303 *chip)
851{
852 int ret;
853 u32 reg;
854
855 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
856 if (ret) {
857 dev_err(chip->dev, "failed to read chip revision register: %d\n",
858 ret);
859 return ret;
860 }
861
862 if (((reg >> 16) != LAN9303_CHIP_ID) &&
863 ((reg >> 16) != LAN9354_CHIP_ID)) {
864 dev_err(chip->dev, "unexpected device found: LAN%4.4X\n",
865 reg >> 16);
866 return -ENODEV;
867 }
868
869 /* The default state of the LAN9303 device is to forward packets between
870 * all ports (if not configured differently by an external EEPROM).
871 * The initial state of a DSA device must be forwarding packets only
872 * between the external and the internal ports and no forwarding
873 * between the external ports. In preparation we stop packet handling
874 * at all for now until the LAN9303 device is re-programmed accordingly.
875 */
876 ret = lan9303_disable_processing(chip);
877 if (ret)
878 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
879
880 dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff);
881
882 ret = lan9303_detect_phy_setup(chip);
883 if (ret) {
884 dev_err(chip->dev,
885 "failed to discover phy bootstrap setup: %d\n", ret);
886 return ret;
887 }
888
889 return 0;
890}
891
892/* ---------------------------- DSA -----------------------------------*/
893
894static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
895 int port,
896 enum dsa_tag_protocol mp)
897{
898 return DSA_TAG_PROTO_LAN9303;
899}
900
901static int lan9303_setup(struct dsa_switch *ds)
902{
903 struct lan9303 *chip = ds->priv;
904 int ret;
905
906 /* Make sure that port 0 is the cpu port */
907 if (!dsa_is_cpu_port(ds, 0)) {
908 dev_err(chip->dev, "port 0 is not the CPU port\n");
909 return -EINVAL;
910 }
911
912 ret = lan9303_setup_tagging(chip);
913 if (ret)
914 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
915
916 ret = lan9303_separate_ports(chip);
917 if (ret)
918 dev_err(chip->dev, "failed to separate ports %d\n", ret);
919
920 ret = lan9303_enable_processing_port(chip, 0);
921 if (ret)
922 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
923
924 /* Trap IGMP to port 0 */
925 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
926 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
927 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
928 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
929 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
930 if (ret)
931 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
932
933 return 0;
934}
935
936struct lan9303_mib_desc {
937 unsigned int offset; /* offset of first MAC */
938 const char *name;
939};
940
941static const struct lan9303_mib_desc lan9303_mib[] = {
942 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
943 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
944 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
945 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
946 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
947 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
948 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
949 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
950 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
951 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
952 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
953 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
954 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
955 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
956 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
957 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
958 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
959 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
960 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
961 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
962 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
963 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
964 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "RxShort", },
965 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
966 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
967 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
968 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
969 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
970 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
971 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
972 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
973 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
974 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
975 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
976 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
977 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
978 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
979};
980
981static void lan9303_get_strings(struct dsa_switch *ds, int port,
982 u32 stringset, uint8_t *data)
983{
984 unsigned int u;
985
986 if (stringset != ETH_SS_STATS)
987 return;
988
989 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
990 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
991 ETH_GSTRING_LEN);
992 }
993}
994
995static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
996 uint64_t *data)
997{
998 struct lan9303 *chip = ds->priv;
999 unsigned int u;
1000
1001 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1002 u32 reg;
1003 int ret;
1004
1005 ret = lan9303_read_switch_port(
1006 chip, port, lan9303_mib[u].offset, ®);
1007
1008 if (ret) {
1009 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1010 port, lan9303_mib[u].offset);
1011 reg = 0;
1012 }
1013 data[u] = reg;
1014 }
1015}
1016
1017static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
1018{
1019 if (sset != ETH_SS_STATS)
1020 return 0;
1021
1022 return ARRAY_SIZE(lan9303_mib);
1023}
1024
1025static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
1026{
1027 struct lan9303 *chip = ds->priv;
1028 int phy_base = chip->phy_addr_base;
1029
1030 if (phy == phy_base)
1031 return lan9303_virt_phy_reg_read(chip, regnum);
1032 if (phy > phy_base + 2)
1033 return -ENODEV;
1034
1035 return chip->ops->phy_read(chip, phy, regnum);
1036}
1037
1038static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
1039 u16 val)
1040{
1041 struct lan9303 *chip = ds->priv;
1042 int phy_base = chip->phy_addr_base;
1043
1044 if (phy == phy_base)
1045 return lan9303_virt_phy_reg_write(chip, regnum, val);
1046 if (phy > phy_base + 2)
1047 return -ENODEV;
1048
1049 return chip->ops->phy_write(chip, phy, regnum, val);
1050}
1051
1052static void lan9303_adjust_link(struct dsa_switch *ds, int port,
1053 struct phy_device *phydev)
1054{
1055 struct lan9303 *chip = ds->priv;
1056 int ctl;
1057
1058 if (!phy_is_pseudo_fixed_link(phydev))
1059 return;
1060
1061 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1062
1063 ctl &= ~BMCR_ANENABLE;
1064
1065 if (phydev->speed == SPEED_100)
1066 ctl |= BMCR_SPEED100;
1067 else if (phydev->speed == SPEED_10)
1068 ctl &= ~BMCR_SPEED100;
1069 else
1070 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed);
1071
1072 if (phydev->duplex == DUPLEX_FULL)
1073 ctl |= BMCR_FULLDPLX;
1074 else
1075 ctl &= ~BMCR_FULLDPLX;
1076
1077 lan9303_phy_write(ds, port, MII_BMCR, ctl);
1078
1079 if (port == chip->phy_addr_base) {
1080 /* Virtual Phy: Remove Turbo 200Mbit mode */
1081 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
1082
1083 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO;
1084 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ctl);
1085 }
1086}
1087
1088static int lan9303_port_enable(struct dsa_switch *ds, int port,
1089 struct phy_device *phy)
1090{
1091 struct dsa_port *dp = dsa_to_port(ds, port);
1092 struct lan9303 *chip = ds->priv;
1093
1094 if (!dsa_port_is_user(dp))
1095 return 0;
1096
1097 vlan_vid_add(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1098
1099 return lan9303_enable_processing_port(chip, port);
1100}
1101
1102static void lan9303_port_disable(struct dsa_switch *ds, int port)
1103{
1104 struct dsa_port *dp = dsa_to_port(ds, port);
1105 struct lan9303 *chip = ds->priv;
1106
1107 if (!dsa_port_is_user(dp))
1108 return;
1109
1110 vlan_vid_del(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1111
1112 lan9303_disable_processing_port(chip, port);
1113 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
1114}
1115
1116static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1117 struct dsa_bridge bridge,
1118 bool *tx_fwd_offload,
1119 struct netlink_ext_ack *extack)
1120{
1121 struct lan9303 *chip = ds->priv;
1122
1123 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1124 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) {
1125 lan9303_bridge_ports(chip);
1126 chip->is_bridged = true; /* unleash stp_state_set() */
1127 }
1128
1129 return 0;
1130}
1131
1132static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1133 struct dsa_bridge bridge)
1134{
1135 struct lan9303 *chip = ds->priv;
1136
1137 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1138 if (chip->is_bridged) {
1139 lan9303_separate_ports(chip);
1140 chip->is_bridged = false;
1141 }
1142}
1143
1144static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1145 u8 state)
1146{
1147 int portmask, portstate;
1148 struct lan9303 *chip = ds->priv;
1149
1150 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1151 __func__, port, state);
1152
1153 switch (state) {
1154 case BR_STATE_DISABLED:
1155 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1156 break;
1157 case BR_STATE_BLOCKING:
1158 case BR_STATE_LISTENING:
1159 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1160 break;
1161 case BR_STATE_LEARNING:
1162 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1163 break;
1164 case BR_STATE_FORWARDING:
1165 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1166 break;
1167 default:
1168 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1169 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1170 port, state);
1171 }
1172
1173 portmask = 0x3 << (port * 2);
1174 portstate <<= (port * 2);
1175
1176 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1177
1178 if (chip->is_bridged)
1179 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1180 chip->swe_port_state);
1181 /* else: touching SWE_PORT_STATE would break port separation */
1182}
1183
1184static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1185{
1186 struct lan9303 *chip = ds->priv;
1187 struct del_port_learned_ctx del_ctx = {
1188 .port = port,
1189 };
1190
1191 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1192 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1193}
1194
1195static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1196 const unsigned char *addr, u16 vid,
1197 struct dsa_db db)
1198{
1199 struct lan9303 *chip = ds->priv;
1200
1201 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1202 if (vid)
1203 return -EOPNOTSUPP;
1204
1205 return lan9303_alr_add_port(chip, addr, port, false);
1206}
1207
1208static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1209 const unsigned char *addr, u16 vid,
1210 struct dsa_db db)
1211{
1212 struct lan9303 *chip = ds->priv;
1213
1214 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1215 if (vid)
1216 return -EOPNOTSUPP;
1217 lan9303_alr_del_port(chip, addr, port);
1218
1219 return 0;
1220}
1221
1222static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1223 dsa_fdb_dump_cb_t *cb, void *data)
1224{
1225 struct lan9303 *chip = ds->priv;
1226 struct port_fdb_dump_ctx dump_ctx = {
1227 .port = port,
1228 .data = data,
1229 .cb = cb,
1230 };
1231
1232 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1233 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1234}
1235
1236static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1237 const struct switchdev_obj_port_mdb *mdb)
1238{
1239 struct lan9303 *chip = ds->priv;
1240
1241 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1242 mdb->vid);
1243 if (mdb->vid)
1244 return -EOPNOTSUPP;
1245 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1246 return 0;
1247 if (!lan9303_alr_cache_find_free(chip))
1248 return -ENOSPC;
1249
1250 return 0;
1251}
1252
1253static int lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1254 const struct switchdev_obj_port_mdb *mdb,
1255 struct dsa_db db)
1256{
1257 struct lan9303 *chip = ds->priv;
1258 int err;
1259
1260 err = lan9303_port_mdb_prepare(ds, port, mdb);
1261 if (err)
1262 return err;
1263
1264 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1265 mdb->vid);
1266 return lan9303_alr_add_port(chip, mdb->addr, port, false);
1267}
1268
1269static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1270 const struct switchdev_obj_port_mdb *mdb,
1271 struct dsa_db db)
1272{
1273 struct lan9303 *chip = ds->priv;
1274
1275 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1276 mdb->vid);
1277 if (mdb->vid)
1278 return -EOPNOTSUPP;
1279 lan9303_alr_del_port(chip, mdb->addr, port);
1280
1281 return 0;
1282}
1283
1284static const struct dsa_switch_ops lan9303_switch_ops = {
1285 .get_tag_protocol = lan9303_get_tag_protocol,
1286 .setup = lan9303_setup,
1287 .get_strings = lan9303_get_strings,
1288 .phy_read = lan9303_phy_read,
1289 .phy_write = lan9303_phy_write,
1290 .adjust_link = lan9303_adjust_link,
1291 .get_ethtool_stats = lan9303_get_ethtool_stats,
1292 .get_sset_count = lan9303_get_sset_count,
1293 .port_enable = lan9303_port_enable,
1294 .port_disable = lan9303_port_disable,
1295 .port_bridge_join = lan9303_port_bridge_join,
1296 .port_bridge_leave = lan9303_port_bridge_leave,
1297 .port_stp_state_set = lan9303_port_stp_state_set,
1298 .port_fast_age = lan9303_port_fast_age,
1299 .port_fdb_add = lan9303_port_fdb_add,
1300 .port_fdb_del = lan9303_port_fdb_del,
1301 .port_fdb_dump = lan9303_port_fdb_dump,
1302 .port_mdb_add = lan9303_port_mdb_add,
1303 .port_mdb_del = lan9303_port_mdb_del,
1304};
1305
1306static int lan9303_register_switch(struct lan9303 *chip)
1307{
1308 int base;
1309
1310 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL);
1311 if (!chip->ds)
1312 return -ENOMEM;
1313
1314 chip->ds->dev = chip->dev;
1315 chip->ds->num_ports = LAN9303_NUM_PORTS;
1316 chip->ds->priv = chip;
1317 chip->ds->ops = &lan9303_switch_ops;
1318 base = chip->phy_addr_base;
1319 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
1320
1321 return dsa_register_switch(chip->ds);
1322}
1323
1324static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1325 struct device_node *np)
1326{
1327 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1328 GPIOD_OUT_HIGH);
1329 if (IS_ERR(chip->reset_gpio))
1330 return PTR_ERR(chip->reset_gpio);
1331
1332 if (!chip->reset_gpio) {
1333 dev_dbg(chip->dev, "No reset GPIO defined\n");
1334 return 0;
1335 }
1336
1337 chip->reset_duration = 200;
1338
1339 if (np) {
1340 of_property_read_u32(np, "reset-duration",
1341 &chip->reset_duration);
1342 } else {
1343 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1344 }
1345
1346 /* A sane reset duration should not be longer than 1s */
1347 if (chip->reset_duration > 1000)
1348 chip->reset_duration = 1000;
1349
1350 return 0;
1351}
1352
1353int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1354{
1355 int ret;
1356 u32 reg;
1357
1358 mutex_init(&chip->indirect_mutex);
1359 mutex_init(&chip->alr_mutex);
1360
1361 ret = lan9303_probe_reset_gpio(chip, np);
1362 if (ret)
1363 return ret;
1364
1365 lan9303_handle_reset(chip);
1366
1367 /* First read to the device. This is a Dummy read to ensure MDIO */
1368 /* access is in 32-bit sync. */
1369 ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, ®);
1370 if (ret) {
1371 dev_err(chip->dev, "failed to access the device: %d\n",
1372 ret);
1373 if (!chip->reset_gpio) {
1374 dev_dbg(chip->dev,
1375 "hint: maybe failed due to missing reset GPIO\n");
1376 }
1377 return ret;
1378 }
1379
1380 ret = lan9303_check_device(chip);
1381 if (ret)
1382 return ret;
1383
1384 ret = lan9303_register_switch(chip);
1385 if (ret) {
1386 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1387 return ret;
1388 }
1389
1390 return 0;
1391}
1392EXPORT_SYMBOL(lan9303_probe);
1393
1394int lan9303_remove(struct lan9303 *chip)
1395{
1396 int rc;
1397
1398 rc = lan9303_disable_processing(chip);
1399 if (rc != 0)
1400 dev_warn(chip->dev, "shutting down failed\n");
1401
1402 dsa_unregister_switch(chip->ds);
1403
1404 /* assert reset to the whole device to prevent it from doing anything */
1405 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1406 gpiod_unexport(chip->reset_gpio);
1407
1408 return 0;
1409}
1410EXPORT_SYMBOL(lan9303_remove);
1411
1412void lan9303_shutdown(struct lan9303 *chip)
1413{
1414 dsa_switch_shutdown(chip->ds);
1415}
1416EXPORT_SYMBOL(lan9303_shutdown);
1417
1418MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1419MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1420MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
4 */
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/gpio/consumer.h>
8#include <linux/regmap.h>
9#include <linux/mutex.h>
10#include <linux/mii.h>
11#include <linux/phy.h>
12#include <linux/if_bridge.h>
13#include <linux/etherdevice.h>
14
15#include "lan9303.h"
16
17#define LAN9303_NUM_PORTS 3
18
19/* 13.2 System Control and Status Registers
20 * Multiply register number by 4 to get address offset.
21 */
22#define LAN9303_CHIP_REV 0x14
23# define LAN9303_CHIP_ID 0x9303
24#define LAN9303_IRQ_CFG 0x15
25# define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
26# define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
27# define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
28#define LAN9303_INT_STS 0x16
29# define LAN9303_INT_STS_PHY_INT2 BIT(27)
30# define LAN9303_INT_STS_PHY_INT1 BIT(26)
31#define LAN9303_INT_EN 0x17
32# define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
33# define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
34#define LAN9303_HW_CFG 0x1D
35# define LAN9303_HW_CFG_READY BIT(27)
36# define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
37# define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
38#define LAN9303_PMI_DATA 0x29
39#define LAN9303_PMI_ACCESS 0x2A
40# define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
41# define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
42# define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
43# define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
44#define LAN9303_MANUAL_FC_1 0x68
45#define LAN9303_MANUAL_FC_2 0x69
46#define LAN9303_MANUAL_FC_0 0x6a
47#define LAN9303_SWITCH_CSR_DATA 0x6b
48#define LAN9303_SWITCH_CSR_CMD 0x6c
49#define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
50#define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
51#define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
52#define LAN9303_VIRT_PHY_BASE 0x70
53#define LAN9303_VIRT_SPECIAL_CTRL 0x77
54#define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
55
56/*13.4 Switch Fabric Control and Status Registers
57 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
58 */
59#define LAN9303_SW_DEV_ID 0x0000
60#define LAN9303_SW_RESET 0x0001
61#define LAN9303_SW_RESET_RESET BIT(0)
62#define LAN9303_SW_IMR 0x0004
63#define LAN9303_SW_IPR 0x0005
64#define LAN9303_MAC_VER_ID_0 0x0400
65#define LAN9303_MAC_RX_CFG_0 0x0401
66# define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
67# define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
68#define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
69#define LAN9303_MAC_RX_64_CNT_0 0x0411
70#define LAN9303_MAC_RX_127_CNT_0 0x0412
71#define LAN9303_MAC_RX_255_CNT_0 0x413
72#define LAN9303_MAC_RX_511_CNT_0 0x0414
73#define LAN9303_MAC_RX_1023_CNT_0 0x0415
74#define LAN9303_MAC_RX_MAX_CNT_0 0x0416
75#define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
76#define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
77#define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
78#define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
79#define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
80#define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
81#define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
82#define LAN9303_MAC_RX_JABB_CNT_0 0x041e
83#define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
84#define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
85#define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
86#define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
87#define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
88
89#define LAN9303_MAC_TX_CFG_0 0x0440
90# define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
91# define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
92# define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
93#define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
94#define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
95#define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
96#define LAN9303_MAC_TX_64_CNT_0 0x0454
97#define LAN9303_MAC_TX_127_CNT_0 0x0455
98#define LAN9303_MAC_TX_255_CNT_0 0x0456
99#define LAN9303_MAC_TX_511_CNT_0 0x0457
100#define LAN9303_MAC_TX_1023_CNT_0 0x0458
101#define LAN9303_MAC_TX_MAX_CNT_0 0x0459
102#define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
103#define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
104#define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
105#define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
106#define LAN9303_MAC_TX_LATECOL_0 0x045f
107#define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
108#define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
109#define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
110#define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
111
112#define LAN9303_MAC_VER_ID_1 0x0800
113#define LAN9303_MAC_RX_CFG_1 0x0801
114#define LAN9303_MAC_TX_CFG_1 0x0840
115#define LAN9303_MAC_VER_ID_2 0x0c00
116#define LAN9303_MAC_RX_CFG_2 0x0c01
117#define LAN9303_MAC_TX_CFG_2 0x0c40
118#define LAN9303_SWE_ALR_CMD 0x1800
119# define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
120# define LAN9303_ALR_CMD_GET_FIRST BIT(1)
121# define LAN9303_ALR_CMD_GET_NEXT BIT(0)
122#define LAN9303_SWE_ALR_WR_DAT_0 0x1801
123#define LAN9303_SWE_ALR_WR_DAT_1 0x1802
124# define LAN9303_ALR_DAT1_VALID BIT(26)
125# define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
126# define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
127# define LAN9303_ALR_DAT1_STATIC BIT(24)
128# define LAN9303_ALR_DAT1_PORT_BITOFFS 16
129# define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
130#define LAN9303_SWE_ALR_RD_DAT_0 0x1805
131#define LAN9303_SWE_ALR_RD_DAT_1 0x1806
132#define LAN9303_SWE_ALR_CMD_STS 0x1808
133# define ALR_STS_MAKE_PEND BIT(0)
134#define LAN9303_SWE_VLAN_CMD 0x180b
135# define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
136# define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
137#define LAN9303_SWE_VLAN_WR_DATA 0x180c
138#define LAN9303_SWE_VLAN_RD_DATA 0x180e
139# define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
140# define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
141# define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
142# define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
143# define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
144# define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
145#define LAN9303_SWE_VLAN_CMD_STS 0x1810
146#define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
147# define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
148# define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
149#define LAN9303_SWE_PORT_STATE 0x1843
150# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
151# define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
152# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
153# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
154# define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
155# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
156# define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
157# define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
158# define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
159# define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
160#define LAN9303_SWE_PORT_MIRROR 0x1846
161# define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
162# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
163# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
164# define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
165# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
166# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
167# define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
168# define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
169# define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
170# define LAN9303_SWE_PORT_MIRROR_DISABLED 0
171#define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
172#define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
173#define LAN9303_BM_CFG 0x1c00
174#define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
175# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
176# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
177# define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
178
179#define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
180
181/* the built-in PHYs are of type LAN911X */
182#define MII_LAN911X_SPECIAL_MODES 0x12
183#define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
184
185static const struct regmap_range lan9303_valid_regs[] = {
186 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
187 regmap_reg_range(0x19, 0x19), /* endian test */
188 regmap_reg_range(0x1d, 0x1d), /* hardware config */
189 regmap_reg_range(0x23, 0x24), /* general purpose timer */
190 regmap_reg_range(0x27, 0x27), /* counter */
191 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
192 regmap_reg_range(0x68, 0x6a), /* flow control */
193 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
194 regmap_reg_range(0x6d, 0x6f), /* misc */
195 regmap_reg_range(0x70, 0x77), /* virtual phy */
196 regmap_reg_range(0x78, 0x7a), /* GPIO */
197 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
198 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
199};
200
201static const struct regmap_range lan9303_reserved_ranges[] = {
202 regmap_reg_range(0x00, 0x13),
203 regmap_reg_range(0x18, 0x18),
204 regmap_reg_range(0x1a, 0x1c),
205 regmap_reg_range(0x1e, 0x22),
206 regmap_reg_range(0x25, 0x26),
207 regmap_reg_range(0x28, 0x28),
208 regmap_reg_range(0x2b, 0x67),
209 regmap_reg_range(0x7b, 0x7b),
210 regmap_reg_range(0x7f, 0x7f),
211 regmap_reg_range(0xb8, 0xff),
212};
213
214const struct regmap_access_table lan9303_register_set = {
215 .yes_ranges = lan9303_valid_regs,
216 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
217 .no_ranges = lan9303_reserved_ranges,
218 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
219};
220EXPORT_SYMBOL(lan9303_register_set);
221
222static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
223{
224 int ret, i;
225
226 /* we can lose arbitration for the I2C case, because the device
227 * tries to detect and read an external EEPROM after reset and acts as
228 * a master on the shared I2C bus itself. This conflicts with our
229 * attempts to access the device as a slave at the same moment.
230 */
231 for (i = 0; i < 5; i++) {
232 ret = regmap_read(regmap, offset, reg);
233 if (!ret)
234 return 0;
235 if (ret != -EAGAIN)
236 break;
237 msleep(500);
238 }
239
240 return -EIO;
241}
242
243static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
244{
245 int i;
246
247 for (i = 0; i < 25; i++) {
248 u32 reg;
249 int ret;
250
251 ret = lan9303_read(chip->regmap, offset, ®);
252 if (ret) {
253 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
254 __func__, offset, ret);
255 return ret;
256 }
257 if (!(reg & mask))
258 return 0;
259 usleep_range(1000, 2000);
260 }
261
262 return -ETIMEDOUT;
263}
264
265static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
266{
267 int ret;
268 u32 val;
269
270 if (regnum > MII_EXPANSION)
271 return -EINVAL;
272
273 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
274 if (ret)
275 return ret;
276
277 return val & 0xffff;
278}
279
280static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
281{
282 if (regnum > MII_EXPANSION)
283 return -EINVAL;
284
285 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
286}
287
288static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
289{
290 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
291 LAN9303_PMI_ACCESS_MII_BUSY);
292}
293
294static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
295{
296 int ret;
297 u32 val;
298
299 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
300 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
301
302 mutex_lock(&chip->indirect_mutex);
303
304 ret = lan9303_indirect_phy_wait_for_completion(chip);
305 if (ret)
306 goto on_error;
307
308 /* start the MII read cycle */
309 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
310 if (ret)
311 goto on_error;
312
313 ret = lan9303_indirect_phy_wait_for_completion(chip);
314 if (ret)
315 goto on_error;
316
317 /* read the result of this operation */
318 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
319 if (ret)
320 goto on_error;
321
322 mutex_unlock(&chip->indirect_mutex);
323
324 return val & 0xffff;
325
326on_error:
327 mutex_unlock(&chip->indirect_mutex);
328 return ret;
329}
330
331static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
332 int regnum, u16 val)
333{
334 int ret;
335 u32 reg;
336
337 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
338 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
339 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
340
341 mutex_lock(&chip->indirect_mutex);
342
343 ret = lan9303_indirect_phy_wait_for_completion(chip);
344 if (ret)
345 goto on_error;
346
347 /* write the data first... */
348 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
349 if (ret)
350 goto on_error;
351
352 /* ...then start the MII write cycle */
353 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
354
355on_error:
356 mutex_unlock(&chip->indirect_mutex);
357 return ret;
358}
359
360const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
361 .phy_read = lan9303_indirect_phy_read,
362 .phy_write = lan9303_indirect_phy_write,
363};
364EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
365
366static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
367{
368 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
369 LAN9303_SWITCH_CSR_CMD_BUSY);
370}
371
372static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
373{
374 u32 reg;
375 int ret;
376
377 reg = regnum;
378 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
379 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
380
381 mutex_lock(&chip->indirect_mutex);
382
383 ret = lan9303_switch_wait_for_completion(chip);
384 if (ret)
385 goto on_error;
386
387 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
388 if (ret) {
389 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
390 goto on_error;
391 }
392
393 /* trigger write */
394 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
395 if (ret)
396 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
397 ret);
398
399on_error:
400 mutex_unlock(&chip->indirect_mutex);
401 return ret;
402}
403
404static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
405{
406 u32 reg;
407 int ret;
408
409 reg = regnum;
410 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
411 reg |= LAN9303_SWITCH_CSR_CMD_RW;
412 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
413
414 mutex_lock(&chip->indirect_mutex);
415
416 ret = lan9303_switch_wait_for_completion(chip);
417 if (ret)
418 goto on_error;
419
420 /* trigger read */
421 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
422 if (ret) {
423 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
424 ret);
425 goto on_error;
426 }
427
428 ret = lan9303_switch_wait_for_completion(chip);
429 if (ret)
430 goto on_error;
431
432 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
433 if (ret)
434 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
435on_error:
436 mutex_unlock(&chip->indirect_mutex);
437 return ret;
438}
439
440static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
441 u32 val, u32 mask)
442{
443 int ret;
444 u32 reg;
445
446 ret = lan9303_read_switch_reg(chip, regnum, ®);
447 if (ret)
448 return ret;
449
450 reg = (reg & ~mask) | val;
451
452 return lan9303_write_switch_reg(chip, regnum, reg);
453}
454
455static int lan9303_write_switch_port(struct lan9303 *chip, int port,
456 u16 regnum, u32 val)
457{
458 return lan9303_write_switch_reg(
459 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
460}
461
462static int lan9303_read_switch_port(struct lan9303 *chip, int port,
463 u16 regnum, u32 *val)
464{
465 return lan9303_read_switch_reg(
466 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
467}
468
469static int lan9303_detect_phy_setup(struct lan9303 *chip)
470{
471 int reg;
472
473 /* Calculate chip->phy_addr_base:
474 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
475 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
476 * 'phy_addr_sel_strap' setting directly, so we need a test, which
477 * configuration is active:
478 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
479 * and the IDs are 0-1-2, else it contains something different from
480 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
481 * 0xffff is returned on MDIO read with no response.
482 */
483 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
484 if (reg < 0) {
485 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
486 return reg;
487 }
488
489 chip->phy_addr_base = reg != 0 && reg != 0xffff;
490
491 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
492 chip->phy_addr_base ? "1-2-3" : "0-1-2");
493
494 return 0;
495}
496
497/* Map ALR-port bits to port bitmap, and back */
498static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
499static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
500
501/* Return pointer to first free ALR cache entry, return NULL if none */
502static struct lan9303_alr_cache_entry *
503lan9303_alr_cache_find_free(struct lan9303 *chip)
504{
505 int i;
506 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
507
508 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
509 if (entr->port_map == 0)
510 return entr;
511
512 return NULL;
513}
514
515/* Return pointer to ALR cache entry matching MAC address */
516static struct lan9303_alr_cache_entry *
517lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
518{
519 int i;
520 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
521
522 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
523 "ether_addr_equal require u16 alignment");
524
525 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
526 if (ether_addr_equal(entr->mac_addr, mac_addr))
527 return entr;
528
529 return NULL;
530}
531
532static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
533{
534 int i;
535
536 for (i = 0; i < 25; i++) {
537 u32 reg;
538
539 lan9303_read_switch_reg(chip, regno, ®);
540 if (!(reg & mask))
541 return 0;
542 usleep_range(1000, 2000);
543 }
544
545 return -ETIMEDOUT;
546}
547
548static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
549{
550 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
551 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
552 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
553 LAN9303_ALR_CMD_MAKE_ENTRY);
554 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
555 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
556
557 return 0;
558}
559
560typedef void alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
561 int portmap, void *ctx);
562
563static void lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
564{
565 int i;
566
567 mutex_lock(&chip->alr_mutex);
568 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
569 LAN9303_ALR_CMD_GET_FIRST);
570 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
571
572 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
573 u32 dat0, dat1;
574 int alrport, portmap;
575
576 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
577 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
578 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
579 break;
580
581 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
582 LAN9303_ALR_DAT1_PORT_BITOFFS;
583 portmap = alrport_2_portmap[alrport];
584
585 cb(chip, dat0, dat1, portmap, ctx);
586
587 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
588 LAN9303_ALR_CMD_GET_NEXT);
589 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
590 }
591 mutex_unlock(&chip->alr_mutex);
592}
593
594static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
595{
596 mac[0] = (dat0 >> 0) & 0xff;
597 mac[1] = (dat0 >> 8) & 0xff;
598 mac[2] = (dat0 >> 16) & 0xff;
599 mac[3] = (dat0 >> 24) & 0xff;
600 mac[4] = (dat1 >> 0) & 0xff;
601 mac[5] = (dat1 >> 8) & 0xff;
602}
603
604struct del_port_learned_ctx {
605 int port;
606};
607
608/* Clear learned (non-static) entry on given port */
609static void alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
610 u32 dat1, int portmap, void *ctx)
611{
612 struct del_port_learned_ctx *del_ctx = ctx;
613 int port = del_ctx->port;
614
615 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
616 return;
617
618 /* learned entries has only one port, we can just delete */
619 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
620 lan9303_alr_make_entry_raw(chip, dat0, dat1);
621}
622
623struct port_fdb_dump_ctx {
624 int port;
625 void *data;
626 dsa_fdb_dump_cb_t *cb;
627};
628
629static void alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
630 u32 dat1, int portmap, void *ctx)
631{
632 struct port_fdb_dump_ctx *dump_ctx = ctx;
633 u8 mac[ETH_ALEN];
634 bool is_static;
635
636 if ((BIT(dump_ctx->port) & portmap) == 0)
637 return;
638
639 alr_reg_to_mac(dat0, dat1, mac);
640 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
641 dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
642}
643
644/* Set a static ALR entry. Delete entry if port_map is zero */
645static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
646 u8 port_map, bool stp_override)
647{
648 u32 dat0, dat1, alr_port;
649
650 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
651 dat1 = LAN9303_ALR_DAT1_STATIC;
652 if (port_map)
653 dat1 |= LAN9303_ALR_DAT1_VALID;
654 /* otherwise no ports: delete entry */
655 if (stp_override)
656 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
657
658 alr_port = portmap_2_alrport[port_map & 7];
659 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
660 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
661
662 dat0 = 0;
663 dat0 |= (mac[0] << 0);
664 dat0 |= (mac[1] << 8);
665 dat0 |= (mac[2] << 16);
666 dat0 |= (mac[3] << 24);
667
668 dat1 |= (mac[4] << 0);
669 dat1 |= (mac[5] << 8);
670
671 lan9303_alr_make_entry_raw(chip, dat0, dat1);
672}
673
674/* Add port to static ALR entry, create new static entry if needed */
675static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
676 bool stp_override)
677{
678 struct lan9303_alr_cache_entry *entr;
679
680 mutex_lock(&chip->alr_mutex);
681 entr = lan9303_alr_cache_find_mac(chip, mac);
682 if (!entr) { /*New entry */
683 entr = lan9303_alr_cache_find_free(chip);
684 if (!entr) {
685 mutex_unlock(&chip->alr_mutex);
686 return -ENOSPC;
687 }
688 ether_addr_copy(entr->mac_addr, mac);
689 }
690 entr->port_map |= BIT(port);
691 entr->stp_override = stp_override;
692 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
693 mutex_unlock(&chip->alr_mutex);
694
695 return 0;
696}
697
698/* Delete static port from ALR entry, delete entry if last port */
699static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
700{
701 struct lan9303_alr_cache_entry *entr;
702
703 mutex_lock(&chip->alr_mutex);
704 entr = lan9303_alr_cache_find_mac(chip, mac);
705 if (!entr)
706 goto out; /* no static entry found */
707
708 entr->port_map &= ~BIT(port);
709 if (entr->port_map == 0) /* zero means its free again */
710 eth_zero_addr(entr->mac_addr);
711 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
712
713out:
714 mutex_unlock(&chip->alr_mutex);
715 return 0;
716}
717
718static int lan9303_disable_processing_port(struct lan9303 *chip,
719 unsigned int port)
720{
721 int ret;
722
723 /* disable RX, but keep register reset default values else */
724 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
725 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
726 if (ret)
727 return ret;
728
729 /* disable TX, but keep register reset default values else */
730 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
731 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
732 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
733}
734
735static int lan9303_enable_processing_port(struct lan9303 *chip,
736 unsigned int port)
737{
738 int ret;
739
740 /* enable RX and keep register reset default values else */
741 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
742 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
743 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
744 if (ret)
745 return ret;
746
747 /* enable TX and keep register reset default values else */
748 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
749 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
750 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
751 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
752}
753
754/* forward special tagged packets from port 0 to port 1 *or* port 2 */
755static int lan9303_setup_tagging(struct lan9303 *chip)
756{
757 int ret;
758 u32 val;
759 /* enable defining the destination port via special VLAN tagging
760 * for port 0
761 */
762 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
763 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
764 if (ret)
765 return ret;
766
767 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
768 * able to discover their source port
769 */
770 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
771 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
772}
773
774/* We want a special working switch:
775 * - do not forward packets between port 1 and 2
776 * - forward everything from port 1 to port 0
777 * - forward everything from port 2 to port 0
778 */
779static int lan9303_separate_ports(struct lan9303 *chip)
780{
781 int ret;
782
783 lan9303_alr_del_port(chip, eth_stp_addr, 0);
784 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
785 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
786 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
787 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
788 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
789 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
790 if (ret)
791 return ret;
792
793 /* prevent port 1 and 2 from forwarding packets by their own */
794 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
795 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
796 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
797 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
798}
799
800static void lan9303_bridge_ports(struct lan9303 *chip)
801{
802 /* ports bridged: remove mirroring */
803 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
804 LAN9303_SWE_PORT_MIRROR_DISABLED);
805
806 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
807 chip->swe_port_state);
808 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
809}
810
811static void lan9303_handle_reset(struct lan9303 *chip)
812{
813 if (!chip->reset_gpio)
814 return;
815
816 if (chip->reset_duration != 0)
817 msleep(chip->reset_duration);
818
819 /* release (deassert) reset and activate the device */
820 gpiod_set_value_cansleep(chip->reset_gpio, 0);
821}
822
823/* stop processing packets for all ports */
824static int lan9303_disable_processing(struct lan9303 *chip)
825{
826 int p;
827
828 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
829 int ret = lan9303_disable_processing_port(chip, p);
830
831 if (ret)
832 return ret;
833 }
834
835 return 0;
836}
837
838static int lan9303_check_device(struct lan9303 *chip)
839{
840 int ret;
841 u32 reg;
842
843 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
844 if (ret) {
845 dev_err(chip->dev, "failed to read chip revision register: %d\n",
846 ret);
847 if (!chip->reset_gpio) {
848 dev_dbg(chip->dev,
849 "hint: maybe failed due to missing reset GPIO\n");
850 }
851 return ret;
852 }
853
854 if ((reg >> 16) != LAN9303_CHIP_ID) {
855 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
856 reg >> 16);
857 return -ENODEV;
858 }
859
860 /* The default state of the LAN9303 device is to forward packets between
861 * all ports (if not configured differently by an external EEPROM).
862 * The initial state of a DSA device must be forwarding packets only
863 * between the external and the internal ports and no forwarding
864 * between the external ports. In preparation we stop packet handling
865 * at all for now until the LAN9303 device is re-programmed accordingly.
866 */
867 ret = lan9303_disable_processing(chip);
868 if (ret)
869 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
870
871 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
872
873 ret = lan9303_detect_phy_setup(chip);
874 if (ret) {
875 dev_err(chip->dev,
876 "failed to discover phy bootstrap setup: %d\n", ret);
877 return ret;
878 }
879
880 return 0;
881}
882
883/* ---------------------------- DSA -----------------------------------*/
884
885static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
886 int port)
887{
888 return DSA_TAG_PROTO_LAN9303;
889}
890
891static int lan9303_setup(struct dsa_switch *ds)
892{
893 struct lan9303 *chip = ds->priv;
894 int ret;
895
896 /* Make sure that port 0 is the cpu port */
897 if (!dsa_is_cpu_port(ds, 0)) {
898 dev_err(chip->dev, "port 0 is not the CPU port\n");
899 return -EINVAL;
900 }
901
902 ret = lan9303_setup_tagging(chip);
903 if (ret)
904 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
905
906 ret = lan9303_separate_ports(chip);
907 if (ret)
908 dev_err(chip->dev, "failed to separate ports %d\n", ret);
909
910 ret = lan9303_enable_processing_port(chip, 0);
911 if (ret)
912 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
913
914 /* Trap IGMP to port 0 */
915 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
916 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
917 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
918 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
919 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
920 if (ret)
921 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
922
923 return 0;
924}
925
926struct lan9303_mib_desc {
927 unsigned int offset; /* offset of first MAC */
928 const char *name;
929};
930
931static const struct lan9303_mib_desc lan9303_mib[] = {
932 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
933 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
934 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
935 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
936 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
937 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
938 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
939 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
940 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
941 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
942 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
943 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
944 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
945 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
946 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
947 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
948 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
949 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
950 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
951 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
952 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
953 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
954 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", },
955 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
956 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
957 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
958 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
959 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
960 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
961 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
962 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
963 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
964 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
965 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
966 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
967 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
968 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
969};
970
971static void lan9303_get_strings(struct dsa_switch *ds, int port,
972 u32 stringset, uint8_t *data)
973{
974 unsigned int u;
975
976 if (stringset != ETH_SS_STATS)
977 return;
978
979 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
980 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
981 ETH_GSTRING_LEN);
982 }
983}
984
985static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
986 uint64_t *data)
987{
988 struct lan9303 *chip = ds->priv;
989 unsigned int u;
990
991 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
992 u32 reg;
993 int ret;
994
995 ret = lan9303_read_switch_port(
996 chip, port, lan9303_mib[u].offset, ®);
997
998 if (ret)
999 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1000 port, lan9303_mib[u].offset);
1001 data[u] = reg;
1002 }
1003}
1004
1005static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
1006{
1007 if (sset != ETH_SS_STATS)
1008 return 0;
1009
1010 return ARRAY_SIZE(lan9303_mib);
1011}
1012
1013static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum)
1014{
1015 struct lan9303 *chip = ds->priv;
1016 int phy_base = chip->phy_addr_base;
1017
1018 if (phy == phy_base)
1019 return lan9303_virt_phy_reg_read(chip, regnum);
1020 if (phy > phy_base + 2)
1021 return -ENODEV;
1022
1023 return chip->ops->phy_read(chip, phy, regnum);
1024}
1025
1026static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum,
1027 u16 val)
1028{
1029 struct lan9303 *chip = ds->priv;
1030 int phy_base = chip->phy_addr_base;
1031
1032 if (phy == phy_base)
1033 return lan9303_virt_phy_reg_write(chip, regnum, val);
1034 if (phy > phy_base + 2)
1035 return -ENODEV;
1036
1037 return chip->ops->phy_write(chip, phy, regnum, val);
1038}
1039
1040static void lan9303_adjust_link(struct dsa_switch *ds, int port,
1041 struct phy_device *phydev)
1042{
1043 struct lan9303 *chip = ds->priv;
1044 int ctl, res;
1045
1046 if (!phy_is_pseudo_fixed_link(phydev))
1047 return;
1048
1049 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1050
1051 ctl &= ~BMCR_ANENABLE;
1052
1053 if (phydev->speed == SPEED_100)
1054 ctl |= BMCR_SPEED100;
1055 else if (phydev->speed == SPEED_10)
1056 ctl &= ~BMCR_SPEED100;
1057 else
1058 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed);
1059
1060 if (phydev->duplex == DUPLEX_FULL)
1061 ctl |= BMCR_FULLDPLX;
1062 else
1063 ctl &= ~BMCR_FULLDPLX;
1064
1065 res = lan9303_phy_write(ds, port, MII_BMCR, ctl);
1066
1067 if (port == chip->phy_addr_base) {
1068 /* Virtual Phy: Remove Turbo 200Mbit mode */
1069 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
1070
1071 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO;
1072 res = regmap_write(chip->regmap,
1073 LAN9303_VIRT_SPECIAL_CTRL, ctl);
1074 }
1075}
1076
1077static int lan9303_port_enable(struct dsa_switch *ds, int port,
1078 struct phy_device *phy)
1079{
1080 struct lan9303 *chip = ds->priv;
1081
1082 if (!dsa_is_user_port(ds, port))
1083 return 0;
1084
1085 return lan9303_enable_processing_port(chip, port);
1086}
1087
1088static void lan9303_port_disable(struct dsa_switch *ds, int port)
1089{
1090 struct lan9303 *chip = ds->priv;
1091
1092 if (!dsa_is_user_port(ds, port))
1093 return;
1094
1095 lan9303_disable_processing_port(chip, port);
1096 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
1097}
1098
1099static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1100 struct net_device *br)
1101{
1102 struct lan9303 *chip = ds->priv;
1103
1104 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1105 if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) {
1106 lan9303_bridge_ports(chip);
1107 chip->is_bridged = true; /* unleash stp_state_set() */
1108 }
1109
1110 return 0;
1111}
1112
1113static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1114 struct net_device *br)
1115{
1116 struct lan9303 *chip = ds->priv;
1117
1118 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1119 if (chip->is_bridged) {
1120 lan9303_separate_ports(chip);
1121 chip->is_bridged = false;
1122 }
1123}
1124
1125static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1126 u8 state)
1127{
1128 int portmask, portstate;
1129 struct lan9303 *chip = ds->priv;
1130
1131 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1132 __func__, port, state);
1133
1134 switch (state) {
1135 case BR_STATE_DISABLED:
1136 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1137 break;
1138 case BR_STATE_BLOCKING:
1139 case BR_STATE_LISTENING:
1140 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1141 break;
1142 case BR_STATE_LEARNING:
1143 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1144 break;
1145 case BR_STATE_FORWARDING:
1146 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1147 break;
1148 default:
1149 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1150 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1151 port, state);
1152 }
1153
1154 portmask = 0x3 << (port * 2);
1155 portstate <<= (port * 2);
1156
1157 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1158
1159 if (chip->is_bridged)
1160 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1161 chip->swe_port_state);
1162 /* else: touching SWE_PORT_STATE would break port separation */
1163}
1164
1165static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1166{
1167 struct lan9303 *chip = ds->priv;
1168 struct del_port_learned_ctx del_ctx = {
1169 .port = port,
1170 };
1171
1172 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1173 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1174}
1175
1176static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1177 const unsigned char *addr, u16 vid)
1178{
1179 struct lan9303 *chip = ds->priv;
1180
1181 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1182 if (vid)
1183 return -EOPNOTSUPP;
1184
1185 return lan9303_alr_add_port(chip, addr, port, false);
1186}
1187
1188static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1189 const unsigned char *addr, u16 vid)
1190
1191{
1192 struct lan9303 *chip = ds->priv;
1193
1194 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1195 if (vid)
1196 return -EOPNOTSUPP;
1197 lan9303_alr_del_port(chip, addr, port);
1198
1199 return 0;
1200}
1201
1202static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1203 dsa_fdb_dump_cb_t *cb, void *data)
1204{
1205 struct lan9303 *chip = ds->priv;
1206 struct port_fdb_dump_ctx dump_ctx = {
1207 .port = port,
1208 .data = data,
1209 .cb = cb,
1210 };
1211
1212 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1213 lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1214
1215 return 0;
1216}
1217
1218static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1219 const struct switchdev_obj_port_mdb *mdb)
1220{
1221 struct lan9303 *chip = ds->priv;
1222
1223 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1224 mdb->vid);
1225 if (mdb->vid)
1226 return -EOPNOTSUPP;
1227 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1228 return 0;
1229 if (!lan9303_alr_cache_find_free(chip))
1230 return -ENOSPC;
1231
1232 return 0;
1233}
1234
1235static void lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1236 const struct switchdev_obj_port_mdb *mdb)
1237{
1238 struct lan9303 *chip = ds->priv;
1239
1240 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1241 mdb->vid);
1242 lan9303_alr_add_port(chip, mdb->addr, port, false);
1243}
1244
1245static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1246 const struct switchdev_obj_port_mdb *mdb)
1247{
1248 struct lan9303 *chip = ds->priv;
1249
1250 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1251 mdb->vid);
1252 if (mdb->vid)
1253 return -EOPNOTSUPP;
1254 lan9303_alr_del_port(chip, mdb->addr, port);
1255
1256 return 0;
1257}
1258
1259static const struct dsa_switch_ops lan9303_switch_ops = {
1260 .get_tag_protocol = lan9303_get_tag_protocol,
1261 .setup = lan9303_setup,
1262 .get_strings = lan9303_get_strings,
1263 .phy_read = lan9303_phy_read,
1264 .phy_write = lan9303_phy_write,
1265 .adjust_link = lan9303_adjust_link,
1266 .get_ethtool_stats = lan9303_get_ethtool_stats,
1267 .get_sset_count = lan9303_get_sset_count,
1268 .port_enable = lan9303_port_enable,
1269 .port_disable = lan9303_port_disable,
1270 .port_bridge_join = lan9303_port_bridge_join,
1271 .port_bridge_leave = lan9303_port_bridge_leave,
1272 .port_stp_state_set = lan9303_port_stp_state_set,
1273 .port_fast_age = lan9303_port_fast_age,
1274 .port_fdb_add = lan9303_port_fdb_add,
1275 .port_fdb_del = lan9303_port_fdb_del,
1276 .port_fdb_dump = lan9303_port_fdb_dump,
1277 .port_mdb_prepare = lan9303_port_mdb_prepare,
1278 .port_mdb_add = lan9303_port_mdb_add,
1279 .port_mdb_del = lan9303_port_mdb_del,
1280};
1281
1282static int lan9303_register_switch(struct lan9303 *chip)
1283{
1284 int base;
1285
1286 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS);
1287 if (!chip->ds)
1288 return -ENOMEM;
1289
1290 chip->ds->priv = chip;
1291 chip->ds->ops = &lan9303_switch_ops;
1292 base = chip->phy_addr_base;
1293 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
1294
1295 return dsa_register_switch(chip->ds);
1296}
1297
1298static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1299 struct device_node *np)
1300{
1301 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1302 GPIOD_OUT_LOW);
1303 if (IS_ERR(chip->reset_gpio))
1304 return PTR_ERR(chip->reset_gpio);
1305
1306 if (!chip->reset_gpio) {
1307 dev_dbg(chip->dev, "No reset GPIO defined\n");
1308 return 0;
1309 }
1310
1311 chip->reset_duration = 200;
1312
1313 if (np) {
1314 of_property_read_u32(np, "reset-duration",
1315 &chip->reset_duration);
1316 } else {
1317 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1318 }
1319
1320 /* A sane reset duration should not be longer than 1s */
1321 if (chip->reset_duration > 1000)
1322 chip->reset_duration = 1000;
1323
1324 return 0;
1325}
1326
1327int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1328{
1329 int ret;
1330
1331 mutex_init(&chip->indirect_mutex);
1332 mutex_init(&chip->alr_mutex);
1333
1334 ret = lan9303_probe_reset_gpio(chip, np);
1335 if (ret)
1336 return ret;
1337
1338 lan9303_handle_reset(chip);
1339
1340 ret = lan9303_check_device(chip);
1341 if (ret)
1342 return ret;
1343
1344 ret = lan9303_register_switch(chip);
1345 if (ret) {
1346 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1347 return ret;
1348 }
1349
1350 return 0;
1351}
1352EXPORT_SYMBOL(lan9303_probe);
1353
1354int lan9303_remove(struct lan9303 *chip)
1355{
1356 int rc;
1357
1358 rc = lan9303_disable_processing(chip);
1359 if (rc != 0)
1360 dev_warn(chip->dev, "shutting down failed\n");
1361
1362 dsa_unregister_switch(chip->ds);
1363
1364 /* assert reset to the whole device to prevent it from doing anything */
1365 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1366 gpiod_unexport(chip->reset_gpio);
1367
1368 return 0;
1369}
1370EXPORT_SYMBOL(lan9303_remove);
1371
1372MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1373MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1374MODULE_LICENSE("GPL v2");