Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DMA support use of SYS DMAC with SDHI SD/SDIO controller
4 *
5 * Copyright (C) 2016-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2017 Horms Solutions, Simon Horman
8 * Copyright (C) 2010-2011 Guennadi Liakhovetski
9 */
10
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/mfd/tmio.h>
15#include <linux/mmc/host.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/pagemap.h>
20#include <linux/scatterlist.h>
21#include <linux/sys_soc.h>
22
23#include "renesas_sdhi.h"
24#include "tmio_mmc.h"
25
26#define TMIO_MMC_MIN_DMA_LEN 8
27
28static const struct renesas_sdhi_of_data of_default_cfg = {
29 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
30};
31
32static const struct renesas_sdhi_of_data of_rz_compatible = {
33 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
34 TMIO_MMC_HAVE_CBSY,
35 .tmio_ocr_mask = MMC_VDD_32_33,
36 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
37 MMC_CAP_WAIT_WHILE_BUSY,
38};
39
40static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
41 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
42 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
43 MMC_CAP_WAIT_WHILE_BUSY,
44 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
45};
46
47/* Definitions for sampling clocks */
48static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
49 {
50 .clk_rate = 156000000,
51 .tap = 0x00000703,
52 },
53 {
54 .clk_rate = 0,
55 .tap = 0x00000300,
56 },
57};
58
59static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
60 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
61 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
62 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
63 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
64 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
65 .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
66 .dma_rx_offset = 0x2000,
67 .scc_offset = 0x0300,
68 .taps = rcar_gen2_scc_taps,
69 .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
70 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
71};
72
73static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
74 { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
75 { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
76 { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
77 { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
78 { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
79 { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
80 { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
81 { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
82 { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
83 { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
84 { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
85 { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
86 { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
87 { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
88 { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
89 { .compatible = "renesas,sdhi-shmobile" },
90 {},
91};
92MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
93
94static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
95 bool enable)
96{
97 struct renesas_sdhi *priv = host_to_priv(host);
98
99 if (!host->chan_tx || !host->chan_rx)
100 return;
101
102 if (priv->dma_priv.enable)
103 priv->dma_priv.enable(host, enable);
104}
105
106static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
107{
108 renesas_sdhi_sys_dmac_enable_dma(host, false);
109
110 if (host->chan_rx)
111 dmaengine_terminate_sync(host->chan_rx);
112 if (host->chan_tx)
113 dmaengine_terminate_sync(host->chan_tx);
114
115 renesas_sdhi_sys_dmac_enable_dma(host, true);
116}
117
118static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
119{
120 struct renesas_sdhi *priv = host_to_priv(host);
121
122 complete(&priv->dma_priv.dma_dataend);
123}
124
125static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
126{
127 struct tmio_mmc_host *host = arg;
128 struct renesas_sdhi *priv = host_to_priv(host);
129
130 spin_lock_irq(&host->lock);
131
132 if (!host->data)
133 goto out;
134
135 if (host->data->flags & MMC_DATA_READ)
136 dma_unmap_sg(host->chan_rx->device->dev,
137 host->sg_ptr, host->sg_len,
138 DMA_FROM_DEVICE);
139 else
140 dma_unmap_sg(host->chan_tx->device->dev,
141 host->sg_ptr, host->sg_len,
142 DMA_TO_DEVICE);
143
144 spin_unlock_irq(&host->lock);
145
146 wait_for_completion(&priv->dma_priv.dma_dataend);
147
148 spin_lock_irq(&host->lock);
149 tmio_mmc_do_data_irq(host);
150out:
151 spin_unlock_irq(&host->lock);
152}
153
154static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
155{
156 struct renesas_sdhi *priv = host_to_priv(host);
157 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
158 struct dma_async_tx_descriptor *desc = NULL;
159 struct dma_chan *chan = host->chan_rx;
160 dma_cookie_t cookie;
161 int ret, i;
162 bool aligned = true, multiple = true;
163 unsigned int align = 1; /* 2-byte alignment */
164
165 for_each_sg(sg, sg_tmp, host->sg_len, i) {
166 if (sg_tmp->offset & align)
167 aligned = false;
168 if (sg_tmp->length & align) {
169 multiple = false;
170 break;
171 }
172 }
173
174 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
175 (align & PAGE_MASK))) || !multiple) {
176 ret = -EINVAL;
177 goto pio;
178 }
179
180 if (sg->length < TMIO_MMC_MIN_DMA_LEN)
181 return;
182
183 /* The only sg element can be unaligned, use our bounce buffer then */
184 if (!aligned) {
185 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
186 host->sg_ptr = &host->bounce_sg;
187 sg = host->sg_ptr;
188 }
189
190 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
191 if (ret > 0)
192 desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
193 DMA_CTRL_ACK);
194
195 if (desc) {
196 reinit_completion(&priv->dma_priv.dma_dataend);
197 desc->callback = renesas_sdhi_sys_dmac_dma_callback;
198 desc->callback_param = host;
199
200 cookie = dmaengine_submit(desc);
201 if (cookie < 0) {
202 desc = NULL;
203 ret = cookie;
204 }
205 host->dma_on = true;
206 }
207pio:
208 if (!desc) {
209 /* DMA failed, fall back to PIO */
210 renesas_sdhi_sys_dmac_enable_dma(host, false);
211 if (ret >= 0)
212 ret = -EIO;
213 host->chan_rx = NULL;
214 dma_release_channel(chan);
215 /* Free the Tx channel too */
216 chan = host->chan_tx;
217 if (chan) {
218 host->chan_tx = NULL;
219 dma_release_channel(chan);
220 }
221 dev_warn(&host->pdev->dev,
222 "DMA failed: %d, falling back to PIO\n", ret);
223 }
224}
225
226static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
227{
228 struct renesas_sdhi *priv = host_to_priv(host);
229 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
230 struct dma_async_tx_descriptor *desc = NULL;
231 struct dma_chan *chan = host->chan_tx;
232 dma_cookie_t cookie;
233 int ret, i;
234 bool aligned = true, multiple = true;
235 unsigned int align = 1; /* 2-byte alignment */
236
237 for_each_sg(sg, sg_tmp, host->sg_len, i) {
238 if (sg_tmp->offset & align)
239 aligned = false;
240 if (sg_tmp->length & align) {
241 multiple = false;
242 break;
243 }
244 }
245
246 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
247 (align & PAGE_MASK))) || !multiple) {
248 ret = -EINVAL;
249 goto pio;
250 }
251
252 if (sg->length < TMIO_MMC_MIN_DMA_LEN)
253 return;
254
255 /* The only sg element can be unaligned, use our bounce buffer then */
256 if (!aligned) {
257 void *sg_vaddr = kmap_local_page(sg_page(sg));
258
259 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
260 memcpy(host->bounce_buf, sg_vaddr + sg->offset, host->bounce_sg.length);
261 kunmap_local(sg_vaddr);
262 host->sg_ptr = &host->bounce_sg;
263 sg = host->sg_ptr;
264 }
265
266 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
267 if (ret > 0)
268 desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
269 DMA_CTRL_ACK);
270
271 if (desc) {
272 reinit_completion(&priv->dma_priv.dma_dataend);
273 desc->callback = renesas_sdhi_sys_dmac_dma_callback;
274 desc->callback_param = host;
275
276 cookie = dmaengine_submit(desc);
277 if (cookie < 0) {
278 desc = NULL;
279 ret = cookie;
280 }
281 host->dma_on = true;
282 }
283pio:
284 if (!desc) {
285 /* DMA failed, fall back to PIO */
286 renesas_sdhi_sys_dmac_enable_dma(host, false);
287 if (ret >= 0)
288 ret = -EIO;
289 host->chan_tx = NULL;
290 dma_release_channel(chan);
291 /* Free the Rx channel too */
292 chan = host->chan_rx;
293 if (chan) {
294 host->chan_rx = NULL;
295 dma_release_channel(chan);
296 }
297 dev_warn(&host->pdev->dev,
298 "DMA failed: %d, falling back to PIO\n", ret);
299 }
300}
301
302static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
303 struct mmc_data *data)
304{
305 if (data->flags & MMC_DATA_READ) {
306 if (host->chan_rx)
307 renesas_sdhi_sys_dmac_start_dma_rx(host);
308 } else {
309 if (host->chan_tx)
310 renesas_sdhi_sys_dmac_start_dma_tx(host);
311 }
312}
313
314static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
315{
316 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
317 struct dma_chan *chan = NULL;
318
319 spin_lock_irq(&host->lock);
320
321 if (host->data) {
322 if (host->data->flags & MMC_DATA_READ)
323 chan = host->chan_rx;
324 else
325 chan = host->chan_tx;
326 }
327
328 spin_unlock_irq(&host->lock);
329
330 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
331
332 if (chan)
333 dma_async_issue_pending(chan);
334}
335
336static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
337 struct tmio_mmc_data *pdata)
338{
339 struct renesas_sdhi *priv = host_to_priv(host);
340
341 /* We can only either use DMA for both Tx and Rx or not use it at all */
342 if (!host->pdev->dev.of_node &&
343 (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
344 return;
345
346 if (!host->chan_tx && !host->chan_rx) {
347 struct resource *res = platform_get_resource(host->pdev,
348 IORESOURCE_MEM, 0);
349 struct dma_slave_config cfg = {};
350 dma_cap_mask_t mask;
351 int ret;
352
353 if (!res)
354 return;
355
356 dma_cap_zero(mask);
357 dma_cap_set(DMA_SLAVE, mask);
358
359 host->chan_tx = dma_request_slave_channel_compat(mask,
360 priv->dma_priv.filter, pdata->chan_priv_tx,
361 &host->pdev->dev, "tx");
362 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
363 host->chan_tx);
364
365 if (!host->chan_tx)
366 return;
367
368 cfg.direction = DMA_MEM_TO_DEV;
369 cfg.dst_addr = res->start +
370 (CTL_SD_DATA_PORT << host->bus_shift);
371 cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
372 if (!cfg.dst_addr_width)
373 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
374 cfg.src_addr = 0;
375 ret = dmaengine_slave_config(host->chan_tx, &cfg);
376 if (ret < 0)
377 goto ecfgtx;
378
379 host->chan_rx = dma_request_slave_channel_compat(mask,
380 priv->dma_priv.filter, pdata->chan_priv_rx,
381 &host->pdev->dev, "rx");
382 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
383 host->chan_rx);
384
385 if (!host->chan_rx)
386 goto ereqrx;
387
388 cfg.direction = DMA_DEV_TO_MEM;
389 cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
390 cfg.src_addr_width = priv->dma_priv.dma_buswidth;
391 if (!cfg.src_addr_width)
392 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
393 cfg.dst_addr = 0;
394 ret = dmaengine_slave_config(host->chan_rx, &cfg);
395 if (ret < 0)
396 goto ecfgrx;
397
398 host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
399 if (!host->bounce_buf)
400 goto ebouncebuf;
401
402 init_completion(&priv->dma_priv.dma_dataend);
403 tasklet_init(&host->dma_issue,
404 renesas_sdhi_sys_dmac_issue_tasklet_fn,
405 (unsigned long)host);
406 }
407
408 renesas_sdhi_sys_dmac_enable_dma(host, true);
409
410 return;
411
412ebouncebuf:
413ecfgrx:
414 dma_release_channel(host->chan_rx);
415 host->chan_rx = NULL;
416ereqrx:
417ecfgtx:
418 dma_release_channel(host->chan_tx);
419 host->chan_tx = NULL;
420}
421
422static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
423{
424 if (host->chan_tx) {
425 struct dma_chan *chan = host->chan_tx;
426
427 host->chan_tx = NULL;
428 dma_release_channel(chan);
429 }
430 if (host->chan_rx) {
431 struct dma_chan *chan = host->chan_rx;
432
433 host->chan_rx = NULL;
434 dma_release_channel(chan);
435 }
436 if (host->bounce_buf) {
437 free_pages((unsigned long)host->bounce_buf, 0);
438 host->bounce_buf = NULL;
439 }
440}
441
442static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
443 .start = renesas_sdhi_sys_dmac_start_dma,
444 .enable = renesas_sdhi_sys_dmac_enable_dma,
445 .request = renesas_sdhi_sys_dmac_request_dma,
446 .release = renesas_sdhi_sys_dmac_release_dma,
447 .abort = renesas_sdhi_sys_dmac_abort_dma,
448 .dataend = renesas_sdhi_sys_dmac_dataend_dma,
449};
450
451static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
452{
453 return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops,
454 of_device_get_match_data(&pdev->dev), NULL);
455}
456
457static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
458 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
459 pm_runtime_force_resume)
460 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
461 tmio_mmc_host_runtime_resume,
462 NULL)
463};
464
465static struct platform_driver renesas_sys_dmac_sdhi_driver = {
466 .driver = {
467 .name = "sh_mobile_sdhi",
468 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
469 .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
470 .of_match_table = renesas_sdhi_sys_dmac_of_match,
471 },
472 .probe = renesas_sdhi_sys_dmac_probe,
473 .remove = renesas_sdhi_remove,
474};
475
476module_platform_driver(renesas_sys_dmac_sdhi_driver);
477
478MODULE_DESCRIPTION("Renesas SDHI driver");
479MODULE_AUTHOR("Magnus Damm");
480MODULE_LICENSE("GPL v2");
481MODULE_ALIAS("platform:sh_mobile_sdhi");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DMA support use of SYS DMAC with SDHI SD/SDIO controller
4 *
5 * Copyright (C) 2016-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2017 Horms Solutions, Simon Horman
8 * Copyright (C) 2010-2011 Guennadi Liakhovetski
9 */
10
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/mfd/tmio.h>
15#include <linux/mmc/host.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/pagemap.h>
20#include <linux/scatterlist.h>
21#include <linux/sys_soc.h>
22
23#include "renesas_sdhi.h"
24#include "tmio_mmc.h"
25
26#define TMIO_MMC_MIN_DMA_LEN 8
27
28static const struct renesas_sdhi_of_data of_default_cfg = {
29 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
30};
31
32static const struct renesas_sdhi_of_data of_rz_compatible = {
33 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
34 TMIO_MMC_HAVE_CBSY,
35 .tmio_ocr_mask = MMC_VDD_32_33,
36 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
37};
38
39static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
40 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
41 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
42 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
43};
44
45/* Definitions for sampling clocks */
46static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
47 {
48 .clk_rate = 156000000,
49 .tap = 0x00000703,
50 },
51 {
52 .clk_rate = 0,
53 .tap = 0x00000300,
54 },
55};
56
57static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
58 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
59 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
60 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
61 MMC_CAP_CMD23,
62 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
63 .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
64 .dma_rx_offset = 0x2000,
65 .scc_offset = 0x0300,
66 .taps = rcar_gen2_scc_taps,
67 .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
68 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
69};
70
71static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
72 { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
73 { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
74 { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
75 { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
76 { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
77 { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
78 { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
79 { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
80 { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
81 { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
82 { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
83 { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
84 { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
85 { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
86 { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
87 { .compatible = "renesas,sdhi-shmobile" },
88 {},
89};
90MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
91
92static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
93 bool enable)
94{
95 struct renesas_sdhi *priv = host_to_priv(host);
96
97 if (!host->chan_tx || !host->chan_rx)
98 return;
99
100 if (priv->dma_priv.enable)
101 priv->dma_priv.enable(host, enable);
102}
103
104static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
105{
106 renesas_sdhi_sys_dmac_enable_dma(host, false);
107
108 if (host->chan_rx)
109 dmaengine_terminate_all(host->chan_rx);
110 if (host->chan_tx)
111 dmaengine_terminate_all(host->chan_tx);
112
113 renesas_sdhi_sys_dmac_enable_dma(host, true);
114}
115
116static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
117{
118 struct renesas_sdhi *priv = host_to_priv(host);
119
120 complete(&priv->dma_priv.dma_dataend);
121}
122
123static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
124{
125 struct tmio_mmc_host *host = arg;
126 struct renesas_sdhi *priv = host_to_priv(host);
127
128 spin_lock_irq(&host->lock);
129
130 if (!host->data)
131 goto out;
132
133 if (host->data->flags & MMC_DATA_READ)
134 dma_unmap_sg(host->chan_rx->device->dev,
135 host->sg_ptr, host->sg_len,
136 DMA_FROM_DEVICE);
137 else
138 dma_unmap_sg(host->chan_tx->device->dev,
139 host->sg_ptr, host->sg_len,
140 DMA_TO_DEVICE);
141
142 spin_unlock_irq(&host->lock);
143
144 wait_for_completion(&priv->dma_priv.dma_dataend);
145
146 spin_lock_irq(&host->lock);
147 tmio_mmc_do_data_irq(host);
148out:
149 spin_unlock_irq(&host->lock);
150}
151
152static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
153{
154 struct renesas_sdhi *priv = host_to_priv(host);
155 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
156 struct dma_async_tx_descriptor *desc = NULL;
157 struct dma_chan *chan = host->chan_rx;
158 dma_cookie_t cookie;
159 int ret, i;
160 bool aligned = true, multiple = true;
161 unsigned int align = (1 << host->pdata->alignment_shift) - 1;
162
163 for_each_sg(sg, sg_tmp, host->sg_len, i) {
164 if (sg_tmp->offset & align)
165 aligned = false;
166 if (sg_tmp->length & align) {
167 multiple = false;
168 break;
169 }
170 }
171
172 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
173 (align & PAGE_MASK))) || !multiple) {
174 ret = -EINVAL;
175 goto pio;
176 }
177
178 if (sg->length < TMIO_MMC_MIN_DMA_LEN)
179 return;
180
181 /* The only sg element can be unaligned, use our bounce buffer then */
182 if (!aligned) {
183 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
184 host->sg_ptr = &host->bounce_sg;
185 sg = host->sg_ptr;
186 }
187
188 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
189 if (ret > 0)
190 desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
191 DMA_CTRL_ACK);
192
193 if (desc) {
194 reinit_completion(&priv->dma_priv.dma_dataend);
195 desc->callback = renesas_sdhi_sys_dmac_dma_callback;
196 desc->callback_param = host;
197
198 cookie = dmaengine_submit(desc);
199 if (cookie < 0) {
200 desc = NULL;
201 ret = cookie;
202 }
203 host->dma_on = true;
204 }
205pio:
206 if (!desc) {
207 /* DMA failed, fall back to PIO */
208 renesas_sdhi_sys_dmac_enable_dma(host, false);
209 if (ret >= 0)
210 ret = -EIO;
211 host->chan_rx = NULL;
212 dma_release_channel(chan);
213 /* Free the Tx channel too */
214 chan = host->chan_tx;
215 if (chan) {
216 host->chan_tx = NULL;
217 dma_release_channel(chan);
218 }
219 dev_warn(&host->pdev->dev,
220 "DMA failed: %d, falling back to PIO\n", ret);
221 }
222}
223
224static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
225{
226 struct renesas_sdhi *priv = host_to_priv(host);
227 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
228 struct dma_async_tx_descriptor *desc = NULL;
229 struct dma_chan *chan = host->chan_tx;
230 dma_cookie_t cookie;
231 int ret, i;
232 bool aligned = true, multiple = true;
233 unsigned int align = (1 << host->pdata->alignment_shift) - 1;
234
235 for_each_sg(sg, sg_tmp, host->sg_len, i) {
236 if (sg_tmp->offset & align)
237 aligned = false;
238 if (sg_tmp->length & align) {
239 multiple = false;
240 break;
241 }
242 }
243
244 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
245 (align & PAGE_MASK))) || !multiple) {
246 ret = -EINVAL;
247 goto pio;
248 }
249
250 if (sg->length < TMIO_MMC_MIN_DMA_LEN)
251 return;
252
253 /* The only sg element can be unaligned, use our bounce buffer then */
254 if (!aligned) {
255 unsigned long flags;
256 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
257
258 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
259 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
260 tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
261 host->sg_ptr = &host->bounce_sg;
262 sg = host->sg_ptr;
263 }
264
265 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
266 if (ret > 0)
267 desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
268 DMA_CTRL_ACK);
269
270 if (desc) {
271 reinit_completion(&priv->dma_priv.dma_dataend);
272 desc->callback = renesas_sdhi_sys_dmac_dma_callback;
273 desc->callback_param = host;
274
275 cookie = dmaengine_submit(desc);
276 if (cookie < 0) {
277 desc = NULL;
278 ret = cookie;
279 }
280 host->dma_on = true;
281 }
282pio:
283 if (!desc) {
284 /* DMA failed, fall back to PIO */
285 renesas_sdhi_sys_dmac_enable_dma(host, false);
286 if (ret >= 0)
287 ret = -EIO;
288 host->chan_tx = NULL;
289 dma_release_channel(chan);
290 /* Free the Rx channel too */
291 chan = host->chan_rx;
292 if (chan) {
293 host->chan_rx = NULL;
294 dma_release_channel(chan);
295 }
296 dev_warn(&host->pdev->dev,
297 "DMA failed: %d, falling back to PIO\n", ret);
298 }
299}
300
301static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
302 struct mmc_data *data)
303{
304 if (data->flags & MMC_DATA_READ) {
305 if (host->chan_rx)
306 renesas_sdhi_sys_dmac_start_dma_rx(host);
307 } else {
308 if (host->chan_tx)
309 renesas_sdhi_sys_dmac_start_dma_tx(host);
310 }
311}
312
313static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
314{
315 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
316 struct dma_chan *chan = NULL;
317
318 spin_lock_irq(&host->lock);
319
320 if (host->data) {
321 if (host->data->flags & MMC_DATA_READ)
322 chan = host->chan_rx;
323 else
324 chan = host->chan_tx;
325 }
326
327 spin_unlock_irq(&host->lock);
328
329 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
330
331 if (chan)
332 dma_async_issue_pending(chan);
333}
334
335static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
336 struct tmio_mmc_data *pdata)
337{
338 struct renesas_sdhi *priv = host_to_priv(host);
339
340 /* We can only either use DMA for both Tx and Rx or not use it at all */
341 if (!host->pdev->dev.of_node &&
342 (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
343 return;
344
345 if (!host->chan_tx && !host->chan_rx) {
346 struct resource *res = platform_get_resource(host->pdev,
347 IORESOURCE_MEM, 0);
348 struct dma_slave_config cfg = {};
349 dma_cap_mask_t mask;
350 int ret;
351
352 if (!res)
353 return;
354
355 dma_cap_zero(mask);
356 dma_cap_set(DMA_SLAVE, mask);
357
358 host->chan_tx = dma_request_slave_channel_compat(mask,
359 priv->dma_priv.filter, pdata->chan_priv_tx,
360 &host->pdev->dev, "tx");
361 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
362 host->chan_tx);
363
364 if (!host->chan_tx)
365 return;
366
367 cfg.direction = DMA_MEM_TO_DEV;
368 cfg.dst_addr = res->start +
369 (CTL_SD_DATA_PORT << host->bus_shift);
370 cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
371 if (!cfg.dst_addr_width)
372 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
373 cfg.src_addr = 0;
374 ret = dmaengine_slave_config(host->chan_tx, &cfg);
375 if (ret < 0)
376 goto ecfgtx;
377
378 host->chan_rx = dma_request_slave_channel_compat(mask,
379 priv->dma_priv.filter, pdata->chan_priv_rx,
380 &host->pdev->dev, "rx");
381 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
382 host->chan_rx);
383
384 if (!host->chan_rx)
385 goto ereqrx;
386
387 cfg.direction = DMA_DEV_TO_MEM;
388 cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
389 cfg.src_addr_width = priv->dma_priv.dma_buswidth;
390 if (!cfg.src_addr_width)
391 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
392 cfg.dst_addr = 0;
393 ret = dmaengine_slave_config(host->chan_rx, &cfg);
394 if (ret < 0)
395 goto ecfgrx;
396
397 host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
398 if (!host->bounce_buf)
399 goto ebouncebuf;
400
401 init_completion(&priv->dma_priv.dma_dataend);
402 tasklet_init(&host->dma_issue,
403 renesas_sdhi_sys_dmac_issue_tasklet_fn,
404 (unsigned long)host);
405 }
406
407 renesas_sdhi_sys_dmac_enable_dma(host, true);
408
409 return;
410
411ebouncebuf:
412ecfgrx:
413 dma_release_channel(host->chan_rx);
414 host->chan_rx = NULL;
415ereqrx:
416ecfgtx:
417 dma_release_channel(host->chan_tx);
418 host->chan_tx = NULL;
419}
420
421static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
422{
423 if (host->chan_tx) {
424 struct dma_chan *chan = host->chan_tx;
425
426 host->chan_tx = NULL;
427 dma_release_channel(chan);
428 }
429 if (host->chan_rx) {
430 struct dma_chan *chan = host->chan_rx;
431
432 host->chan_rx = NULL;
433 dma_release_channel(chan);
434 }
435 if (host->bounce_buf) {
436 free_pages((unsigned long)host->bounce_buf, 0);
437 host->bounce_buf = NULL;
438 }
439}
440
441static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
442 .start = renesas_sdhi_sys_dmac_start_dma,
443 .enable = renesas_sdhi_sys_dmac_enable_dma,
444 .request = renesas_sdhi_sys_dmac_request_dma,
445 .release = renesas_sdhi_sys_dmac_release_dma,
446 .abort = renesas_sdhi_sys_dmac_abort_dma,
447 .dataend = renesas_sdhi_sys_dmac_dataend_dma,
448};
449
450static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
451{
452 return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
453}
454
455static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
456 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
457 pm_runtime_force_resume)
458 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
459 tmio_mmc_host_runtime_resume,
460 NULL)
461};
462
463static struct platform_driver renesas_sys_dmac_sdhi_driver = {
464 .driver = {
465 .name = "sh_mobile_sdhi",
466 .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
467 .of_match_table = renesas_sdhi_sys_dmac_of_match,
468 },
469 .probe = renesas_sdhi_sys_dmac_probe,
470 .remove = renesas_sdhi_remove,
471};
472
473module_platform_driver(renesas_sys_dmac_sdhi_driver);
474
475MODULE_DESCRIPTION("Renesas SDHI driver");
476MODULE_AUTHOR("Magnus Damm");
477MODULE_LICENSE("GPL v2");
478MODULE_ALIAS("platform:sh_mobile_sdhi");