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1/* SPDX-License-Identifier: GPL-2.0 */
2#define MMC_STRPCL 0x0000
3#define STOP_CLOCK (1 << 0)
4#define START_CLOCK (2 << 0)
5
6#define MMC_STAT 0x0004
7#define STAT_END_CMD_RES (1 << 13)
8#define STAT_PRG_DONE (1 << 12)
9#define STAT_DATA_TRAN_DONE (1 << 11)
10#define STAT_CLK_EN (1 << 8)
11#define STAT_RECV_FIFO_FULL (1 << 7)
12#define STAT_XMIT_FIFO_EMPTY (1 << 6)
13#define STAT_RES_CRC_ERR (1 << 5)
14#define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
15#define STAT_CRC_READ_ERROR (1 << 3)
16#define STAT_CRC_WRITE_ERROR (1 << 2)
17#define STAT_TIME_OUT_RESPONSE (1 << 1)
18#define STAT_READ_TIME_OUT (1 << 0)
19
20#define MMC_CLKRT 0x0008 /* 3 bit */
21
22#define MMC_SPI 0x000c
23#define SPI_CS_ADDRESS (1 << 3)
24#define SPI_CS_EN (1 << 2)
25#define CRC_ON (1 << 1)
26#define SPI_EN (1 << 0)
27
28#define MMC_CMDAT 0x0010
29#define CMDAT_SDIO_INT_EN (1 << 11)
30#define CMDAT_SD_4DAT (1 << 8)
31#define CMDAT_DMAEN (1 << 7)
32#define CMDAT_INIT (1 << 6)
33#define CMDAT_BUSY (1 << 5)
34#define CMDAT_STREAM (1 << 4) /* 1 = stream */
35#define CMDAT_WRITE (1 << 3) /* 1 = write */
36#define CMDAT_DATAEN (1 << 2)
37#define CMDAT_RESP_NONE (0 << 0)
38#define CMDAT_RESP_SHORT (1 << 0)
39#define CMDAT_RESP_R2 (2 << 0)
40#define CMDAT_RESP_R3 (3 << 0)
41
42#define MMC_RESTO 0x0014 /* 7 bit */
43
44#define MMC_RDTO 0x0018 /* 16 bit */
45
46#define MMC_BLKLEN 0x001c /* 10 bit */
47
48#define MMC_NOB 0x0020 /* 16 bit */
49
50#define MMC_PRTBUF 0x0024
51#define BUF_PART_FULL (1 << 0)
52
53#define MMC_I_MASK 0x0028
54
55/*PXA27x MMC interrupts*/
56#define SDIO_SUSPEND_ACK (1 << 12)
57#define SDIO_INT (1 << 11)
58#define RD_STALLED (1 << 10)
59#define RES_ERR (1 << 9)
60#define DAT_ERR (1 << 8)
61#define TINT (1 << 7)
62
63/*PXA2xx MMC interrupts*/
64#define TXFIFO_WR_REQ (1 << 6)
65#define RXFIFO_RD_REQ (1 << 5)
66#define CLK_IS_OFF (1 << 4)
67#define STOP_CMD (1 << 3)
68#define END_CMD_RES (1 << 2)
69#define PRG_DONE (1 << 1)
70#define DATA_TRAN_DONE (1 << 0)
71
72#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
73#define MMC_I_MASK_ALL 0x00001fff
74#else
75#define MMC_I_MASK_ALL 0x0000007f
76#endif
77
78#define MMC_I_REG 0x002c
79/* same as MMC_I_MASK */
80
81#define MMC_CMD 0x0030
82
83#define MMC_ARGH 0x0034 /* 16 bit */
84
85#define MMC_ARGL 0x0038 /* 16 bit */
86
87#define MMC_RES 0x003c /* 16 bit */
88
89#define MMC_RXFIFO 0x0040 /* 8 bit */
90
91#define MMC_TXFIFO 0x0044 /* 8 bit */
1/* SPDX-License-Identifier: GPL-2.0 */
2#define MMC_STRPCL 0x0000
3#define STOP_CLOCK (1 << 0)
4#define START_CLOCK (2 << 0)
5
6#define MMC_STAT 0x0004
7#define STAT_END_CMD_RES (1 << 13)
8#define STAT_PRG_DONE (1 << 12)
9#define STAT_DATA_TRAN_DONE (1 << 11)
10#define STAT_CLK_EN (1 << 8)
11#define STAT_RECV_FIFO_FULL (1 << 7)
12#define STAT_XMIT_FIFO_EMPTY (1 << 6)
13#define STAT_RES_CRC_ERR (1 << 5)
14#define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
15#define STAT_CRC_READ_ERROR (1 << 3)
16#define STAT_CRC_WRITE_ERROR (1 << 2)
17#define STAT_TIME_OUT_RESPONSE (1 << 1)
18#define STAT_READ_TIME_OUT (1 << 0)
19
20#define MMC_CLKRT 0x0008 /* 3 bit */
21
22#define MMC_SPI 0x000c
23#define SPI_CS_ADDRESS (1 << 3)
24#define SPI_CS_EN (1 << 2)
25#define CRC_ON (1 << 1)
26#define SPI_EN (1 << 0)
27
28#define MMC_CMDAT 0x0010
29#define CMDAT_SDIO_INT_EN (1 << 11)
30#define CMDAT_SD_4DAT (1 << 8)
31#define CMDAT_DMAEN (1 << 7)
32#define CMDAT_INIT (1 << 6)
33#define CMDAT_BUSY (1 << 5)
34#define CMDAT_STREAM (1 << 4) /* 1 = stream */
35#define CMDAT_WRITE (1 << 3) /* 1 = write */
36#define CMDAT_DATAEN (1 << 2)
37#define CMDAT_RESP_NONE (0 << 0)
38#define CMDAT_RESP_SHORT (1 << 0)
39#define CMDAT_RESP_R2 (2 << 0)
40#define CMDAT_RESP_R3 (3 << 0)
41
42#define MMC_RESTO 0x0014 /* 7 bit */
43
44#define MMC_RDTO 0x0018 /* 16 bit */
45
46#define MMC_BLKLEN 0x001c /* 10 bit */
47
48#define MMC_NOB 0x0020 /* 16 bit */
49
50#define MMC_PRTBUF 0x0024
51#define BUF_PART_FULL (1 << 0)
52
53#define MMC_I_MASK 0x0028
54
55/*PXA27x MMC interrupts*/
56#define SDIO_SUSPEND_ACK (1 << 12)
57#define SDIO_INT (1 << 11)
58#define RD_STALLED (1 << 10)
59#define RES_ERR (1 << 9)
60#define DAT_ERR (1 << 8)
61#define TINT (1 << 7)
62
63/*PXA2xx MMC interrupts*/
64#define TXFIFO_WR_REQ (1 << 6)
65#define RXFIFO_RD_REQ (1 << 5)
66#define CLK_IS_OFF (1 << 4)
67#define STOP_CMD (1 << 3)
68#define END_CMD_RES (1 << 2)
69#define PRG_DONE (1 << 1)
70#define DATA_TRAN_DONE (1 << 0)
71
72#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
73#define MMC_I_MASK_ALL 0x00001fff
74#else
75#define MMC_I_MASK_ALL 0x0000007f
76#endif
77
78#define MMC_I_REG 0x002c
79/* same as MMC_I_MASK */
80
81#define MMC_CMD 0x0030
82
83#define MMC_ARGH 0x0034 /* 16 bit */
84
85#define MMC_ARGL 0x0038 /* 16 bit */
86
87#define MMC_RES 0x003c /* 16 bit */
88
89#define MMC_RXFIFO 0x0040 /* 8 bit */
90
91#define MMC_TXFIFO 0x0044 /* 8 bit */