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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/errno.h>
12#include <linux/i3c/master.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/ioport.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/workqueue.h>
25#include <linux/of_device.h>
26
27#define DEV_ID 0x0
28#define DEV_ID_I3C_MASTER 0x5034
29
30#define CONF_STATUS0 0x4
31#define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
32#define CONF_STATUS0_ECC_CHK BIT(28)
33#define CONF_STATUS0_INTEG_CHK BIT(27)
34#define CONF_STATUS0_CSR_DAP_CHK BIT(26)
35#define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
36#define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
37#define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
38#define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
39#define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
40#define CONF_STATUS0_SUPPORTS_DDR BIT(5)
41#define CONF_STATUS0_SEC_MASTER BIT(4)
42#define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
43
44#define CONF_STATUS1 0x8
45#define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
46#define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
47#define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
48#define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
49#define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
50#define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
51#define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
52
53#define REV_ID 0xc
54#define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
55#define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
56#define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
57#define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
58
59#define CTRL 0x10
60#define CTRL_DEV_EN BIT(31)
61#define CTRL_HALT_EN BIT(30)
62#define CTRL_MCS BIT(29)
63#define CTRL_MCS_EN BIT(28)
64#define CTRL_THD_DELAY(x) (((x) << 24) & GENMASK(25, 24))
65#define CTRL_HJ_DISEC BIT(8)
66#define CTRL_MST_ACK BIT(7)
67#define CTRL_HJ_ACK BIT(6)
68#define CTRL_HJ_INIT BIT(5)
69#define CTRL_MST_INIT BIT(4)
70#define CTRL_AHDR_OPT BIT(3)
71#define CTRL_PURE_BUS_MODE 0
72#define CTRL_MIXED_FAST_BUS_MODE 2
73#define CTRL_MIXED_SLOW_BUS_MODE 3
74#define CTRL_BUS_MODE_MASK GENMASK(1, 0)
75#define THD_DELAY_MAX 3
76
77#define PRESCL_CTRL0 0x14
78#define PRESCL_CTRL0_I2C(x) ((x) << 16)
79#define PRESCL_CTRL0_I3C(x) (x)
80#define PRESCL_CTRL0_MAX GENMASK(9, 0)
81
82#define PRESCL_CTRL1 0x18
83#define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
84#define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
85#define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
86#define PRESCL_CTRL1_OD_LOW(x) (x)
87
88#define MST_IER 0x20
89#define MST_IDR 0x24
90#define MST_IMR 0x28
91#define MST_ICR 0x2c
92#define MST_ISR 0x30
93#define MST_INT_HALTED BIT(18)
94#define MST_INT_MR_DONE BIT(17)
95#define MST_INT_IMM_COMP BIT(16)
96#define MST_INT_TX_THR BIT(15)
97#define MST_INT_TX_OVF BIT(14)
98#define MST_INT_IBID_THR BIT(12)
99#define MST_INT_IBID_UNF BIT(11)
100#define MST_INT_IBIR_THR BIT(10)
101#define MST_INT_IBIR_UNF BIT(9)
102#define MST_INT_IBIR_OVF BIT(8)
103#define MST_INT_RX_THR BIT(7)
104#define MST_INT_RX_UNF BIT(6)
105#define MST_INT_CMDD_EMP BIT(5)
106#define MST_INT_CMDD_THR BIT(4)
107#define MST_INT_CMDD_OVF BIT(3)
108#define MST_INT_CMDR_THR BIT(2)
109#define MST_INT_CMDR_UNF BIT(1)
110#define MST_INT_CMDR_OVF BIT(0)
111
112#define MST_STATUS0 0x34
113#define MST_STATUS0_IDLE BIT(18)
114#define MST_STATUS0_HALTED BIT(17)
115#define MST_STATUS0_MASTER_MODE BIT(16)
116#define MST_STATUS0_TX_FULL BIT(13)
117#define MST_STATUS0_IBID_FULL BIT(12)
118#define MST_STATUS0_IBIR_FULL BIT(11)
119#define MST_STATUS0_RX_FULL BIT(10)
120#define MST_STATUS0_CMDD_FULL BIT(9)
121#define MST_STATUS0_CMDR_FULL BIT(8)
122#define MST_STATUS0_TX_EMP BIT(5)
123#define MST_STATUS0_IBID_EMP BIT(4)
124#define MST_STATUS0_IBIR_EMP BIT(3)
125#define MST_STATUS0_RX_EMP BIT(2)
126#define MST_STATUS0_CMDD_EMP BIT(1)
127#define MST_STATUS0_CMDR_EMP BIT(0)
128
129#define CMDR 0x38
130#define CMDR_NO_ERROR 0
131#define CMDR_DDR_PREAMBLE_ERROR 1
132#define CMDR_DDR_PARITY_ERROR 2
133#define CMDR_DDR_RX_FIFO_OVF 3
134#define CMDR_DDR_TX_FIFO_UNF 4
135#define CMDR_M0_ERROR 5
136#define CMDR_M1_ERROR 6
137#define CMDR_M2_ERROR 7
138#define CMDR_MST_ABORT 8
139#define CMDR_NACK_RESP 9
140#define CMDR_INVALID_DA 10
141#define CMDR_DDR_DROPPED 11
142#define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)
143#define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)
144#define CMDR_CMDID_HJACK_DISEC 0xfe
145#define CMDR_CMDID_HJACK_ENTDAA 0xff
146#define CMDR_CMDID(x) ((x) & GENMASK(7, 0))
147
148#define IBIR 0x3c
149#define IBIR_ACKED BIT(12)
150#define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)
151#define IBIR_ERROR BIT(7)
152#define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)
153#define IBIR_TYPE_IBI 0
154#define IBIR_TYPE_HJ 1
155#define IBIR_TYPE_MR 2
156#define IBIR_TYPE(x) ((x) & GENMASK(1, 0))
157
158#define SLV_IER 0x40
159#define SLV_IDR 0x44
160#define SLV_IMR 0x48
161#define SLV_ICR 0x4c
162#define SLV_ISR 0x50
163#define SLV_INT_TM BIT(20)
164#define SLV_INT_ERROR BIT(19)
165#define SLV_INT_EVENT_UP BIT(18)
166#define SLV_INT_HJ_DONE BIT(17)
167#define SLV_INT_MR_DONE BIT(16)
168#define SLV_INT_DA_UPD BIT(15)
169#define SLV_INT_SDR_FAIL BIT(14)
170#define SLV_INT_DDR_FAIL BIT(13)
171#define SLV_INT_M_RD_ABORT BIT(12)
172#define SLV_INT_DDR_RX_THR BIT(11)
173#define SLV_INT_DDR_TX_THR BIT(10)
174#define SLV_INT_SDR_RX_THR BIT(9)
175#define SLV_INT_SDR_TX_THR BIT(8)
176#define SLV_INT_DDR_RX_UNF BIT(7)
177#define SLV_INT_DDR_TX_OVF BIT(6)
178#define SLV_INT_SDR_RX_UNF BIT(5)
179#define SLV_INT_SDR_TX_OVF BIT(4)
180#define SLV_INT_DDR_RD_COMP BIT(3)
181#define SLV_INT_DDR_WR_COMP BIT(2)
182#define SLV_INT_SDR_RD_COMP BIT(1)
183#define SLV_INT_SDR_WR_COMP BIT(0)
184
185#define SLV_STATUS0 0x54
186#define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)
187#define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))
188
189#define SLV_STATUS1 0x58
190#define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)
191#define SLV_STATUS1_VEN_TM BIT(19)
192#define SLV_STATUS1_HJ_DIS BIT(18)
193#define SLV_STATUS1_MR_DIS BIT(17)
194#define SLV_STATUS1_PROT_ERR BIT(16)
195#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
196#define SLV_STATUS1_HAS_DA BIT(8)
197#define SLV_STATUS1_DDR_RX_FULL BIT(7)
198#define SLV_STATUS1_DDR_TX_FULL BIT(6)
199#define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
200#define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
201#define SLV_STATUS1_SDR_RX_FULL BIT(3)
202#define SLV_STATUS1_SDR_TX_FULL BIT(2)
203#define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
204#define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
205
206#define CMD0_FIFO 0x60
207#define CMD0_FIFO_IS_DDR BIT(31)
208#define CMD0_FIFO_IS_CCC BIT(30)
209#define CMD0_FIFO_BCH BIT(29)
210#define XMIT_BURST_STATIC_SUBADDR 0
211#define XMIT_SINGLE_INC_SUBADDR 1
212#define XMIT_SINGLE_STATIC_SUBADDR 2
213#define XMIT_BURST_WITHOUT_SUBADDR 3
214#define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
215#define CMD0_FIFO_SBCA BIT(26)
216#define CMD0_FIFO_RSBC BIT(25)
217#define CMD0_FIFO_IS_10B BIT(24)
218#define CMD0_FIFO_PL_LEN(l) ((l) << 12)
219#define CMD0_FIFO_PL_LEN_MAX 4095
220#define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
221#define CMD0_FIFO_RNW BIT(0)
222
223#define CMD1_FIFO 0x64
224#define CMD1_FIFO_CMDID(id) ((id) << 24)
225#define CMD1_FIFO_CSRADDR(a) (a)
226#define CMD1_FIFO_CCC(id) (id)
227
228#define TX_FIFO 0x68
229
230#define IMD_CMD0 0x70
231#define IMD_CMD0_PL_LEN(l) ((l) << 12)
232#define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
233#define IMD_CMD0_RNW BIT(0)
234
235#define IMD_CMD1 0x74
236#define IMD_CMD1_CCC(id) (id)
237
238#define IMD_DATA 0x78
239#define RX_FIFO 0x80
240#define IBI_DATA_FIFO 0x84
241#define SLV_DDR_TX_FIFO 0x88
242#define SLV_DDR_RX_FIFO 0x8c
243
244#define CMD_IBI_THR_CTRL 0x90
245#define IBIR_THR(t) ((t) << 24)
246#define CMDR_THR(t) ((t) << 16)
247#define IBI_THR(t) ((t) << 8)
248#define CMD_THR(t) (t)
249
250#define TX_RX_THR_CTRL 0x94
251#define RX_THR(t) ((t) << 16)
252#define TX_THR(t) (t)
253
254#define SLV_DDR_TX_RX_THR_CTRL 0x98
255#define SLV_DDR_RX_THR(t) ((t) << 16)
256#define SLV_DDR_TX_THR(t) (t)
257
258#define FLUSH_CTRL 0x9c
259#define FLUSH_IBI_RESP BIT(23)
260#define FLUSH_CMD_RESP BIT(22)
261#define FLUSH_SLV_DDR_RX_FIFO BIT(22)
262#define FLUSH_SLV_DDR_TX_FIFO BIT(21)
263#define FLUSH_IMM_FIFO BIT(20)
264#define FLUSH_IBI_FIFO BIT(19)
265#define FLUSH_RX_FIFO BIT(18)
266#define FLUSH_TX_FIFO BIT(17)
267#define FLUSH_CMD_FIFO BIT(16)
268
269#define TTO_PRESCL_CTRL0 0xb0
270#define TTO_PRESCL_CTRL0_DIVB(x) ((x) << 16)
271#define TTO_PRESCL_CTRL0_DIVA(x) (x)
272
273#define TTO_PRESCL_CTRL1 0xb4
274#define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
275#define TTO_PRESCL_CTRL1_DIVA(x) (x)
276
277#define DEVS_CTRL 0xb8
278#define DEVS_CTRL_DEV_CLR_SHIFT 16
279#define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
280#define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
281#define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
282#define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
283#define MAX_DEVS 16
284
285#define DEV_ID_RR0(d) (0xc0 + ((d) * 0x10))
286#define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
287#define DEV_ID_RR0_HDR_CAP BIT(10)
288#define DEV_ID_RR0_IS_I3C BIT(9)
289#define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
290#define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \
291 (((a) & GENMASK(9, 7)) << 6))
292#define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \
293 (((x) >> 6) & GENMASK(9, 7)))
294
295#define DEV_ID_RR1(d) (0xc4 + ((d) * 0x10))
296#define DEV_ID_RR1_PID_MSB(pid) (pid)
297
298#define DEV_ID_RR2(d) (0xc8 + ((d) * 0x10))
299#define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
300#define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
301#define DEV_ID_RR2_DCR(dcr) (dcr)
302#define DEV_ID_RR2_LVR(lvr) (lvr)
303
304#define SIR_MAP(x) (0x180 + ((x) * 4))
305#define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
306#define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
307#define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
308#define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
309#define DEV_ROLE_SLAVE 0
310#define DEV_ROLE_MASTER 1
311#define SIR_MAP_DEV_ROLE(role) ((role) << 14)
312#define SIR_MAP_DEV_SLOW BIT(13)
313#define SIR_MAP_DEV_PL(l) ((l) << 8)
314#define SIR_MAP_PL_MAX GENMASK(4, 0)
315#define SIR_MAP_DEV_DA(a) ((a) << 1)
316#define SIR_MAP_DEV_ACK BIT(0)
317
318#define GPIR_WORD(x) (0x200 + ((x) * 4))
319#define GPI_REG(val, id) \
320 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
321
322#define GPOR_WORD(x) (0x220 + ((x) * 4))
323#define GPO_REG(val, id) \
324 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
325
326#define ASF_INT_STATUS 0x300
327#define ASF_INT_RAW_STATUS 0x304
328#define ASF_INT_MASK 0x308
329#define ASF_INT_TEST 0x30c
330#define ASF_INT_FATAL_SELECT 0x310
331#define ASF_INTEGRITY_ERR BIT(6)
332#define ASF_PROTOCOL_ERR BIT(5)
333#define ASF_TRANS_TIMEOUT_ERR BIT(4)
334#define ASF_CSR_ERR BIT(3)
335#define ASF_DAP_ERR BIT(2)
336#define ASF_SRAM_UNCORR_ERR BIT(1)
337#define ASF_SRAM_CORR_ERR BIT(0)
338
339#define ASF_SRAM_CORR_FAULT_STATUS 0x320
340#define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
341#define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
342#define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))
343
344#define ASF_SRAM_FAULT_STATS 0x328
345#define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
346#define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))
347
348#define ASF_TRANS_TOUT_CTRL 0x330
349#define ASF_TRANS_TOUT_EN BIT(31)
350#define ASF_TRANS_TOUT_VAL(x) (x)
351
352#define ASF_TRANS_TOUT_FAULT_MASK 0x334
353#define ASF_TRANS_TOUT_FAULT_STATUS 0x338
354#define ASF_TRANS_TOUT_FAULT_APB BIT(3)
355#define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
356#define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
357#define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
358
359#define ASF_PROTO_FAULT_MASK 0x340
360#define ASF_PROTO_FAULT_STATUS 0x344
361#define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
362#define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
363#define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
364#define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
365#define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
366#define ASF_PROTO_FAULT_M(x) BIT(x)
367
368struct cdns_i3c_master_caps {
369 u32 cmdfifodepth;
370 u32 cmdrfifodepth;
371 u32 txfifodepth;
372 u32 rxfifodepth;
373 u32 ibirfifodepth;
374};
375
376struct cdns_i3c_cmd {
377 u32 cmd0;
378 u32 cmd1;
379 u32 tx_len;
380 const void *tx_buf;
381 u32 rx_len;
382 void *rx_buf;
383 u32 error;
384};
385
386struct cdns_i3c_xfer {
387 struct list_head node;
388 struct completion comp;
389 int ret;
390 unsigned int ncmds;
391 struct cdns_i3c_cmd cmds[];
392};
393
394struct cdns_i3c_data {
395 u8 thd_delay_ns;
396};
397
398struct cdns_i3c_master {
399 struct work_struct hj_work;
400 struct i3c_master_controller base;
401 u32 free_rr_slots;
402 unsigned int maxdevs;
403 struct {
404 unsigned int num_slots;
405 struct i3c_dev_desc **slots;
406 spinlock_t lock;
407 } ibi;
408 struct {
409 struct list_head list;
410 struct cdns_i3c_xfer *cur;
411 spinlock_t lock;
412 } xferqueue;
413 void __iomem *regs;
414 struct clk *sysclk;
415 struct clk *pclk;
416 struct cdns_i3c_master_caps caps;
417 unsigned long i3c_scl_lim;
418 const struct cdns_i3c_data *devdata;
419};
420
421static inline struct cdns_i3c_master *
422to_cdns_i3c_master(struct i3c_master_controller *master)
423{
424 return container_of(master, struct cdns_i3c_master, base);
425}
426
427static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
428 const u8 *bytes, int nbytes)
429{
430 writesl(master->regs + TX_FIFO, bytes, nbytes / 4);
431 if (nbytes & 3) {
432 u32 tmp = 0;
433
434 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
435 writesl(master->regs + TX_FIFO, &tmp, 1);
436 }
437}
438
439static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
440 u8 *bytes, int nbytes)
441{
442 readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
443 if (nbytes & 3) {
444 u32 tmp;
445
446 readsl(master->regs + RX_FIFO, &tmp, 1);
447 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
448 }
449}
450
451static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
452 const struct i3c_ccc_cmd *cmd)
453{
454 if (cmd->ndests > 1)
455 return false;
456
457 switch (cmd->id) {
458 case I3C_CCC_ENEC(true):
459 case I3C_CCC_ENEC(false):
460 case I3C_CCC_DISEC(true):
461 case I3C_CCC_DISEC(false):
462 case I3C_CCC_ENTAS(0, true):
463 case I3C_CCC_ENTAS(0, false):
464 case I3C_CCC_RSTDAA(true):
465 case I3C_CCC_RSTDAA(false):
466 case I3C_CCC_ENTDAA:
467 case I3C_CCC_SETMWL(true):
468 case I3C_CCC_SETMWL(false):
469 case I3C_CCC_SETMRL(true):
470 case I3C_CCC_SETMRL(false):
471 case I3C_CCC_DEFSLVS:
472 case I3C_CCC_ENTHDR(0):
473 case I3C_CCC_SETDASA:
474 case I3C_CCC_SETNEWDA:
475 case I3C_CCC_GETMWL:
476 case I3C_CCC_GETMRL:
477 case I3C_CCC_GETPID:
478 case I3C_CCC_GETBCR:
479 case I3C_CCC_GETDCR:
480 case I3C_CCC_GETSTATUS:
481 case I3C_CCC_GETACCMST:
482 case I3C_CCC_GETMXDS:
483 case I3C_CCC_GETHDRCAP:
484 return true;
485 default:
486 break;
487 }
488
489 return false;
490}
491
492static int cdns_i3c_master_disable(struct cdns_i3c_master *master)
493{
494 u32 status;
495
496 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
497
498 return readl_poll_timeout(master->regs + MST_STATUS0, status,
499 status & MST_STATUS0_IDLE, 10, 1000000);
500}
501
502static void cdns_i3c_master_enable(struct cdns_i3c_master *master)
503{
504 writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
505}
506
507static struct cdns_i3c_xfer *
508cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds)
509{
510 struct cdns_i3c_xfer *xfer;
511
512 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
513 if (!xfer)
514 return NULL;
515
516 INIT_LIST_HEAD(&xfer->node);
517 xfer->ncmds = ncmds;
518 xfer->ret = -ETIMEDOUT;
519
520 return xfer;
521}
522
523static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer)
524{
525 kfree(xfer);
526}
527
528static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master)
529{
530 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
531 unsigned int i;
532
533 if (!xfer)
534 return;
535
536 writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
537 for (i = 0; i < xfer->ncmds; i++) {
538 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
539
540 cdns_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf,
541 cmd->tx_len);
542 }
543
544 for (i = 0; i < xfer->ncmds; i++) {
545 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
546
547 writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
548 master->regs + CMD1_FIFO);
549 writel(cmd->cmd0, master->regs + CMD0_FIFO);
550 }
551
552 writel(readl(master->regs + CTRL) | CTRL_MCS,
553 master->regs + CTRL);
554 writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
555}
556
557static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master,
558 u32 isr)
559{
560 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
561 int i, ret = 0;
562 u32 status0;
563
564 if (!xfer)
565 return;
566
567 if (!(isr & MST_INT_CMDD_EMP))
568 return;
569
570 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
571
572 for (status0 = readl(master->regs + MST_STATUS0);
573 !(status0 & MST_STATUS0_CMDR_EMP);
574 status0 = readl(master->regs + MST_STATUS0)) {
575 struct cdns_i3c_cmd *cmd;
576 u32 cmdr, rx_len, id;
577
578 cmdr = readl(master->regs + CMDR);
579 id = CMDR_CMDID(cmdr);
580 if (id == CMDR_CMDID_HJACK_DISEC ||
581 id == CMDR_CMDID_HJACK_ENTDAA ||
582 WARN_ON(id >= xfer->ncmds))
583 continue;
584
585 cmd = &xfer->cmds[CMDR_CMDID(cmdr)];
586 rx_len = min_t(u32, CMDR_XFER_BYTES(cmdr), cmd->rx_len);
587 cdns_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
588 cmd->error = CMDR_ERROR(cmdr);
589 }
590
591 for (i = 0; i < xfer->ncmds; i++) {
592 switch (xfer->cmds[i].error) {
593 case CMDR_NO_ERROR:
594 break;
595
596 case CMDR_DDR_PREAMBLE_ERROR:
597 case CMDR_DDR_PARITY_ERROR:
598 case CMDR_M0_ERROR:
599 case CMDR_M1_ERROR:
600 case CMDR_M2_ERROR:
601 case CMDR_MST_ABORT:
602 case CMDR_NACK_RESP:
603 case CMDR_DDR_DROPPED:
604 ret = -EIO;
605 break;
606
607 case CMDR_DDR_RX_FIFO_OVF:
608 case CMDR_DDR_TX_FIFO_UNF:
609 ret = -ENOSPC;
610 break;
611
612 case CMDR_INVALID_DA:
613 default:
614 ret = -EINVAL;
615 break;
616 }
617 }
618
619 xfer->ret = ret;
620 complete(&xfer->comp);
621
622 xfer = list_first_entry_or_null(&master->xferqueue.list,
623 struct cdns_i3c_xfer, node);
624 if (xfer)
625 list_del_init(&xfer->node);
626
627 master->xferqueue.cur = xfer;
628 cdns_i3c_master_start_xfer_locked(master);
629}
630
631static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master,
632 struct cdns_i3c_xfer *xfer)
633{
634 unsigned long flags;
635
636 init_completion(&xfer->comp);
637 spin_lock_irqsave(&master->xferqueue.lock, flags);
638 if (master->xferqueue.cur) {
639 list_add_tail(&xfer->node, &master->xferqueue.list);
640 } else {
641 master->xferqueue.cur = xfer;
642 cdns_i3c_master_start_xfer_locked(master);
643 }
644 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
645}
646
647static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master,
648 struct cdns_i3c_xfer *xfer)
649{
650 unsigned long flags;
651
652 spin_lock_irqsave(&master->xferqueue.lock, flags);
653 if (master->xferqueue.cur == xfer) {
654 u32 status;
655
656 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
657 master->regs + CTRL);
658 readl_poll_timeout_atomic(master->regs + MST_STATUS0, status,
659 status & MST_STATUS0_IDLE, 10,
660 1000000);
661 master->xferqueue.cur = NULL;
662 writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
663 FLUSH_CMD_RESP,
664 master->regs + FLUSH_CTRL);
665 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
666 writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
667 master->regs + CTRL);
668 } else {
669 list_del_init(&xfer->node);
670 }
671 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
672}
673
674static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd)
675{
676 switch (cmd->error) {
677 case CMDR_M0_ERROR:
678 return I3C_ERROR_M0;
679
680 case CMDR_M1_ERROR:
681 return I3C_ERROR_M1;
682
683 case CMDR_M2_ERROR:
684 case CMDR_NACK_RESP:
685 return I3C_ERROR_M2;
686
687 default:
688 break;
689 }
690
691 return I3C_ERROR_UNKNOWN;
692}
693
694static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
695 struct i3c_ccc_cmd *cmd)
696{
697 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
698 struct cdns_i3c_xfer *xfer;
699 struct cdns_i3c_cmd *ccmd;
700 int ret;
701
702 xfer = cdns_i3c_master_alloc_xfer(master, 1);
703 if (!xfer)
704 return -ENOMEM;
705
706 ccmd = xfer->cmds;
707 ccmd->cmd1 = CMD1_FIFO_CCC(cmd->id);
708 ccmd->cmd0 = CMD0_FIFO_IS_CCC |
709 CMD0_FIFO_PL_LEN(cmd->dests[0].payload.len);
710
711 if (cmd->id & I3C_CCC_DIRECT)
712 ccmd->cmd0 |= CMD0_FIFO_DEV_ADDR(cmd->dests[0].addr);
713
714 if (cmd->rnw) {
715 ccmd->cmd0 |= CMD0_FIFO_RNW;
716 ccmd->rx_buf = cmd->dests[0].payload.data;
717 ccmd->rx_len = cmd->dests[0].payload.len;
718 } else {
719 ccmd->tx_buf = cmd->dests[0].payload.data;
720 ccmd->tx_len = cmd->dests[0].payload.len;
721 }
722
723 cdns_i3c_master_queue_xfer(master, xfer);
724 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
725 cdns_i3c_master_unqueue_xfer(master, xfer);
726
727 ret = xfer->ret;
728 cmd->err = cdns_i3c_cmd_get_err(&xfer->cmds[0]);
729 cdns_i3c_master_free_xfer(xfer);
730
731 return ret;
732}
733
734static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
735 struct i3c_priv_xfer *xfers,
736 int nxfers)
737{
738 struct i3c_master_controller *m = i3c_dev_get_master(dev);
739 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
740 int txslots = 0, rxslots = 0, i, ret;
741 struct cdns_i3c_xfer *cdns_xfer;
742
743 for (i = 0; i < nxfers; i++) {
744 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
745 return -ENOTSUPP;
746 }
747
748 if (!nxfers)
749 return 0;
750
751 if (nxfers > master->caps.cmdfifodepth ||
752 nxfers > master->caps.cmdrfifodepth)
753 return -ENOTSUPP;
754
755 /*
756 * First make sure that all transactions (block of transfers separated
757 * by a STOP marker) fit in the FIFOs.
758 */
759 for (i = 0; i < nxfers; i++) {
760 if (xfers[i].rnw)
761 rxslots += DIV_ROUND_UP(xfers[i].len, 4);
762 else
763 txslots += DIV_ROUND_UP(xfers[i].len, 4);
764 }
765
766 if (rxslots > master->caps.rxfifodepth ||
767 txslots > master->caps.txfifodepth)
768 return -ENOTSUPP;
769
770 cdns_xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
771 if (!cdns_xfer)
772 return -ENOMEM;
773
774 for (i = 0; i < nxfers; i++) {
775 struct cdns_i3c_cmd *ccmd = &cdns_xfer->cmds[i];
776 u32 pl_len = xfers[i].len;
777
778 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(dev->info.dyn_addr) |
779 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
780
781 if (xfers[i].rnw) {
782 ccmd->cmd0 |= CMD0_FIFO_RNW;
783 ccmd->rx_buf = xfers[i].data.in;
784 ccmd->rx_len = xfers[i].len;
785 pl_len++;
786 } else {
787 ccmd->tx_buf = xfers[i].data.out;
788 ccmd->tx_len = xfers[i].len;
789 }
790
791 ccmd->cmd0 |= CMD0_FIFO_PL_LEN(pl_len);
792
793 if (i < nxfers - 1)
794 ccmd->cmd0 |= CMD0_FIFO_RSBC;
795
796 if (!i)
797 ccmd->cmd0 |= CMD0_FIFO_BCH;
798 }
799
800 cdns_i3c_master_queue_xfer(master, cdns_xfer);
801 if (!wait_for_completion_timeout(&cdns_xfer->comp,
802 msecs_to_jiffies(1000)))
803 cdns_i3c_master_unqueue_xfer(master, cdns_xfer);
804
805 ret = cdns_xfer->ret;
806
807 for (i = 0; i < nxfers; i++)
808 xfers[i].err = cdns_i3c_cmd_get_err(&cdns_xfer->cmds[i]);
809
810 cdns_i3c_master_free_xfer(cdns_xfer);
811
812 return ret;
813}
814
815static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
816 const struct i2c_msg *xfers, int nxfers)
817{
818 struct i3c_master_controller *m = i2c_dev_get_master(dev);
819 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
820 unsigned int nrxwords = 0, ntxwords = 0;
821 struct cdns_i3c_xfer *xfer;
822 int i, ret = 0;
823
824 if (nxfers > master->caps.cmdfifodepth)
825 return -ENOTSUPP;
826
827 for (i = 0; i < nxfers; i++) {
828 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
829 return -ENOTSUPP;
830
831 if (xfers[i].flags & I2C_M_RD)
832 nrxwords += DIV_ROUND_UP(xfers[i].len, 4);
833 else
834 ntxwords += DIV_ROUND_UP(xfers[i].len, 4);
835 }
836
837 if (ntxwords > master->caps.txfifodepth ||
838 nrxwords > master->caps.rxfifodepth)
839 return -ENOTSUPP;
840
841 xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
842 if (!xfer)
843 return -ENOMEM;
844
845 for (i = 0; i < nxfers; i++) {
846 struct cdns_i3c_cmd *ccmd = &xfer->cmds[i];
847
848 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(xfers[i].addr) |
849 CMD0_FIFO_PL_LEN(xfers[i].len) |
850 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
851
852 if (xfers[i].flags & I2C_M_TEN)
853 ccmd->cmd0 |= CMD0_FIFO_IS_10B;
854
855 if (xfers[i].flags & I2C_M_RD) {
856 ccmd->cmd0 |= CMD0_FIFO_RNW;
857 ccmd->rx_buf = xfers[i].buf;
858 ccmd->rx_len = xfers[i].len;
859 } else {
860 ccmd->tx_buf = xfers[i].buf;
861 ccmd->tx_len = xfers[i].len;
862 }
863 }
864
865 cdns_i3c_master_queue_xfer(master, xfer);
866 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
867 cdns_i3c_master_unqueue_xfer(master, xfer);
868
869 ret = xfer->ret;
870 cdns_i3c_master_free_xfer(xfer);
871
872 return ret;
873}
874
875struct cdns_i3c_i2c_dev_data {
876 u16 id;
877 s16 ibi;
878 struct i3c_generic_ibi_pool *ibi_pool;
879};
880
881static u32 prepare_rr0_dev_address(u32 addr)
882{
883 u32 ret = (addr << 1) & 0xff;
884
885 /* RR0[7:1] = addr[6:0] */
886 ret |= (addr & GENMASK(6, 0)) << 1;
887
888 /* RR0[15:13] = addr[9:7] */
889 ret |= (addr & GENMASK(9, 7)) << 6;
890
891 /* RR0[0] = ~XOR(addr[6:0]) */
892 if (!(hweight8(addr & 0x7f) & 1))
893 ret |= 1;
894
895 return ret;
896}
897
898static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev)
899{
900 struct i3c_master_controller *m = i3c_dev_get_master(dev);
901 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
902 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
903 u32 rr;
904
905 rr = prepare_rr0_dev_address(dev->info.dyn_addr ?
906 dev->info.dyn_addr :
907 dev->info.static_addr);
908 writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
909}
910
911static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master,
912 u8 dyn_addr)
913{
914 unsigned long activedevs;
915 u32 rr;
916 int i;
917
918 if (!dyn_addr) {
919 if (!master->free_rr_slots)
920 return -ENOSPC;
921
922 return ffs(master->free_rr_slots) - 1;
923 }
924
925 activedevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
926 activedevs &= ~BIT(0);
927
928 for_each_set_bit(i, &activedevs, master->maxdevs + 1) {
929 rr = readl(master->regs + DEV_ID_RR0(i));
930 if (!(rr & DEV_ID_RR0_IS_I3C) ||
931 DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr)
932 continue;
933
934 return i;
935 }
936
937 return -EINVAL;
938}
939
940static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
941 u8 old_dyn_addr)
942{
943 cdns_i3c_master_upd_i3c_addr(dev);
944
945 return 0;
946}
947
948static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
949{
950 struct i3c_master_controller *m = i3c_dev_get_master(dev);
951 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
952 struct cdns_i3c_i2c_dev_data *data;
953 int slot;
954
955 data = kzalloc(sizeof(*data), GFP_KERNEL);
956 if (!data)
957 return -ENOMEM;
958
959 slot = cdns_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
960 if (slot < 0) {
961 kfree(data);
962 return slot;
963 }
964
965 data->ibi = -1;
966 data->id = slot;
967 i3c_dev_set_master_data(dev, data);
968 master->free_rr_slots &= ~BIT(slot);
969
970 if (!dev->info.dyn_addr) {
971 cdns_i3c_master_upd_i3c_addr(dev);
972 writel(readl(master->regs + DEVS_CTRL) |
973 DEVS_CTRL_DEV_ACTIVE(data->id),
974 master->regs + DEVS_CTRL);
975 }
976
977 return 0;
978}
979
980static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
981{
982 struct i3c_master_controller *m = i3c_dev_get_master(dev);
983 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
984 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
985
986 writel(readl(master->regs + DEVS_CTRL) |
987 DEVS_CTRL_DEV_CLR(data->id),
988 master->regs + DEVS_CTRL);
989
990 i3c_dev_set_master_data(dev, NULL);
991 master->free_rr_slots |= BIT(data->id);
992 kfree(data);
993}
994
995static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
996{
997 struct i3c_master_controller *m = i2c_dev_get_master(dev);
998 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
999 struct cdns_i3c_i2c_dev_data *data;
1000 int slot;
1001
1002 slot = cdns_i3c_master_get_rr_slot(master, 0);
1003 if (slot < 0)
1004 return slot;
1005
1006 data = kzalloc(sizeof(*data), GFP_KERNEL);
1007 if (!data)
1008 return -ENOMEM;
1009
1010 data->id = slot;
1011 master->free_rr_slots &= ~BIT(slot);
1012 i2c_dev_set_master_data(dev, data);
1013
1014 writel(prepare_rr0_dev_address(dev->addr),
1015 master->regs + DEV_ID_RR0(data->id));
1016 writel(dev->lvr, master->regs + DEV_ID_RR2(data->id));
1017 writel(readl(master->regs + DEVS_CTRL) |
1018 DEVS_CTRL_DEV_ACTIVE(data->id),
1019 master->regs + DEVS_CTRL);
1020
1021 return 0;
1022}
1023
1024static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1025{
1026 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1027 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1028 struct cdns_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1029
1030 writel(readl(master->regs + DEVS_CTRL) |
1031 DEVS_CTRL_DEV_CLR(data->id),
1032 master->regs + DEVS_CTRL);
1033 master->free_rr_slots |= BIT(data->id);
1034
1035 i2c_dev_set_master_data(dev, NULL);
1036 kfree(data);
1037}
1038
1039static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m)
1040{
1041 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1042
1043 cdns_i3c_master_disable(master);
1044}
1045
1046static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master,
1047 unsigned int slot,
1048 struct i3c_device_info *info)
1049{
1050 u32 rr;
1051
1052 memset(info, 0, sizeof(*info));
1053 rr = readl(master->regs + DEV_ID_RR0(slot));
1054 info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
1055 rr = readl(master->regs + DEV_ID_RR2(slot));
1056 info->dcr = rr;
1057 info->bcr = rr >> 8;
1058 info->pid = rr >> 16;
1059 info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16;
1060}
1061
1062static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master)
1063{
1064 struct i3c_master_controller *m = &master->base;
1065 unsigned long i3c_lim_period, pres_step, ncycles;
1066 struct i3c_bus *bus = i3c_master_get_bus(m);
1067 unsigned long new_i3c_scl_lim = 0;
1068 struct i3c_dev_desc *dev;
1069 u32 prescl1, ctrl;
1070
1071 i3c_bus_for_each_i3cdev(bus, dev) {
1072 unsigned long max_fscl;
1073
1074 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
1075 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
1076 switch (max_fscl) {
1077 case I3C_SDR1_FSCL_8MHZ:
1078 max_fscl = 8000000;
1079 break;
1080 case I3C_SDR2_FSCL_6MHZ:
1081 max_fscl = 6000000;
1082 break;
1083 case I3C_SDR3_FSCL_4MHZ:
1084 max_fscl = 4000000;
1085 break;
1086 case I3C_SDR4_FSCL_2MHZ:
1087 max_fscl = 2000000;
1088 break;
1089 case I3C_SDR0_FSCL_MAX:
1090 default:
1091 max_fscl = 0;
1092 break;
1093 }
1094
1095 if (max_fscl &&
1096 (new_i3c_scl_lim > max_fscl || !new_i3c_scl_lim))
1097 new_i3c_scl_lim = max_fscl;
1098 }
1099
1100 /* Only update PRESCL_CTRL1 if the I3C SCL limitation has changed. */
1101 if (new_i3c_scl_lim == master->i3c_scl_lim)
1102 return;
1103 master->i3c_scl_lim = new_i3c_scl_lim;
1104 if (!new_i3c_scl_lim)
1105 return;
1106 pres_step = 1000000000UL / (bus->scl_rate.i3c * 4);
1107
1108 /* Configure PP_LOW to meet I3C slave limitations. */
1109 prescl1 = readl(master->regs + PRESCL_CTRL1) &
1110 ~PRESCL_CTRL1_PP_LOW_MASK;
1111 ctrl = readl(master->regs + CTRL);
1112
1113 i3c_lim_period = DIV_ROUND_UP(1000000000, master->i3c_scl_lim);
1114 ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step);
1115 if (ncycles < 4)
1116 ncycles = 0;
1117 else
1118 ncycles -= 4;
1119
1120 prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
1121
1122 /* Disable I3C master before updating PRESCL_CTRL1. */
1123 if (ctrl & CTRL_DEV_EN)
1124 cdns_i3c_master_disable(master);
1125
1126 writel(prescl1, master->regs + PRESCL_CTRL1);
1127
1128 if (ctrl & CTRL_DEV_EN)
1129 cdns_i3c_master_enable(master);
1130}
1131
1132static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
1133{
1134 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1135 unsigned long olddevs, newdevs;
1136 int ret, slot;
1137 u8 addrs[MAX_DEVS] = { };
1138 u8 last_addr = 0;
1139
1140 olddevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1141 olddevs |= BIT(0);
1142
1143 /* Prepare RR slots before launching DAA. */
1144 for_each_clear_bit(slot, &olddevs, master->maxdevs + 1) {
1145 ret = i3c_master_get_free_addr(m, last_addr + 1);
1146 if (ret < 0)
1147 return -ENOSPC;
1148
1149 last_addr = ret;
1150 addrs[slot] = last_addr;
1151 writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
1152 master->regs + DEV_ID_RR0(slot));
1153 writel(0, master->regs + DEV_ID_RR1(slot));
1154 writel(0, master->regs + DEV_ID_RR2(slot));
1155 }
1156
1157 ret = i3c_master_entdaa_locked(&master->base);
1158 if (ret && ret != I3C_ERROR_M2)
1159 return ret;
1160
1161 newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1162 newdevs &= ~olddevs;
1163
1164 /*
1165 * Clear all retaining registers filled during DAA. We already
1166 * have the addressed assigned to them in the addrs array.
1167 */
1168 for_each_set_bit(slot, &newdevs, master->maxdevs + 1)
1169 i3c_master_add_i3c_dev_locked(m, addrs[slot]);
1170
1171 /*
1172 * Clear slots that ended up not being used. Can be caused by I3C
1173 * device creation failure or when the I3C device was already known
1174 * by the system but with a different address (in this case the device
1175 * already has a slot and does not need a new one).
1176 */
1177 writel(readl(master->regs + DEVS_CTRL) |
1178 master->free_rr_slots << DEVS_CTRL_DEV_CLR_SHIFT,
1179 master->regs + DEVS_CTRL);
1180
1181 i3c_master_defslvs_locked(&master->base);
1182
1183 cdns_i3c_master_upd_i3c_scl_lim(master);
1184
1185 /* Unmask Hot-Join and Mastership request interrupts. */
1186 i3c_master_enec_locked(m, I3C_BROADCAST_ADDR,
1187 I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR);
1188
1189 return 0;
1190}
1191
1192static u8 cdns_i3c_master_calculate_thd_delay(struct cdns_i3c_master *master)
1193{
1194 unsigned long sysclk_rate = clk_get_rate(master->sysclk);
1195 u8 thd_delay = DIV_ROUND_UP(master->devdata->thd_delay_ns,
1196 (NSEC_PER_SEC / sysclk_rate));
1197
1198 /* Every value greater than 3 is not valid. */
1199 if (thd_delay > THD_DELAY_MAX)
1200 thd_delay = THD_DELAY_MAX;
1201
1202 /* CTLR_THD_DEL value is encoded. */
1203 return (THD_DELAY_MAX - thd_delay);
1204}
1205
1206static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
1207{
1208 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1209 unsigned long pres_step, sysclk_rate, max_i2cfreq;
1210 struct i3c_bus *bus = i3c_master_get_bus(m);
1211 u32 ctrl, prescl0, prescl1, pres, low;
1212 struct i3c_device_info info = { };
1213 int ret, ncycles;
1214
1215 switch (bus->mode) {
1216 case I3C_BUS_MODE_PURE:
1217 ctrl = CTRL_PURE_BUS_MODE;
1218 break;
1219
1220 case I3C_BUS_MODE_MIXED_FAST:
1221 ctrl = CTRL_MIXED_FAST_BUS_MODE;
1222 break;
1223
1224 case I3C_BUS_MODE_MIXED_SLOW:
1225 ctrl = CTRL_MIXED_SLOW_BUS_MODE;
1226 break;
1227
1228 default:
1229 return -EINVAL;
1230 }
1231
1232 sysclk_rate = clk_get_rate(master->sysclk);
1233 if (!sysclk_rate)
1234 return -EINVAL;
1235
1236 pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
1237 if (pres > PRESCL_CTRL0_MAX)
1238 return -ERANGE;
1239
1240 bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
1241
1242 prescl0 = PRESCL_CTRL0_I3C(pres);
1243
1244 low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
1245 prescl1 = PRESCL_CTRL1_OD_LOW(low);
1246
1247 max_i2cfreq = bus->scl_rate.i2c;
1248
1249 pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
1250 if (pres > PRESCL_CTRL0_MAX)
1251 return -ERANGE;
1252
1253 bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
1254
1255 prescl0 |= PRESCL_CTRL0_I2C(pres);
1256 writel(prescl0, master->regs + PRESCL_CTRL0);
1257
1258 /* Calculate OD and PP low. */
1259 pres_step = 1000000000 / (bus->scl_rate.i3c * 4);
1260 ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
1261 if (ncycles < 0)
1262 ncycles = 0;
1263 prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
1264 writel(prescl1, master->regs + PRESCL_CTRL1);
1265
1266 /* Get an address for the master. */
1267 ret = i3c_master_get_free_addr(m, 0);
1268 if (ret < 0)
1269 return ret;
1270
1271 writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
1272 master->regs + DEV_ID_RR0(0));
1273
1274 cdns_i3c_master_dev_rr_to_info(master, 0, &info);
1275 if (info.bcr & I3C_BCR_HDR_CAP)
1276 info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
1277
1278 ret = i3c_master_set_info(&master->base, &info);
1279 if (ret)
1280 return ret;
1281
1282 /*
1283 * Enable Hot-Join, and, when a Hot-Join request happens, disable all
1284 * events coming from this device.
1285 *
1286 * We will issue ENTDAA afterwards from the threaded IRQ handler.
1287 */
1288 ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
1289
1290 /*
1291 * Configure data hold delay based on device-specific data.
1292 *
1293 * MIPI I3C Specification 1.0 defines non-zero minimal tHD_PP timing on
1294 * master output. This setting allows to meet this timing on master's
1295 * SoC outputs, regardless of PCB balancing.
1296 */
1297 ctrl |= CTRL_THD_DELAY(cdns_i3c_master_calculate_thd_delay(master));
1298 writel(ctrl, master->regs + CTRL);
1299
1300 cdns_i3c_master_enable(master);
1301
1302 return 0;
1303}
1304
1305static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
1306 u32 ibir)
1307{
1308 struct cdns_i3c_i2c_dev_data *data;
1309 bool data_consumed = false;
1310 struct i3c_ibi_slot *slot;
1311 u32 id = IBIR_SLVID(ibir);
1312 struct i3c_dev_desc *dev;
1313 size_t nbytes;
1314 u8 *buf;
1315
1316 /*
1317 * FIXME: maybe we should report the FIFO OVF errors to the upper
1318 * layer.
1319 */
1320 if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR))
1321 goto out;
1322
1323 dev = master->ibi.slots[id];
1324 spin_lock(&master->ibi.lock);
1325
1326 data = i3c_dev_get_master_data(dev);
1327 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1328 if (!slot)
1329 goto out_unlock;
1330
1331 buf = slot->data;
1332
1333 nbytes = IBIR_XFER_BYTES(ibir);
1334 readsl(master->regs + IBI_DATA_FIFO, buf, nbytes / 4);
1335 if (nbytes % 3) {
1336 u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO);
1337
1338 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
1339 }
1340
1341 slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
1342 dev->ibi->max_payload_len);
1343 i3c_master_queue_ibi(dev, slot);
1344 data_consumed = true;
1345
1346out_unlock:
1347 spin_unlock(&master->ibi.lock);
1348
1349out:
1350 /* Consume data from the FIFO if it's not been done already. */
1351 if (!data_consumed) {
1352 int i;
1353
1354 for (i = 0; i < IBIR_XFER_BYTES(ibir); i += 4)
1355 readl(master->regs + IBI_DATA_FIFO);
1356 }
1357}
1358
1359static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master)
1360{
1361 u32 status0;
1362
1363 writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
1364
1365 for (status0 = readl(master->regs + MST_STATUS0);
1366 !(status0 & MST_STATUS0_IBIR_EMP);
1367 status0 = readl(master->regs + MST_STATUS0)) {
1368 u32 ibir = readl(master->regs + IBIR);
1369
1370 switch (IBIR_TYPE(ibir)) {
1371 case IBIR_TYPE_IBI:
1372 cdns_i3c_master_handle_ibi(master, ibir);
1373 break;
1374
1375 case IBIR_TYPE_HJ:
1376 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1377 queue_work(master->base.wq, &master->hj_work);
1378 break;
1379
1380 case IBIR_TYPE_MR:
1381 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1382 break;
1383
1384 default:
1385 break;
1386 }
1387 }
1388}
1389
1390static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data)
1391{
1392 struct cdns_i3c_master *master = data;
1393 u32 status;
1394
1395 status = readl(master->regs + MST_ISR);
1396 if (!(status & readl(master->regs + MST_IMR)))
1397 return IRQ_NONE;
1398
1399 spin_lock(&master->xferqueue.lock);
1400 cdns_i3c_master_end_xfer_locked(master, status);
1401 spin_unlock(&master->xferqueue.lock);
1402
1403 if (status & MST_INT_IBIR_THR)
1404 cnds_i3c_master_demux_ibis(master);
1405
1406 return IRQ_HANDLED;
1407}
1408
1409static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1410{
1411 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1412 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1413 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1414 unsigned long flags;
1415 u32 sirmap;
1416 int ret;
1417
1418 ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
1419 I3C_CCC_EVENT_SIR);
1420 if (ret)
1421 return ret;
1422
1423 spin_lock_irqsave(&master->ibi.lock, flags);
1424 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1425 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1426 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1427 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1428 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1429 spin_unlock_irqrestore(&master->ibi.lock, flags);
1430
1431 return ret;
1432}
1433
1434static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1435{
1436 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1437 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1438 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1439 unsigned long flags;
1440 u32 sircfg, sirmap;
1441 int ret;
1442
1443 spin_lock_irqsave(&master->ibi.lock, flags);
1444 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1445 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1446 sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) |
1447 SIR_MAP_DEV_DA(dev->info.dyn_addr) |
1448 SIR_MAP_DEV_PL(dev->info.max_ibi_len) |
1449 SIR_MAP_DEV_ACK;
1450
1451 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM)
1452 sircfg |= SIR_MAP_DEV_SLOW;
1453
1454 sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg);
1455 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1456 spin_unlock_irqrestore(&master->ibi.lock, flags);
1457
1458 ret = i3c_master_enec_locked(m, dev->info.dyn_addr,
1459 I3C_CCC_EVENT_SIR);
1460 if (ret) {
1461 spin_lock_irqsave(&master->ibi.lock, flags);
1462 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1463 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1464 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1465 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1466 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1467 spin_unlock_irqrestore(&master->ibi.lock, flags);
1468 }
1469
1470 return ret;
1471}
1472
1473static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1474 const struct i3c_ibi_setup *req)
1475{
1476 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1477 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1478 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1479 unsigned long flags;
1480 unsigned int i;
1481
1482 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1483 if (IS_ERR(data->ibi_pool))
1484 return PTR_ERR(data->ibi_pool);
1485
1486 spin_lock_irqsave(&master->ibi.lock, flags);
1487 for (i = 0; i < master->ibi.num_slots; i++) {
1488 if (!master->ibi.slots[i]) {
1489 data->ibi = i;
1490 master->ibi.slots[i] = dev;
1491 break;
1492 }
1493 }
1494 spin_unlock_irqrestore(&master->ibi.lock, flags);
1495
1496 if (i < master->ibi.num_slots)
1497 return 0;
1498
1499 i3c_generic_ibi_free_pool(data->ibi_pool);
1500 data->ibi_pool = NULL;
1501
1502 return -ENOSPC;
1503}
1504
1505static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1506{
1507 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1508 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1509 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1510 unsigned long flags;
1511
1512 spin_lock_irqsave(&master->ibi.lock, flags);
1513 master->ibi.slots[data->ibi] = NULL;
1514 data->ibi = -1;
1515 spin_unlock_irqrestore(&master->ibi.lock, flags);
1516
1517 i3c_generic_ibi_free_pool(data->ibi_pool);
1518}
1519
1520static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1521 struct i3c_ibi_slot *slot)
1522{
1523 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1524
1525 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1526}
1527
1528static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
1529 .bus_init = cdns_i3c_master_bus_init,
1530 .bus_cleanup = cdns_i3c_master_bus_cleanup,
1531 .do_daa = cdns_i3c_master_do_daa,
1532 .attach_i3c_dev = cdns_i3c_master_attach_i3c_dev,
1533 .reattach_i3c_dev = cdns_i3c_master_reattach_i3c_dev,
1534 .detach_i3c_dev = cdns_i3c_master_detach_i3c_dev,
1535 .attach_i2c_dev = cdns_i3c_master_attach_i2c_dev,
1536 .detach_i2c_dev = cdns_i3c_master_detach_i2c_dev,
1537 .supports_ccc_cmd = cdns_i3c_master_supports_ccc_cmd,
1538 .send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
1539 .priv_xfers = cdns_i3c_master_priv_xfers,
1540 .i2c_xfers = cdns_i3c_master_i2c_xfers,
1541 .enable_ibi = cdns_i3c_master_enable_ibi,
1542 .disable_ibi = cdns_i3c_master_disable_ibi,
1543 .request_ibi = cdns_i3c_master_request_ibi,
1544 .free_ibi = cdns_i3c_master_free_ibi,
1545 .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot,
1546};
1547
1548static void cdns_i3c_master_hj(struct work_struct *work)
1549{
1550 struct cdns_i3c_master *master = container_of(work,
1551 struct cdns_i3c_master,
1552 hj_work);
1553
1554 i3c_master_do_daa(&master->base);
1555}
1556
1557static struct cdns_i3c_data cdns_i3c_devdata = {
1558 .thd_delay_ns = 10,
1559};
1560
1561static const struct of_device_id cdns_i3c_master_of_ids[] = {
1562 { .compatible = "cdns,i3c-master", .data = &cdns_i3c_devdata },
1563 { /* sentinel */ },
1564};
1565
1566static int cdns_i3c_master_probe(struct platform_device *pdev)
1567{
1568 struct cdns_i3c_master *master;
1569 int ret, irq;
1570 u32 val;
1571
1572 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1573 if (!master)
1574 return -ENOMEM;
1575
1576 master->devdata = of_device_get_match_data(&pdev->dev);
1577 if (!master->devdata)
1578 return -EINVAL;
1579
1580 master->regs = devm_platform_ioremap_resource(pdev, 0);
1581 if (IS_ERR(master->regs))
1582 return PTR_ERR(master->regs);
1583
1584 master->pclk = devm_clk_get(&pdev->dev, "pclk");
1585 if (IS_ERR(master->pclk))
1586 return PTR_ERR(master->pclk);
1587
1588 master->sysclk = devm_clk_get(&pdev->dev, "sysclk");
1589 if (IS_ERR(master->sysclk))
1590 return PTR_ERR(master->sysclk);
1591
1592 irq = platform_get_irq(pdev, 0);
1593 if (irq < 0)
1594 return irq;
1595
1596 ret = clk_prepare_enable(master->pclk);
1597 if (ret)
1598 return ret;
1599
1600 ret = clk_prepare_enable(master->sysclk);
1601 if (ret)
1602 goto err_disable_pclk;
1603
1604 if (readl(master->regs + DEV_ID) != DEV_ID_I3C_MASTER) {
1605 ret = -EINVAL;
1606 goto err_disable_sysclk;
1607 }
1608
1609 spin_lock_init(&master->xferqueue.lock);
1610 INIT_LIST_HEAD(&master->xferqueue.list);
1611
1612 INIT_WORK(&master->hj_work, cdns_i3c_master_hj);
1613 writel(0xffffffff, master->regs + MST_IDR);
1614 writel(0xffffffff, master->regs + SLV_IDR);
1615 ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0,
1616 dev_name(&pdev->dev), master);
1617 if (ret)
1618 goto err_disable_sysclk;
1619
1620 platform_set_drvdata(pdev, master);
1621
1622 val = readl(master->regs + CONF_STATUS0);
1623
1624 /* Device ID0 is reserved to describe this master. */
1625 master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
1626 master->free_rr_slots = GENMASK(master->maxdevs, 1);
1627
1628 val = readl(master->regs + CONF_STATUS1);
1629 master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
1630 master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
1631 master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
1632 master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
1633 master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
1634
1635 spin_lock_init(&master->ibi.lock);
1636 master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
1637 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1638 sizeof(*master->ibi.slots),
1639 GFP_KERNEL);
1640 if (!master->ibi.slots) {
1641 ret = -ENOMEM;
1642 goto err_disable_sysclk;
1643 }
1644
1645 writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
1646 writel(MST_INT_IBIR_THR, master->regs + MST_IER);
1647 writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
1648
1649 ret = i3c_master_register(&master->base, &pdev->dev,
1650 &cdns_i3c_master_ops, false);
1651 if (ret)
1652 goto err_disable_sysclk;
1653
1654 return 0;
1655
1656err_disable_sysclk:
1657 clk_disable_unprepare(master->sysclk);
1658
1659err_disable_pclk:
1660 clk_disable_unprepare(master->pclk);
1661
1662 return ret;
1663}
1664
1665static int cdns_i3c_master_remove(struct platform_device *pdev)
1666{
1667 struct cdns_i3c_master *master = platform_get_drvdata(pdev);
1668 int ret;
1669
1670 ret = i3c_master_unregister(&master->base);
1671 if (ret)
1672 return ret;
1673
1674 clk_disable_unprepare(master->sysclk);
1675 clk_disable_unprepare(master->pclk);
1676
1677 return 0;
1678}
1679
1680static struct platform_driver cdns_i3c_master = {
1681 .probe = cdns_i3c_master_probe,
1682 .remove = cdns_i3c_master_remove,
1683 .driver = {
1684 .name = "cdns-i3c-master",
1685 .of_match_table = cdns_i3c_master_of_ids,
1686 },
1687};
1688module_platform_driver(cdns_i3c_master);
1689
1690MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1691MODULE_DESCRIPTION("Cadence I3C master driver");
1692MODULE_LICENSE("GPL v2");
1693MODULE_ALIAS("platform:cdns-i3c-master");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Cadence Design Systems Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/errno.h>
12#include <linux/i3c/master.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/ioport.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/workqueue.h>
25
26#define DEV_ID 0x0
27#define DEV_ID_I3C_MASTER 0x5034
28
29#define CONF_STATUS0 0x4
30#define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
31#define CONF_STATUS0_ECC_CHK BIT(28)
32#define CONF_STATUS0_INTEG_CHK BIT(27)
33#define CONF_STATUS0_CSR_DAP_CHK BIT(26)
34#define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
35#define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
36#define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
37#define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
38#define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
39#define CONF_STATUS0_SUPPORTS_DDR BIT(5)
40#define CONF_STATUS0_SEC_MASTER BIT(4)
41#define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
42
43#define CONF_STATUS1 0x8
44#define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
45#define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
46#define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
47#define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
48#define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
49#define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
50#define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
51
52#define REV_ID 0xc
53#define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
54#define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
55#define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
56#define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
57
58#define CTRL 0x10
59#define CTRL_DEV_EN BIT(31)
60#define CTRL_HALT_EN BIT(30)
61#define CTRL_MCS BIT(29)
62#define CTRL_MCS_EN BIT(28)
63#define CTRL_HJ_DISEC BIT(8)
64#define CTRL_MST_ACK BIT(7)
65#define CTRL_HJ_ACK BIT(6)
66#define CTRL_HJ_INIT BIT(5)
67#define CTRL_MST_INIT BIT(4)
68#define CTRL_AHDR_OPT BIT(3)
69#define CTRL_PURE_BUS_MODE 0
70#define CTRL_MIXED_FAST_BUS_MODE 2
71#define CTRL_MIXED_SLOW_BUS_MODE 3
72#define CTRL_BUS_MODE_MASK GENMASK(1, 0)
73
74#define PRESCL_CTRL0 0x14
75#define PRESCL_CTRL0_I2C(x) ((x) << 16)
76#define PRESCL_CTRL0_I3C(x) (x)
77#define PRESCL_CTRL0_MAX GENMASK(9, 0)
78
79#define PRESCL_CTRL1 0x18
80#define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
81#define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
82#define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
83#define PRESCL_CTRL1_OD_LOW(x) (x)
84
85#define MST_IER 0x20
86#define MST_IDR 0x24
87#define MST_IMR 0x28
88#define MST_ICR 0x2c
89#define MST_ISR 0x30
90#define MST_INT_HALTED BIT(18)
91#define MST_INT_MR_DONE BIT(17)
92#define MST_INT_IMM_COMP BIT(16)
93#define MST_INT_TX_THR BIT(15)
94#define MST_INT_TX_OVF BIT(14)
95#define MST_INT_IBID_THR BIT(12)
96#define MST_INT_IBID_UNF BIT(11)
97#define MST_INT_IBIR_THR BIT(10)
98#define MST_INT_IBIR_UNF BIT(9)
99#define MST_INT_IBIR_OVF BIT(8)
100#define MST_INT_RX_THR BIT(7)
101#define MST_INT_RX_UNF BIT(6)
102#define MST_INT_CMDD_EMP BIT(5)
103#define MST_INT_CMDD_THR BIT(4)
104#define MST_INT_CMDD_OVF BIT(3)
105#define MST_INT_CMDR_THR BIT(2)
106#define MST_INT_CMDR_UNF BIT(1)
107#define MST_INT_CMDR_OVF BIT(0)
108
109#define MST_STATUS0 0x34
110#define MST_STATUS0_IDLE BIT(18)
111#define MST_STATUS0_HALTED BIT(17)
112#define MST_STATUS0_MASTER_MODE BIT(16)
113#define MST_STATUS0_TX_FULL BIT(13)
114#define MST_STATUS0_IBID_FULL BIT(12)
115#define MST_STATUS0_IBIR_FULL BIT(11)
116#define MST_STATUS0_RX_FULL BIT(10)
117#define MST_STATUS0_CMDD_FULL BIT(9)
118#define MST_STATUS0_CMDR_FULL BIT(8)
119#define MST_STATUS0_TX_EMP BIT(5)
120#define MST_STATUS0_IBID_EMP BIT(4)
121#define MST_STATUS0_IBIR_EMP BIT(3)
122#define MST_STATUS0_RX_EMP BIT(2)
123#define MST_STATUS0_CMDD_EMP BIT(1)
124#define MST_STATUS0_CMDR_EMP BIT(0)
125
126#define CMDR 0x38
127#define CMDR_NO_ERROR 0
128#define CMDR_DDR_PREAMBLE_ERROR 1
129#define CMDR_DDR_PARITY_ERROR 2
130#define CMDR_DDR_RX_FIFO_OVF 3
131#define CMDR_DDR_TX_FIFO_UNF 4
132#define CMDR_M0_ERROR 5
133#define CMDR_M1_ERROR 6
134#define CMDR_M2_ERROR 7
135#define CMDR_MST_ABORT 8
136#define CMDR_NACK_RESP 9
137#define CMDR_INVALID_DA 10
138#define CMDR_DDR_DROPPED 11
139#define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)
140#define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)
141#define CMDR_CMDID_HJACK_DISEC 0xfe
142#define CMDR_CMDID_HJACK_ENTDAA 0xff
143#define CMDR_CMDID(x) ((x) & GENMASK(7, 0))
144
145#define IBIR 0x3c
146#define IBIR_ACKED BIT(12)
147#define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)
148#define IBIR_ERROR BIT(7)
149#define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)
150#define IBIR_TYPE_IBI 0
151#define IBIR_TYPE_HJ 1
152#define IBIR_TYPE_MR 2
153#define IBIR_TYPE(x) ((x) & GENMASK(1, 0))
154
155#define SLV_IER 0x40
156#define SLV_IDR 0x44
157#define SLV_IMR 0x48
158#define SLV_ICR 0x4c
159#define SLV_ISR 0x50
160#define SLV_INT_TM BIT(20)
161#define SLV_INT_ERROR BIT(19)
162#define SLV_INT_EVENT_UP BIT(18)
163#define SLV_INT_HJ_DONE BIT(17)
164#define SLV_INT_MR_DONE BIT(16)
165#define SLV_INT_DA_UPD BIT(15)
166#define SLV_INT_SDR_FAIL BIT(14)
167#define SLV_INT_DDR_FAIL BIT(13)
168#define SLV_INT_M_RD_ABORT BIT(12)
169#define SLV_INT_DDR_RX_THR BIT(11)
170#define SLV_INT_DDR_TX_THR BIT(10)
171#define SLV_INT_SDR_RX_THR BIT(9)
172#define SLV_INT_SDR_TX_THR BIT(8)
173#define SLV_INT_DDR_RX_UNF BIT(7)
174#define SLV_INT_DDR_TX_OVF BIT(6)
175#define SLV_INT_SDR_RX_UNF BIT(5)
176#define SLV_INT_SDR_TX_OVF BIT(4)
177#define SLV_INT_DDR_RD_COMP BIT(3)
178#define SLV_INT_DDR_WR_COMP BIT(2)
179#define SLV_INT_SDR_RD_COMP BIT(1)
180#define SLV_INT_SDR_WR_COMP BIT(0)
181
182#define SLV_STATUS0 0x54
183#define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)
184#define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))
185
186#define SLV_STATUS1 0x58
187#define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)
188#define SLV_STATUS1_VEN_TM BIT(19)
189#define SLV_STATUS1_HJ_DIS BIT(18)
190#define SLV_STATUS1_MR_DIS BIT(17)
191#define SLV_STATUS1_PROT_ERR BIT(16)
192#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
193#define SLV_STATUS1_HAS_DA BIT(8)
194#define SLV_STATUS1_DDR_RX_FULL BIT(7)
195#define SLV_STATUS1_DDR_TX_FULL BIT(6)
196#define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
197#define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
198#define SLV_STATUS1_SDR_RX_FULL BIT(3)
199#define SLV_STATUS1_SDR_TX_FULL BIT(2)
200#define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
201#define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
202
203#define CMD0_FIFO 0x60
204#define CMD0_FIFO_IS_DDR BIT(31)
205#define CMD0_FIFO_IS_CCC BIT(30)
206#define CMD0_FIFO_BCH BIT(29)
207#define XMIT_BURST_STATIC_SUBADDR 0
208#define XMIT_SINGLE_INC_SUBADDR 1
209#define XMIT_SINGLE_STATIC_SUBADDR 2
210#define XMIT_BURST_WITHOUT_SUBADDR 3
211#define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
212#define CMD0_FIFO_SBCA BIT(26)
213#define CMD0_FIFO_RSBC BIT(25)
214#define CMD0_FIFO_IS_10B BIT(24)
215#define CMD0_FIFO_PL_LEN(l) ((l) << 12)
216#define CMD0_FIFO_PL_LEN_MAX 4095
217#define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
218#define CMD0_FIFO_RNW BIT(0)
219
220#define CMD1_FIFO 0x64
221#define CMD1_FIFO_CMDID(id) ((id) << 24)
222#define CMD1_FIFO_CSRADDR(a) (a)
223#define CMD1_FIFO_CCC(id) (id)
224
225#define TX_FIFO 0x68
226
227#define IMD_CMD0 0x70
228#define IMD_CMD0_PL_LEN(l) ((l) << 12)
229#define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
230#define IMD_CMD0_RNW BIT(0)
231
232#define IMD_CMD1 0x74
233#define IMD_CMD1_CCC(id) (id)
234
235#define IMD_DATA 0x78
236#define RX_FIFO 0x80
237#define IBI_DATA_FIFO 0x84
238#define SLV_DDR_TX_FIFO 0x88
239#define SLV_DDR_RX_FIFO 0x8c
240
241#define CMD_IBI_THR_CTRL 0x90
242#define IBIR_THR(t) ((t) << 24)
243#define CMDR_THR(t) ((t) << 16)
244#define IBI_THR(t) ((t) << 8)
245#define CMD_THR(t) (t)
246
247#define TX_RX_THR_CTRL 0x94
248#define RX_THR(t) ((t) << 16)
249#define TX_THR(t) (t)
250
251#define SLV_DDR_TX_RX_THR_CTRL 0x98
252#define SLV_DDR_RX_THR(t) ((t) << 16)
253#define SLV_DDR_TX_THR(t) (t)
254
255#define FLUSH_CTRL 0x9c
256#define FLUSH_IBI_RESP BIT(23)
257#define FLUSH_CMD_RESP BIT(22)
258#define FLUSH_SLV_DDR_RX_FIFO BIT(22)
259#define FLUSH_SLV_DDR_TX_FIFO BIT(21)
260#define FLUSH_IMM_FIFO BIT(20)
261#define FLUSH_IBI_FIFO BIT(19)
262#define FLUSH_RX_FIFO BIT(18)
263#define FLUSH_TX_FIFO BIT(17)
264#define FLUSH_CMD_FIFO BIT(16)
265
266#define TTO_PRESCL_CTRL0 0xb0
267#define TTO_PRESCL_CTRL0_DIVB(x) ((x) << 16)
268#define TTO_PRESCL_CTRL0_DIVA(x) (x)
269
270#define TTO_PRESCL_CTRL1 0xb4
271#define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
272#define TTO_PRESCL_CTRL1_DIVA(x) (x)
273
274#define DEVS_CTRL 0xb8
275#define DEVS_CTRL_DEV_CLR_SHIFT 16
276#define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
277#define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
278#define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
279#define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
280#define MAX_DEVS 16
281
282#define DEV_ID_RR0(d) (0xc0 + ((d) * 0x10))
283#define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
284#define DEV_ID_RR0_HDR_CAP BIT(10)
285#define DEV_ID_RR0_IS_I3C BIT(9)
286#define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
287#define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \
288 (((a) & GENMASK(9, 7)) << 6))
289#define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \
290 (((x) >> 6) & GENMASK(9, 7)))
291
292#define DEV_ID_RR1(d) (0xc4 + ((d) * 0x10))
293#define DEV_ID_RR1_PID_MSB(pid) (pid)
294
295#define DEV_ID_RR2(d) (0xc8 + ((d) * 0x10))
296#define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
297#define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
298#define DEV_ID_RR2_DCR(dcr) (dcr)
299#define DEV_ID_RR2_LVR(lvr) (lvr)
300
301#define SIR_MAP(x) (0x180 + ((x) * 4))
302#define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
303#define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
304#define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
305#define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
306#define DEV_ROLE_SLAVE 0
307#define DEV_ROLE_MASTER 1
308#define SIR_MAP_DEV_ROLE(role) ((role) << 14)
309#define SIR_MAP_DEV_SLOW BIT(13)
310#define SIR_MAP_DEV_PL(l) ((l) << 8)
311#define SIR_MAP_PL_MAX GENMASK(4, 0)
312#define SIR_MAP_DEV_DA(a) ((a) << 1)
313#define SIR_MAP_DEV_ACK BIT(0)
314
315#define GPIR_WORD(x) (0x200 + ((x) * 4))
316#define GPI_REG(val, id) \
317 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
318
319#define GPOR_WORD(x) (0x220 + ((x) * 4))
320#define GPO_REG(val, id) \
321 (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
322
323#define ASF_INT_STATUS 0x300
324#define ASF_INT_RAW_STATUS 0x304
325#define ASF_INT_MASK 0x308
326#define ASF_INT_TEST 0x30c
327#define ASF_INT_FATAL_SELECT 0x310
328#define ASF_INTEGRITY_ERR BIT(6)
329#define ASF_PROTOCOL_ERR BIT(5)
330#define ASF_TRANS_TIMEOUT_ERR BIT(4)
331#define ASF_CSR_ERR BIT(3)
332#define ASF_DAP_ERR BIT(2)
333#define ASF_SRAM_UNCORR_ERR BIT(1)
334#define ASF_SRAM_CORR_ERR BIT(0)
335
336#define ASF_SRAM_CORR_FAULT_STATUS 0x320
337#define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
338#define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
339#define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))
340
341#define ASF_SRAM_FAULT_STATS 0x328
342#define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
343#define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))
344
345#define ASF_TRANS_TOUT_CTRL 0x330
346#define ASF_TRANS_TOUT_EN BIT(31)
347#define ASF_TRANS_TOUT_VAL(x) (x)
348
349#define ASF_TRANS_TOUT_FAULT_MASK 0x334
350#define ASF_TRANS_TOUT_FAULT_STATUS 0x338
351#define ASF_TRANS_TOUT_FAULT_APB BIT(3)
352#define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
353#define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
354#define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
355
356#define ASF_PROTO_FAULT_MASK 0x340
357#define ASF_PROTO_FAULT_STATUS 0x344
358#define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
359#define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
360#define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
361#define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
362#define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
363#define ASF_PROTO_FAULT_M(x) BIT(x)
364
365struct cdns_i3c_master_caps {
366 u32 cmdfifodepth;
367 u32 cmdrfifodepth;
368 u32 txfifodepth;
369 u32 rxfifodepth;
370 u32 ibirfifodepth;
371};
372
373struct cdns_i3c_cmd {
374 u32 cmd0;
375 u32 cmd1;
376 u32 tx_len;
377 const void *tx_buf;
378 u32 rx_len;
379 void *rx_buf;
380 u32 error;
381};
382
383struct cdns_i3c_xfer {
384 struct list_head node;
385 struct completion comp;
386 int ret;
387 unsigned int ncmds;
388 struct cdns_i3c_cmd cmds[0];
389};
390
391struct cdns_i3c_master {
392 struct work_struct hj_work;
393 struct i3c_master_controller base;
394 u32 free_rr_slots;
395 unsigned int maxdevs;
396 struct {
397 unsigned int num_slots;
398 struct i3c_dev_desc **slots;
399 spinlock_t lock;
400 } ibi;
401 struct {
402 struct list_head list;
403 struct cdns_i3c_xfer *cur;
404 spinlock_t lock;
405 } xferqueue;
406 void __iomem *regs;
407 struct clk *sysclk;
408 struct clk *pclk;
409 struct cdns_i3c_master_caps caps;
410 unsigned long i3c_scl_lim;
411};
412
413static inline struct cdns_i3c_master *
414to_cdns_i3c_master(struct i3c_master_controller *master)
415{
416 return container_of(master, struct cdns_i3c_master, base);
417}
418
419static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
420 const u8 *bytes, int nbytes)
421{
422 writesl(master->regs + TX_FIFO, bytes, nbytes / 4);
423 if (nbytes & 3) {
424 u32 tmp = 0;
425
426 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
427 writesl(master->regs + TX_FIFO, &tmp, 1);
428 }
429}
430
431static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
432 u8 *bytes, int nbytes)
433{
434 readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
435 if (nbytes & 3) {
436 u32 tmp;
437
438 readsl(master->regs + RX_FIFO, &tmp, 1);
439 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
440 }
441}
442
443static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
444 const struct i3c_ccc_cmd *cmd)
445{
446 if (cmd->ndests > 1)
447 return false;
448
449 switch (cmd->id) {
450 case I3C_CCC_ENEC(true):
451 case I3C_CCC_ENEC(false):
452 case I3C_CCC_DISEC(true):
453 case I3C_CCC_DISEC(false):
454 case I3C_CCC_ENTAS(0, true):
455 case I3C_CCC_ENTAS(0, false):
456 case I3C_CCC_RSTDAA(true):
457 case I3C_CCC_RSTDAA(false):
458 case I3C_CCC_ENTDAA:
459 case I3C_CCC_SETMWL(true):
460 case I3C_CCC_SETMWL(false):
461 case I3C_CCC_SETMRL(true):
462 case I3C_CCC_SETMRL(false):
463 case I3C_CCC_DEFSLVS:
464 case I3C_CCC_ENTHDR(0):
465 case I3C_CCC_SETDASA:
466 case I3C_CCC_SETNEWDA:
467 case I3C_CCC_GETMWL:
468 case I3C_CCC_GETMRL:
469 case I3C_CCC_GETPID:
470 case I3C_CCC_GETBCR:
471 case I3C_CCC_GETDCR:
472 case I3C_CCC_GETSTATUS:
473 case I3C_CCC_GETACCMST:
474 case I3C_CCC_GETMXDS:
475 case I3C_CCC_GETHDRCAP:
476 return true;
477 default:
478 break;
479 }
480
481 return false;
482}
483
484static int cdns_i3c_master_disable(struct cdns_i3c_master *master)
485{
486 u32 status;
487
488 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
489
490 return readl_poll_timeout(master->regs + MST_STATUS0, status,
491 status & MST_STATUS0_IDLE, 10, 1000000);
492}
493
494static void cdns_i3c_master_enable(struct cdns_i3c_master *master)
495{
496 writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
497}
498
499static struct cdns_i3c_xfer *
500cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds)
501{
502 struct cdns_i3c_xfer *xfer;
503
504 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
505 if (!xfer)
506 return NULL;
507
508 INIT_LIST_HEAD(&xfer->node);
509 xfer->ncmds = ncmds;
510 xfer->ret = -ETIMEDOUT;
511
512 return xfer;
513}
514
515static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer)
516{
517 kfree(xfer);
518}
519
520static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master)
521{
522 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
523 unsigned int i;
524
525 if (!xfer)
526 return;
527
528 writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
529 for (i = 0; i < xfer->ncmds; i++) {
530 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
531
532 cdns_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf,
533 cmd->tx_len);
534 }
535
536 for (i = 0; i < xfer->ncmds; i++) {
537 struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
538
539 writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
540 master->regs + CMD1_FIFO);
541 writel(cmd->cmd0, master->regs + CMD0_FIFO);
542 }
543
544 writel(readl(master->regs + CTRL) | CTRL_MCS,
545 master->regs + CTRL);
546 writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
547}
548
549static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master,
550 u32 isr)
551{
552 struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
553 int i, ret = 0;
554 u32 status0;
555
556 if (!xfer)
557 return;
558
559 if (!(isr & MST_INT_CMDD_EMP))
560 return;
561
562 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
563
564 for (status0 = readl(master->regs + MST_STATUS0);
565 !(status0 & MST_STATUS0_CMDR_EMP);
566 status0 = readl(master->regs + MST_STATUS0)) {
567 struct cdns_i3c_cmd *cmd;
568 u32 cmdr, rx_len, id;
569
570 cmdr = readl(master->regs + CMDR);
571 id = CMDR_CMDID(cmdr);
572 if (id == CMDR_CMDID_HJACK_DISEC ||
573 id == CMDR_CMDID_HJACK_ENTDAA ||
574 WARN_ON(id >= xfer->ncmds))
575 continue;
576
577 cmd = &xfer->cmds[CMDR_CMDID(cmdr)];
578 rx_len = min_t(u32, CMDR_XFER_BYTES(cmdr), cmd->rx_len);
579 cdns_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
580 cmd->error = CMDR_ERROR(cmdr);
581 }
582
583 for (i = 0; i < xfer->ncmds; i++) {
584 switch (xfer->cmds[i].error) {
585 case CMDR_NO_ERROR:
586 break;
587
588 case CMDR_DDR_PREAMBLE_ERROR:
589 case CMDR_DDR_PARITY_ERROR:
590 case CMDR_M0_ERROR:
591 case CMDR_M1_ERROR:
592 case CMDR_M2_ERROR:
593 case CMDR_MST_ABORT:
594 case CMDR_NACK_RESP:
595 case CMDR_DDR_DROPPED:
596 ret = -EIO;
597 break;
598
599 case CMDR_DDR_RX_FIFO_OVF:
600 case CMDR_DDR_TX_FIFO_UNF:
601 ret = -ENOSPC;
602 break;
603
604 case CMDR_INVALID_DA:
605 default:
606 ret = -EINVAL;
607 break;
608 }
609 }
610
611 xfer->ret = ret;
612 complete(&xfer->comp);
613
614 xfer = list_first_entry_or_null(&master->xferqueue.list,
615 struct cdns_i3c_xfer, node);
616 if (xfer)
617 list_del_init(&xfer->node);
618
619 master->xferqueue.cur = xfer;
620 cdns_i3c_master_start_xfer_locked(master);
621}
622
623static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master,
624 struct cdns_i3c_xfer *xfer)
625{
626 unsigned long flags;
627
628 init_completion(&xfer->comp);
629 spin_lock_irqsave(&master->xferqueue.lock, flags);
630 if (master->xferqueue.cur) {
631 list_add_tail(&xfer->node, &master->xferqueue.list);
632 } else {
633 master->xferqueue.cur = xfer;
634 cdns_i3c_master_start_xfer_locked(master);
635 }
636 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
637}
638
639static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master,
640 struct cdns_i3c_xfer *xfer)
641{
642 unsigned long flags;
643
644 spin_lock_irqsave(&master->xferqueue.lock, flags);
645 if (master->xferqueue.cur == xfer) {
646 u32 status;
647
648 writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
649 master->regs + CTRL);
650 readl_poll_timeout_atomic(master->regs + MST_STATUS0, status,
651 status & MST_STATUS0_IDLE, 10,
652 1000000);
653 master->xferqueue.cur = NULL;
654 writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
655 FLUSH_CMD_RESP,
656 master->regs + FLUSH_CTRL);
657 writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
658 writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
659 master->regs + CTRL);
660 } else {
661 list_del_init(&xfer->node);
662 }
663 spin_unlock_irqrestore(&master->xferqueue.lock, flags);
664}
665
666static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd)
667{
668 switch (cmd->error) {
669 case CMDR_M0_ERROR:
670 return I3C_ERROR_M0;
671
672 case CMDR_M1_ERROR:
673 return I3C_ERROR_M1;
674
675 case CMDR_M2_ERROR:
676 case CMDR_NACK_RESP:
677 return I3C_ERROR_M2;
678
679 default:
680 break;
681 }
682
683 return I3C_ERROR_UNKNOWN;
684}
685
686static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
687 struct i3c_ccc_cmd *cmd)
688{
689 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
690 struct cdns_i3c_xfer *xfer;
691 struct cdns_i3c_cmd *ccmd;
692 int ret;
693
694 xfer = cdns_i3c_master_alloc_xfer(master, 1);
695 if (!xfer)
696 return -ENOMEM;
697
698 ccmd = xfer->cmds;
699 ccmd->cmd1 = CMD1_FIFO_CCC(cmd->id);
700 ccmd->cmd0 = CMD0_FIFO_IS_CCC |
701 CMD0_FIFO_PL_LEN(cmd->dests[0].payload.len);
702
703 if (cmd->id & I3C_CCC_DIRECT)
704 ccmd->cmd0 |= CMD0_FIFO_DEV_ADDR(cmd->dests[0].addr);
705
706 if (cmd->rnw) {
707 ccmd->cmd0 |= CMD0_FIFO_RNW;
708 ccmd->rx_buf = cmd->dests[0].payload.data;
709 ccmd->rx_len = cmd->dests[0].payload.len;
710 } else {
711 ccmd->tx_buf = cmd->dests[0].payload.data;
712 ccmd->tx_len = cmd->dests[0].payload.len;
713 }
714
715 cdns_i3c_master_queue_xfer(master, xfer);
716 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
717 cdns_i3c_master_unqueue_xfer(master, xfer);
718
719 ret = xfer->ret;
720 cmd->err = cdns_i3c_cmd_get_err(&xfer->cmds[0]);
721 cdns_i3c_master_free_xfer(xfer);
722
723 return ret;
724}
725
726static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
727 struct i3c_priv_xfer *xfers,
728 int nxfers)
729{
730 struct i3c_master_controller *m = i3c_dev_get_master(dev);
731 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
732 int txslots = 0, rxslots = 0, i, ret;
733 struct cdns_i3c_xfer *cdns_xfer;
734
735 for (i = 0; i < nxfers; i++) {
736 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
737 return -ENOTSUPP;
738 }
739
740 if (!nxfers)
741 return 0;
742
743 if (nxfers > master->caps.cmdfifodepth ||
744 nxfers > master->caps.cmdrfifodepth)
745 return -ENOTSUPP;
746
747 /*
748 * First make sure that all transactions (block of transfers separated
749 * by a STOP marker) fit in the FIFOs.
750 */
751 for (i = 0; i < nxfers; i++) {
752 if (xfers[i].rnw)
753 rxslots += DIV_ROUND_UP(xfers[i].len, 4);
754 else
755 txslots += DIV_ROUND_UP(xfers[i].len, 4);
756 }
757
758 if (rxslots > master->caps.rxfifodepth ||
759 txslots > master->caps.txfifodepth)
760 return -ENOTSUPP;
761
762 cdns_xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
763 if (!cdns_xfer)
764 return -ENOMEM;
765
766 for (i = 0; i < nxfers; i++) {
767 struct cdns_i3c_cmd *ccmd = &cdns_xfer->cmds[i];
768 u32 pl_len = xfers[i].len;
769
770 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(dev->info.dyn_addr) |
771 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
772
773 if (xfers[i].rnw) {
774 ccmd->cmd0 |= CMD0_FIFO_RNW;
775 ccmd->rx_buf = xfers[i].data.in;
776 ccmd->rx_len = xfers[i].len;
777 pl_len++;
778 } else {
779 ccmd->tx_buf = xfers[i].data.out;
780 ccmd->tx_len = xfers[i].len;
781 }
782
783 ccmd->cmd0 |= CMD0_FIFO_PL_LEN(pl_len);
784
785 if (i < nxfers - 1)
786 ccmd->cmd0 |= CMD0_FIFO_RSBC;
787
788 if (!i)
789 ccmd->cmd0 |= CMD0_FIFO_BCH;
790 }
791
792 cdns_i3c_master_queue_xfer(master, cdns_xfer);
793 if (!wait_for_completion_timeout(&cdns_xfer->comp,
794 msecs_to_jiffies(1000)))
795 cdns_i3c_master_unqueue_xfer(master, cdns_xfer);
796
797 ret = cdns_xfer->ret;
798
799 for (i = 0; i < nxfers; i++)
800 xfers[i].err = cdns_i3c_cmd_get_err(&cdns_xfer->cmds[i]);
801
802 cdns_i3c_master_free_xfer(cdns_xfer);
803
804 return ret;
805}
806
807static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
808 const struct i2c_msg *xfers, int nxfers)
809{
810 struct i3c_master_controller *m = i2c_dev_get_master(dev);
811 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
812 unsigned int nrxwords = 0, ntxwords = 0;
813 struct cdns_i3c_xfer *xfer;
814 int i, ret = 0;
815
816 if (nxfers > master->caps.cmdfifodepth)
817 return -ENOTSUPP;
818
819 for (i = 0; i < nxfers; i++) {
820 if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
821 return -ENOTSUPP;
822
823 if (xfers[i].flags & I2C_M_RD)
824 nrxwords += DIV_ROUND_UP(xfers[i].len, 4);
825 else
826 ntxwords += DIV_ROUND_UP(xfers[i].len, 4);
827 }
828
829 if (ntxwords > master->caps.txfifodepth ||
830 nrxwords > master->caps.rxfifodepth)
831 return -ENOTSUPP;
832
833 xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
834 if (!xfer)
835 return -ENOMEM;
836
837 for (i = 0; i < nxfers; i++) {
838 struct cdns_i3c_cmd *ccmd = &xfer->cmds[i];
839
840 ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(xfers[i].addr) |
841 CMD0_FIFO_PL_LEN(xfers[i].len) |
842 CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
843
844 if (xfers[i].flags & I2C_M_TEN)
845 ccmd->cmd0 |= CMD0_FIFO_IS_10B;
846
847 if (xfers[i].flags & I2C_M_RD) {
848 ccmd->cmd0 |= CMD0_FIFO_RNW;
849 ccmd->rx_buf = xfers[i].buf;
850 ccmd->rx_len = xfers[i].len;
851 } else {
852 ccmd->tx_buf = xfers[i].buf;
853 ccmd->tx_len = xfers[i].len;
854 }
855 }
856
857 cdns_i3c_master_queue_xfer(master, xfer);
858 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
859 cdns_i3c_master_unqueue_xfer(master, xfer);
860
861 ret = xfer->ret;
862 cdns_i3c_master_free_xfer(xfer);
863
864 return ret;
865}
866
867struct cdns_i3c_i2c_dev_data {
868 u16 id;
869 s16 ibi;
870 struct i3c_generic_ibi_pool *ibi_pool;
871};
872
873static u32 prepare_rr0_dev_address(u32 addr)
874{
875 u32 ret = (addr << 1) & 0xff;
876
877 /* RR0[7:1] = addr[6:0] */
878 ret |= (addr & GENMASK(6, 0)) << 1;
879
880 /* RR0[15:13] = addr[9:7] */
881 ret |= (addr & GENMASK(9, 7)) << 6;
882
883 /* RR0[0] = ~XOR(addr[6:0]) */
884 if (!(hweight8(addr & 0x7f) & 1))
885 ret |= 1;
886
887 return ret;
888}
889
890static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev)
891{
892 struct i3c_master_controller *m = i3c_dev_get_master(dev);
893 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
894 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
895 u32 rr;
896
897 rr = prepare_rr0_dev_address(dev->info.dyn_addr ?
898 dev->info.dyn_addr :
899 dev->info.static_addr);
900 writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
901}
902
903static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master,
904 u8 dyn_addr)
905{
906 unsigned long activedevs;
907 u32 rr;
908 int i;
909
910 if (!dyn_addr) {
911 if (!master->free_rr_slots)
912 return -ENOSPC;
913
914 return ffs(master->free_rr_slots) - 1;
915 }
916
917 activedevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
918 activedevs &= ~BIT(0);
919
920 for_each_set_bit(i, &activedevs, master->maxdevs + 1) {
921 rr = readl(master->regs + DEV_ID_RR0(i));
922 if (!(rr & DEV_ID_RR0_IS_I3C) ||
923 DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr)
924 continue;
925
926 return i;
927 }
928
929 return -EINVAL;
930}
931
932static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
933 u8 old_dyn_addr)
934{
935 cdns_i3c_master_upd_i3c_addr(dev);
936
937 return 0;
938}
939
940static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
941{
942 struct i3c_master_controller *m = i3c_dev_get_master(dev);
943 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
944 struct cdns_i3c_i2c_dev_data *data;
945 int slot;
946
947 data = kzalloc(sizeof(*data), GFP_KERNEL);
948 if (!data)
949 return -ENOMEM;
950
951 slot = cdns_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
952 if (slot < 0) {
953 kfree(data);
954 return slot;
955 }
956
957 data->ibi = -1;
958 data->id = slot;
959 i3c_dev_set_master_data(dev, data);
960 master->free_rr_slots &= ~BIT(slot);
961
962 if (!dev->info.dyn_addr) {
963 cdns_i3c_master_upd_i3c_addr(dev);
964 writel(readl(master->regs + DEVS_CTRL) |
965 DEVS_CTRL_DEV_ACTIVE(data->id),
966 master->regs + DEVS_CTRL);
967 }
968
969 return 0;
970}
971
972static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
973{
974 struct i3c_master_controller *m = i3c_dev_get_master(dev);
975 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
976 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
977
978 writel(readl(master->regs + DEVS_CTRL) |
979 DEVS_CTRL_DEV_CLR(data->id),
980 master->regs + DEVS_CTRL);
981
982 i3c_dev_set_master_data(dev, NULL);
983 master->free_rr_slots |= BIT(data->id);
984 kfree(data);
985}
986
987static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
988{
989 struct i3c_master_controller *m = i2c_dev_get_master(dev);
990 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
991 struct cdns_i3c_i2c_dev_data *data;
992 int slot;
993
994 slot = cdns_i3c_master_get_rr_slot(master, 0);
995 if (slot < 0)
996 return slot;
997
998 data = kzalloc(sizeof(*data), GFP_KERNEL);
999 if (!data)
1000 return -ENOMEM;
1001
1002 data->id = slot;
1003 master->free_rr_slots &= ~BIT(slot);
1004 i2c_dev_set_master_data(dev, data);
1005
1006 writel(prepare_rr0_dev_address(dev->addr),
1007 master->regs + DEV_ID_RR0(data->id));
1008 writel(dev->lvr, master->regs + DEV_ID_RR2(data->id));
1009 writel(readl(master->regs + DEVS_CTRL) |
1010 DEVS_CTRL_DEV_ACTIVE(data->id),
1011 master->regs + DEVS_CTRL);
1012
1013 return 0;
1014}
1015
1016static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1017{
1018 struct i3c_master_controller *m = i2c_dev_get_master(dev);
1019 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1020 struct cdns_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1021
1022 writel(readl(master->regs + DEVS_CTRL) |
1023 DEVS_CTRL_DEV_CLR(data->id),
1024 master->regs + DEVS_CTRL);
1025 master->free_rr_slots |= BIT(data->id);
1026
1027 i2c_dev_set_master_data(dev, NULL);
1028 kfree(data);
1029}
1030
1031static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m)
1032{
1033 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1034
1035 cdns_i3c_master_disable(master);
1036}
1037
1038static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master,
1039 unsigned int slot,
1040 struct i3c_device_info *info)
1041{
1042 u32 rr;
1043
1044 memset(info, 0, sizeof(*info));
1045 rr = readl(master->regs + DEV_ID_RR0(slot));
1046 info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
1047 rr = readl(master->regs + DEV_ID_RR2(slot));
1048 info->dcr = rr;
1049 info->bcr = rr >> 8;
1050 info->pid = rr >> 16;
1051 info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16;
1052}
1053
1054static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master)
1055{
1056 struct i3c_master_controller *m = &master->base;
1057 unsigned long i3c_lim_period, pres_step, ncycles;
1058 struct i3c_bus *bus = i3c_master_get_bus(m);
1059 unsigned long new_i3c_scl_lim = 0;
1060 struct i3c_dev_desc *dev;
1061 u32 prescl1, ctrl;
1062
1063 i3c_bus_for_each_i3cdev(bus, dev) {
1064 unsigned long max_fscl;
1065
1066 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
1067 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
1068 switch (max_fscl) {
1069 case I3C_SDR1_FSCL_8MHZ:
1070 max_fscl = 8000000;
1071 break;
1072 case I3C_SDR2_FSCL_6MHZ:
1073 max_fscl = 6000000;
1074 break;
1075 case I3C_SDR3_FSCL_4MHZ:
1076 max_fscl = 4000000;
1077 break;
1078 case I3C_SDR4_FSCL_2MHZ:
1079 max_fscl = 2000000;
1080 break;
1081 case I3C_SDR0_FSCL_MAX:
1082 default:
1083 max_fscl = 0;
1084 break;
1085 }
1086
1087 if (max_fscl &&
1088 (new_i3c_scl_lim > max_fscl || !new_i3c_scl_lim))
1089 new_i3c_scl_lim = max_fscl;
1090 }
1091
1092 /* Only update PRESCL_CTRL1 if the I3C SCL limitation has changed. */
1093 if (new_i3c_scl_lim == master->i3c_scl_lim)
1094 return;
1095 master->i3c_scl_lim = new_i3c_scl_lim;
1096 if (!new_i3c_scl_lim)
1097 return;
1098 pres_step = 1000000000UL / (bus->scl_rate.i3c * 4);
1099
1100 /* Configure PP_LOW to meet I3C slave limitations. */
1101 prescl1 = readl(master->regs + PRESCL_CTRL1) &
1102 ~PRESCL_CTRL1_PP_LOW_MASK;
1103 ctrl = readl(master->regs + CTRL);
1104
1105 i3c_lim_period = DIV_ROUND_UP(1000000000, master->i3c_scl_lim);
1106 ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step);
1107 if (ncycles < 4)
1108 ncycles = 0;
1109 else
1110 ncycles -= 4;
1111
1112 prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
1113
1114 /* Disable I3C master before updating PRESCL_CTRL1. */
1115 if (ctrl & CTRL_DEV_EN)
1116 cdns_i3c_master_disable(master);
1117
1118 writel(prescl1, master->regs + PRESCL_CTRL1);
1119
1120 if (ctrl & CTRL_DEV_EN)
1121 cdns_i3c_master_enable(master);
1122}
1123
1124static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
1125{
1126 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1127 unsigned long olddevs, newdevs;
1128 int ret, slot;
1129 u8 addrs[MAX_DEVS] = { };
1130 u8 last_addr = 0;
1131
1132 olddevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1133 olddevs |= BIT(0);
1134
1135 /* Prepare RR slots before launching DAA. */
1136 for_each_clear_bit(slot, &olddevs, master->maxdevs + 1) {
1137 ret = i3c_master_get_free_addr(m, last_addr + 1);
1138 if (ret < 0)
1139 return -ENOSPC;
1140
1141 last_addr = ret;
1142 addrs[slot] = last_addr;
1143 writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
1144 master->regs + DEV_ID_RR0(slot));
1145 writel(0, master->regs + DEV_ID_RR1(slot));
1146 writel(0, master->regs + DEV_ID_RR2(slot));
1147 }
1148
1149 ret = i3c_master_entdaa_locked(&master->base);
1150 if (ret && ret != I3C_ERROR_M2)
1151 return ret;
1152
1153 newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1154 newdevs &= ~olddevs;
1155
1156 /*
1157 * Clear all retaining registers filled during DAA. We already
1158 * have the addressed assigned to them in the addrs array.
1159 */
1160 for_each_set_bit(slot, &newdevs, master->maxdevs + 1)
1161 i3c_master_add_i3c_dev_locked(m, addrs[slot]);
1162
1163 /*
1164 * Clear slots that ended up not being used. Can be caused by I3C
1165 * device creation failure or when the I3C device was already known
1166 * by the system but with a different address (in this case the device
1167 * already has a slot and does not need a new one).
1168 */
1169 writel(readl(master->regs + DEVS_CTRL) |
1170 master->free_rr_slots << DEVS_CTRL_DEV_CLR_SHIFT,
1171 master->regs + DEVS_CTRL);
1172
1173 i3c_master_defslvs_locked(&master->base);
1174
1175 cdns_i3c_master_upd_i3c_scl_lim(master);
1176
1177 /* Unmask Hot-Join and Mastership request interrupts. */
1178 i3c_master_enec_locked(m, I3C_BROADCAST_ADDR,
1179 I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR);
1180
1181 return 0;
1182}
1183
1184static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
1185{
1186 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1187 unsigned long pres_step, sysclk_rate, max_i2cfreq;
1188 struct i3c_bus *bus = i3c_master_get_bus(m);
1189 u32 ctrl, prescl0, prescl1, pres, low;
1190 struct i3c_device_info info = { };
1191 int ret, ncycles;
1192
1193 switch (bus->mode) {
1194 case I3C_BUS_MODE_PURE:
1195 ctrl = CTRL_PURE_BUS_MODE;
1196 break;
1197
1198 case I3C_BUS_MODE_MIXED_FAST:
1199 ctrl = CTRL_MIXED_FAST_BUS_MODE;
1200 break;
1201
1202 case I3C_BUS_MODE_MIXED_SLOW:
1203 ctrl = CTRL_MIXED_SLOW_BUS_MODE;
1204 break;
1205
1206 default:
1207 return -EINVAL;
1208 }
1209
1210 sysclk_rate = clk_get_rate(master->sysclk);
1211 if (!sysclk_rate)
1212 return -EINVAL;
1213
1214 pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
1215 if (pres > PRESCL_CTRL0_MAX)
1216 return -ERANGE;
1217
1218 bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
1219
1220 prescl0 = PRESCL_CTRL0_I3C(pres);
1221
1222 low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
1223 prescl1 = PRESCL_CTRL1_OD_LOW(low);
1224
1225 max_i2cfreq = bus->scl_rate.i2c;
1226
1227 pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
1228 if (pres > PRESCL_CTRL0_MAX)
1229 return -ERANGE;
1230
1231 bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
1232
1233 prescl0 |= PRESCL_CTRL0_I2C(pres);
1234 writel(prescl0, master->regs + PRESCL_CTRL0);
1235
1236 /* Calculate OD and PP low. */
1237 pres_step = 1000000000 / (bus->scl_rate.i3c * 4);
1238 ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
1239 if (ncycles < 0)
1240 ncycles = 0;
1241 prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
1242 writel(prescl1, master->regs + PRESCL_CTRL1);
1243
1244 /* Get an address for the master. */
1245 ret = i3c_master_get_free_addr(m, 0);
1246 if (ret < 0)
1247 return ret;
1248
1249 writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
1250 master->regs + DEV_ID_RR0(0));
1251
1252 cdns_i3c_master_dev_rr_to_info(master, 0, &info);
1253 if (info.bcr & I3C_BCR_HDR_CAP)
1254 info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
1255
1256 ret = i3c_master_set_info(&master->base, &info);
1257 if (ret)
1258 return ret;
1259
1260 /*
1261 * Enable Hot-Join, and, when a Hot-Join request happens, disable all
1262 * events coming from this device.
1263 *
1264 * We will issue ENTDAA afterwards from the threaded IRQ handler.
1265 */
1266 ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
1267 writel(ctrl, master->regs + CTRL);
1268
1269 cdns_i3c_master_enable(master);
1270
1271 return 0;
1272}
1273
1274static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
1275 u32 ibir)
1276{
1277 struct cdns_i3c_i2c_dev_data *data;
1278 bool data_consumed = false;
1279 struct i3c_ibi_slot *slot;
1280 u32 id = IBIR_SLVID(ibir);
1281 struct i3c_dev_desc *dev;
1282 size_t nbytes;
1283 u8 *buf;
1284
1285 /*
1286 * FIXME: maybe we should report the FIFO OVF errors to the upper
1287 * layer.
1288 */
1289 if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR))
1290 goto out;
1291
1292 dev = master->ibi.slots[id];
1293 spin_lock(&master->ibi.lock);
1294
1295 data = i3c_dev_get_master_data(dev);
1296 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
1297 if (!slot)
1298 goto out_unlock;
1299
1300 buf = slot->data;
1301
1302 nbytes = IBIR_XFER_BYTES(ibir);
1303 readsl(master->regs + IBI_DATA_FIFO, buf, nbytes / 4);
1304 if (nbytes % 3) {
1305 u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO);
1306
1307 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
1308 }
1309
1310 slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
1311 dev->ibi->max_payload_len);
1312 i3c_master_queue_ibi(dev, slot);
1313 data_consumed = true;
1314
1315out_unlock:
1316 spin_unlock(&master->ibi.lock);
1317
1318out:
1319 /* Consume data from the FIFO if it's not been done already. */
1320 if (!data_consumed) {
1321 int i;
1322
1323 for (i = 0; i < IBIR_XFER_BYTES(ibir); i += 4)
1324 readl(master->regs + IBI_DATA_FIFO);
1325 }
1326}
1327
1328static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master)
1329{
1330 u32 status0;
1331
1332 writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
1333
1334 for (status0 = readl(master->regs + MST_STATUS0);
1335 !(status0 & MST_STATUS0_IBIR_EMP);
1336 status0 = readl(master->regs + MST_STATUS0)) {
1337 u32 ibir = readl(master->regs + IBIR);
1338
1339 switch (IBIR_TYPE(ibir)) {
1340 case IBIR_TYPE_IBI:
1341 cdns_i3c_master_handle_ibi(master, ibir);
1342 break;
1343
1344 case IBIR_TYPE_HJ:
1345 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1346 queue_work(master->base.wq, &master->hj_work);
1347 break;
1348
1349 case IBIR_TYPE_MR:
1350 WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
1351 default:
1352 break;
1353 }
1354 }
1355}
1356
1357static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data)
1358{
1359 struct cdns_i3c_master *master = data;
1360 u32 status;
1361
1362 status = readl(master->regs + MST_ISR);
1363 if (!(status & readl(master->regs + MST_IMR)))
1364 return IRQ_NONE;
1365
1366 spin_lock(&master->xferqueue.lock);
1367 cdns_i3c_master_end_xfer_locked(master, status);
1368 spin_unlock(&master->xferqueue.lock);
1369
1370 if (status & MST_INT_IBIR_THR)
1371 cnds_i3c_master_demux_ibis(master);
1372
1373 return IRQ_HANDLED;
1374}
1375
1376static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1377{
1378 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1379 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1380 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1381 unsigned long flags;
1382 u32 sirmap;
1383 int ret;
1384
1385 ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
1386 I3C_CCC_EVENT_SIR);
1387 if (ret)
1388 return ret;
1389
1390 spin_lock_irqsave(&master->ibi.lock, flags);
1391 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1392 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1393 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1394 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1395 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1396 spin_unlock_irqrestore(&master->ibi.lock, flags);
1397
1398 return ret;
1399}
1400
1401static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1402{
1403 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1404 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1405 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1406 unsigned long flags;
1407 u32 sircfg, sirmap;
1408 int ret;
1409
1410 spin_lock_irqsave(&master->ibi.lock, flags);
1411 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1412 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1413 sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) |
1414 SIR_MAP_DEV_DA(dev->info.dyn_addr) |
1415 SIR_MAP_DEV_PL(dev->info.max_ibi_len) |
1416 SIR_MAP_DEV_ACK;
1417
1418 if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM)
1419 sircfg |= SIR_MAP_DEV_SLOW;
1420
1421 sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg);
1422 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1423 spin_unlock_irqrestore(&master->ibi.lock, flags);
1424
1425 ret = i3c_master_enec_locked(m, dev->info.dyn_addr,
1426 I3C_CCC_EVENT_SIR);
1427 if (ret) {
1428 spin_lock_irqsave(&master->ibi.lock, flags);
1429 sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
1430 sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
1431 sirmap |= SIR_MAP_DEV_CONF(data->ibi,
1432 SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
1433 writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
1434 spin_unlock_irqrestore(&master->ibi.lock, flags);
1435 }
1436
1437 return ret;
1438}
1439
1440static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1441 const struct i3c_ibi_setup *req)
1442{
1443 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1444 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1445 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1446 unsigned long flags;
1447 unsigned int i;
1448
1449 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1450 if (IS_ERR(data->ibi_pool))
1451 return PTR_ERR(data->ibi_pool);
1452
1453 spin_lock_irqsave(&master->ibi.lock, flags);
1454 for (i = 0; i < master->ibi.num_slots; i++) {
1455 if (!master->ibi.slots[i]) {
1456 data->ibi = i;
1457 master->ibi.slots[i] = dev;
1458 break;
1459 }
1460 }
1461 spin_unlock_irqrestore(&master->ibi.lock, flags);
1462
1463 if (i < master->ibi.num_slots)
1464 return 0;
1465
1466 i3c_generic_ibi_free_pool(data->ibi_pool);
1467 data->ibi_pool = NULL;
1468
1469 return -ENOSPC;
1470}
1471
1472static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1473{
1474 struct i3c_master_controller *m = i3c_dev_get_master(dev);
1475 struct cdns_i3c_master *master = to_cdns_i3c_master(m);
1476 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&master->ibi.lock, flags);
1480 master->ibi.slots[data->ibi] = NULL;
1481 data->ibi = -1;
1482 spin_unlock_irqrestore(&master->ibi.lock, flags);
1483
1484 i3c_generic_ibi_free_pool(data->ibi_pool);
1485}
1486
1487static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1488 struct i3c_ibi_slot *slot)
1489{
1490 struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1491
1492 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1493}
1494
1495static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
1496 .bus_init = cdns_i3c_master_bus_init,
1497 .bus_cleanup = cdns_i3c_master_bus_cleanup,
1498 .do_daa = cdns_i3c_master_do_daa,
1499 .attach_i3c_dev = cdns_i3c_master_attach_i3c_dev,
1500 .reattach_i3c_dev = cdns_i3c_master_reattach_i3c_dev,
1501 .detach_i3c_dev = cdns_i3c_master_detach_i3c_dev,
1502 .attach_i2c_dev = cdns_i3c_master_attach_i2c_dev,
1503 .detach_i2c_dev = cdns_i3c_master_detach_i2c_dev,
1504 .supports_ccc_cmd = cdns_i3c_master_supports_ccc_cmd,
1505 .send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
1506 .priv_xfers = cdns_i3c_master_priv_xfers,
1507 .i2c_xfers = cdns_i3c_master_i2c_xfers,
1508 .enable_ibi = cdns_i3c_master_enable_ibi,
1509 .disable_ibi = cdns_i3c_master_disable_ibi,
1510 .request_ibi = cdns_i3c_master_request_ibi,
1511 .free_ibi = cdns_i3c_master_free_ibi,
1512 .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot,
1513};
1514
1515static void cdns_i3c_master_hj(struct work_struct *work)
1516{
1517 struct cdns_i3c_master *master = container_of(work,
1518 struct cdns_i3c_master,
1519 hj_work);
1520
1521 i3c_master_do_daa(&master->base);
1522}
1523
1524static int cdns_i3c_master_probe(struct platform_device *pdev)
1525{
1526 struct cdns_i3c_master *master;
1527 struct resource *res;
1528 int ret, irq;
1529 u32 val;
1530
1531 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1532 if (!master)
1533 return -ENOMEM;
1534
1535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536 master->regs = devm_ioremap_resource(&pdev->dev, res);
1537 if (IS_ERR(master->regs))
1538 return PTR_ERR(master->regs);
1539
1540 master->pclk = devm_clk_get(&pdev->dev, "pclk");
1541 if (IS_ERR(master->pclk))
1542 return PTR_ERR(master->pclk);
1543
1544 master->sysclk = devm_clk_get(&pdev->dev, "sysclk");
1545 if (IS_ERR(master->sysclk))
1546 return PTR_ERR(master->sysclk);
1547
1548 irq = platform_get_irq(pdev, 0);
1549 if (irq < 0)
1550 return irq;
1551
1552 ret = clk_prepare_enable(master->pclk);
1553 if (ret)
1554 return ret;
1555
1556 ret = clk_prepare_enable(master->sysclk);
1557 if (ret)
1558 goto err_disable_pclk;
1559
1560 if (readl(master->regs + DEV_ID) != DEV_ID_I3C_MASTER) {
1561 ret = -EINVAL;
1562 goto err_disable_sysclk;
1563 }
1564
1565 spin_lock_init(&master->xferqueue.lock);
1566 INIT_LIST_HEAD(&master->xferqueue.list);
1567
1568 INIT_WORK(&master->hj_work, cdns_i3c_master_hj);
1569 writel(0xffffffff, master->regs + MST_IDR);
1570 writel(0xffffffff, master->regs + SLV_IDR);
1571 ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0,
1572 dev_name(&pdev->dev), master);
1573 if (ret)
1574 goto err_disable_sysclk;
1575
1576 platform_set_drvdata(pdev, master);
1577
1578 val = readl(master->regs + CONF_STATUS0);
1579
1580 /* Device ID0 is reserved to describe this master. */
1581 master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
1582 master->free_rr_slots = GENMASK(master->maxdevs, 1);
1583
1584 val = readl(master->regs + CONF_STATUS1);
1585 master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
1586 master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
1587 master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
1588 master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
1589 master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
1590
1591 spin_lock_init(&master->ibi.lock);
1592 master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
1593 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1594 sizeof(*master->ibi.slots),
1595 GFP_KERNEL);
1596 if (!master->ibi.slots)
1597 goto err_disable_sysclk;
1598
1599 writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
1600 writel(MST_INT_IBIR_THR, master->regs + MST_IER);
1601 writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
1602
1603 ret = i3c_master_register(&master->base, &pdev->dev,
1604 &cdns_i3c_master_ops, false);
1605 if (ret)
1606 goto err_disable_sysclk;
1607
1608 return 0;
1609
1610err_disable_sysclk:
1611 clk_disable_unprepare(master->sysclk);
1612
1613err_disable_pclk:
1614 clk_disable_unprepare(master->pclk);
1615
1616 return ret;
1617}
1618
1619static int cdns_i3c_master_remove(struct platform_device *pdev)
1620{
1621 struct cdns_i3c_master *master = platform_get_drvdata(pdev);
1622 int ret;
1623
1624 ret = i3c_master_unregister(&master->base);
1625 if (ret)
1626 return ret;
1627
1628 clk_disable_unprepare(master->sysclk);
1629 clk_disable_unprepare(master->pclk);
1630
1631 return 0;
1632}
1633
1634static const struct of_device_id cdns_i3c_master_of_ids[] = {
1635 { .compatible = "cdns,i3c-master" },
1636 { /* sentinel */ },
1637};
1638
1639static struct platform_driver cdns_i3c_master = {
1640 .probe = cdns_i3c_master_probe,
1641 .remove = cdns_i3c_master_remove,
1642 .driver = {
1643 .name = "cdns-i3c-master",
1644 .of_match_table = cdns_i3c_master_of_ids,
1645 },
1646};
1647module_platform_driver(cdns_i3c_master);
1648
1649MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1650MODULE_DESCRIPTION("Cadence I3C master driver");
1651MODULE_LICENSE("GPL v2");
1652MODULE_ALIAS("platform:cdns-i3c-master");