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1/*
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33#include <linux/compat.h>
34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
37#include <linux/mmu_notifier.h>
38#include <linux/pci.h>
39
40#include <drm/drm_aperture.h>
41#include <drm/drm_crtc_helper.h>
42#include <drm/drm_drv.h>
43#include <drm/drm_fb_helper.h>
44#include <drm/drm_file.h>
45#include <drm/drm_gem.h>
46#include <drm/drm_ioctl.h>
47#include <drm/drm_pciids.h>
48#include <drm/drm_probe_helper.h>
49#include <drm/drm_vblank.h>
50#include <drm/radeon_drm.h>
51
52#include "radeon_drv.h"
53#include "radeon.h"
54#include "radeon_kms.h"
55#include "radeon_ttm.h"
56#include "radeon_device.h"
57#include "radeon_prime.h"
58
59/*
60 * KMS wrapper.
61 * - 2.0.0 - initial interface
62 * - 2.1.0 - add square tiling interface
63 * - 2.2.0 - add r6xx/r7xx const buffer support
64 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
65 * - 2.4.0 - add crtc id query
66 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
67 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
68 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
69 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
70 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
71 * 2.10.0 - fusion 2D tiling
72 * 2.11.0 - backend map, initial compute support for the CS checker
73 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
74 * 2.13.0 - virtual memory support, streamout
75 * 2.14.0 - add evergreen tiling informations
76 * 2.15.0 - add max_pipes query
77 * 2.16.0 - fix evergreen 2D tiled surface calculation
78 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
79 * 2.18.0 - r600-eg: allow "invalid" DB formats
80 * 2.19.0 - r600-eg: MSAA textures
81 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
82 * 2.21.0 - r600-r700: FMASK and CMASK
83 * 2.22.0 - r600 only: RESOLVE_BOX allowed
84 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
85 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
86 * 2.25.0 - eg+: new info request for num SE and num SH
87 * 2.26.0 - r600-eg: fix htile size computation
88 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
89 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
90 * 2.29.0 - R500 FP16 color clear registers
91 * 2.30.0 - fix for FMASK texturing
92 * 2.31.0 - Add fastfb support for rs690
93 * 2.32.0 - new info request for rings working
94 * 2.33.0 - Add SI tiling mode array query
95 * 2.34.0 - Add CIK tiling mode array query
96 * 2.35.0 - Add CIK macrotile mode array query
97 * 2.36.0 - Fix CIK DCE tiling setup
98 * 2.37.0 - allow GS ring setup on r6xx/r7xx
99 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
100 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
101 * 2.39.0 - Add INFO query for number of active CUs
102 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
103 * CS to GPU on >= r600
104 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
105 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
106 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
107 * 2.44.0 - SET_APPEND_CNT packet3 support
108 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
109 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
110 * 2.47.0 - Add UVD_NO_OP register support
111 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
112 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
113 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
114 */
115#define KMS_DRIVER_MAJOR 2
116#define KMS_DRIVER_MINOR 50
117#define KMS_DRIVER_PATCHLEVEL 0
118int radeon_suspend_kms(struct drm_device *dev, bool suspend,
119 bool fbcon, bool freeze);
120int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
121extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
122 unsigned int flags, int *vpos, int *hpos,
123 ktime_t *stime, ktime_t *etime,
124 const struct drm_display_mode *mode);
125extern bool radeon_is_px(struct drm_device *dev);
126int radeon_mode_dumb_mmap(struct drm_file *filp,
127 struct drm_device *dev,
128 uint32_t handle, uint64_t *offset_p);
129int radeon_mode_dumb_create(struct drm_file *file_priv,
130 struct drm_device *dev,
131 struct drm_mode_create_dumb *args);
132
133/* atpx handler */
134#if defined(CONFIG_VGA_SWITCHEROO)
135void radeon_register_atpx_handler(void);
136void radeon_unregister_atpx_handler(void);
137bool radeon_has_atpx_dgpu_power_cntl(void);
138bool radeon_is_atpx_hybrid(void);
139#else
140static inline void radeon_register_atpx_handler(void) {}
141static inline void radeon_unregister_atpx_handler(void) {}
142static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
143static inline bool radeon_is_atpx_hybrid(void) { return false; }
144#endif
145
146int radeon_no_wb;
147int radeon_modeset = -1;
148int radeon_dynclks = -1;
149int radeon_r4xx_atom = 0;
150int radeon_agpmode = -1;
151int radeon_vram_limit = 0;
152int radeon_gart_size = -1; /* auto */
153int radeon_benchmarking = 0;
154int radeon_testing = 0;
155int radeon_connector_table = 0;
156int radeon_tv = 1;
157int radeon_audio = -1;
158int radeon_disp_priority = 0;
159int radeon_hw_i2c = 0;
160int radeon_pcie_gen2 = -1;
161int radeon_msi = -1;
162int radeon_lockup_timeout = 10000;
163int radeon_fastfb = 0;
164int radeon_dpm = -1;
165int radeon_aspm = -1;
166int radeon_runtime_pm = -1;
167int radeon_hard_reset = 0;
168int radeon_vm_size = 8;
169int radeon_vm_block_size = -1;
170int radeon_deep_color = 0;
171int radeon_use_pflipirq = 2;
172int radeon_bapm = -1;
173int radeon_backlight = -1;
174int radeon_auxch = -1;
175int radeon_uvd = 1;
176int radeon_vce = 1;
177
178MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
179module_param_named(no_wb, radeon_no_wb, int, 0444);
180
181MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
182module_param_named(modeset, radeon_modeset, int, 0400);
183
184MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
185module_param_named(dynclks, radeon_dynclks, int, 0444);
186
187MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
188module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
189
190MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
191module_param_named(vramlimit, radeon_vram_limit, int, 0600);
192
193MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
194module_param_named(agpmode, radeon_agpmode, int, 0444);
195
196MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
197module_param_named(gartsize, radeon_gart_size, int, 0600);
198
199MODULE_PARM_DESC(benchmark, "Run benchmark");
200module_param_named(benchmark, radeon_benchmarking, int, 0444);
201
202MODULE_PARM_DESC(test, "Run tests");
203module_param_named(test, radeon_testing, int, 0444);
204
205MODULE_PARM_DESC(connector_table, "Force connector table");
206module_param_named(connector_table, radeon_connector_table, int, 0444);
207
208MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
209module_param_named(tv, radeon_tv, int, 0444);
210
211MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
212module_param_named(audio, radeon_audio, int, 0444);
213
214MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
215module_param_named(disp_priority, radeon_disp_priority, int, 0444);
216
217MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
218module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
219
220MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
221module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
222
223MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
224module_param_named(msi, radeon_msi, int, 0444);
225
226MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
227module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
228
229MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
230module_param_named(fastfb, radeon_fastfb, int, 0444);
231
232MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
233module_param_named(dpm, radeon_dpm, int, 0444);
234
235MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
236module_param_named(aspm, radeon_aspm, int, 0444);
237
238MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
239module_param_named(runpm, radeon_runtime_pm, int, 0444);
240
241MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
242module_param_named(hard_reset, radeon_hard_reset, int, 0444);
243
244MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
245module_param_named(vm_size, radeon_vm_size, int, 0444);
246
247MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
248module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
249
250MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
251module_param_named(deep_color, radeon_deep_color, int, 0444);
252
253MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
254module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
255
256MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
257module_param_named(bapm, radeon_bapm, int, 0444);
258
259MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
260module_param_named(backlight, radeon_backlight, int, 0444);
261
262MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
263module_param_named(auxch, radeon_auxch, int, 0444);
264
265MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
266module_param_named(uvd, radeon_uvd, int, 0444);
267
268MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
269module_param_named(vce, radeon_vce, int, 0444);
270
271int radeon_si_support = 1;
272MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
273module_param_named(si_support, radeon_si_support, int, 0444);
274
275int radeon_cik_support = 1;
276MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
277module_param_named(cik_support, radeon_cik_support, int, 0444);
278
279static struct pci_device_id pciidlist[] = {
280 radeon_PCI_IDS
281};
282
283MODULE_DEVICE_TABLE(pci, pciidlist);
284
285static const struct drm_driver kms_driver;
286
287static int radeon_pci_probe(struct pci_dev *pdev,
288 const struct pci_device_id *ent)
289{
290 unsigned long flags = 0;
291 struct drm_device *dev;
292 int ret;
293
294 if (!ent)
295 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
296
297 flags = ent->driver_data;
298
299 if (!radeon_si_support) {
300 switch (flags & RADEON_FAMILY_MASK) {
301 case CHIP_TAHITI:
302 case CHIP_PITCAIRN:
303 case CHIP_VERDE:
304 case CHIP_OLAND:
305 case CHIP_HAINAN:
306 dev_info(&pdev->dev,
307 "SI support disabled by module param\n");
308 return -ENODEV;
309 }
310 }
311 if (!radeon_cik_support) {
312 switch (flags & RADEON_FAMILY_MASK) {
313 case CHIP_KAVERI:
314 case CHIP_BONAIRE:
315 case CHIP_HAWAII:
316 case CHIP_KABINI:
317 case CHIP_MULLINS:
318 dev_info(&pdev->dev,
319 "CIK support disabled by module param\n");
320 return -ENODEV;
321 }
322 }
323
324 if (vga_switcheroo_client_probe_defer(pdev))
325 return -EPROBE_DEFER;
326
327 /* Get rid of things like offb */
328 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver);
329 if (ret)
330 return ret;
331
332 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
333 if (IS_ERR(dev))
334 return PTR_ERR(dev);
335
336 ret = pci_enable_device(pdev);
337 if (ret)
338 goto err_free;
339
340 pci_set_drvdata(pdev, dev);
341
342 ret = drm_dev_register(dev, ent->driver_data);
343 if (ret)
344 goto err_agp;
345
346 return 0;
347
348err_agp:
349 pci_disable_device(pdev);
350err_free:
351 drm_dev_put(dev);
352 return ret;
353}
354
355static void
356radeon_pci_remove(struct pci_dev *pdev)
357{
358 struct drm_device *dev = pci_get_drvdata(pdev);
359
360 drm_put_dev(dev);
361}
362
363static void
364radeon_pci_shutdown(struct pci_dev *pdev)
365{
366 /* if we are running in a VM, make sure the device
367 * torn down properly on reboot/shutdown
368 */
369 if (radeon_device_is_virtual())
370 radeon_pci_remove(pdev);
371
372#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
373 /*
374 * Some adapters need to be suspended before a
375 * shutdown occurs in order to prevent an error
376 * during kexec, shutdown or reboot.
377 * Make this power and Loongson specific because
378 * it breaks some other boards.
379 */
380 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
381#endif
382}
383
384static int radeon_pmops_suspend(struct device *dev)
385{
386 struct drm_device *drm_dev = dev_get_drvdata(dev);
387 return radeon_suspend_kms(drm_dev, true, true, false);
388}
389
390static int radeon_pmops_resume(struct device *dev)
391{
392 struct drm_device *drm_dev = dev_get_drvdata(dev);
393
394 /* GPU comes up enabled by the bios on resume */
395 if (radeon_is_px(drm_dev)) {
396 pm_runtime_disable(dev);
397 pm_runtime_set_active(dev);
398 pm_runtime_enable(dev);
399 }
400
401 return radeon_resume_kms(drm_dev, true, true);
402}
403
404static int radeon_pmops_freeze(struct device *dev)
405{
406 struct drm_device *drm_dev = dev_get_drvdata(dev);
407 return radeon_suspend_kms(drm_dev, false, true, true);
408}
409
410static int radeon_pmops_thaw(struct device *dev)
411{
412 struct drm_device *drm_dev = dev_get_drvdata(dev);
413 return radeon_resume_kms(drm_dev, false, true);
414}
415
416static int radeon_pmops_runtime_suspend(struct device *dev)
417{
418 struct pci_dev *pdev = to_pci_dev(dev);
419 struct drm_device *drm_dev = pci_get_drvdata(pdev);
420
421 if (!radeon_is_px(drm_dev)) {
422 pm_runtime_forbid(dev);
423 return -EBUSY;
424 }
425
426 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
427 drm_kms_helper_poll_disable(drm_dev);
428
429 radeon_suspend_kms(drm_dev, false, false, false);
430 pci_save_state(pdev);
431 pci_disable_device(pdev);
432 pci_ignore_hotplug(pdev);
433 if (radeon_is_atpx_hybrid())
434 pci_set_power_state(pdev, PCI_D3cold);
435 else if (!radeon_has_atpx_dgpu_power_cntl())
436 pci_set_power_state(pdev, PCI_D3hot);
437 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
438
439 return 0;
440}
441
442static int radeon_pmops_runtime_resume(struct device *dev)
443{
444 struct pci_dev *pdev = to_pci_dev(dev);
445 struct drm_device *drm_dev = pci_get_drvdata(pdev);
446 int ret;
447
448 if (!radeon_is_px(drm_dev))
449 return -EINVAL;
450
451 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
452
453 if (radeon_is_atpx_hybrid() ||
454 !radeon_has_atpx_dgpu_power_cntl())
455 pci_set_power_state(pdev, PCI_D0);
456 pci_restore_state(pdev);
457 ret = pci_enable_device(pdev);
458 if (ret)
459 return ret;
460 pci_set_master(pdev);
461
462 ret = radeon_resume_kms(drm_dev, false, false);
463 drm_kms_helper_poll_enable(drm_dev);
464 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
465 return 0;
466}
467
468static int radeon_pmops_runtime_idle(struct device *dev)
469{
470 struct drm_device *drm_dev = dev_get_drvdata(dev);
471 struct drm_crtc *crtc;
472
473 if (!radeon_is_px(drm_dev)) {
474 pm_runtime_forbid(dev);
475 return -EBUSY;
476 }
477
478 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
479 if (crtc->enabled) {
480 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
481 return -EBUSY;
482 }
483 }
484
485 pm_runtime_mark_last_busy(dev);
486 pm_runtime_autosuspend(dev);
487 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
488 return 1;
489}
490
491long radeon_drm_ioctl(struct file *filp,
492 unsigned int cmd, unsigned long arg)
493{
494 struct drm_file *file_priv = filp->private_data;
495 struct drm_device *dev;
496 long ret;
497 dev = file_priv->minor->dev;
498 ret = pm_runtime_get_sync(dev->dev);
499 if (ret < 0) {
500 pm_runtime_put_autosuspend(dev->dev);
501 return ret;
502 }
503
504 ret = drm_ioctl(filp, cmd, arg);
505
506 pm_runtime_mark_last_busy(dev->dev);
507 pm_runtime_put_autosuspend(dev->dev);
508 return ret;
509}
510
511#ifdef CONFIG_COMPAT
512static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
513{
514 unsigned int nr = DRM_IOCTL_NR(cmd);
515
516 if (nr < DRM_COMMAND_BASE)
517 return drm_compat_ioctl(filp, cmd, arg);
518
519 return radeon_drm_ioctl(filp, cmd, arg);
520}
521#endif
522
523static const struct dev_pm_ops radeon_pm_ops = {
524 .suspend = radeon_pmops_suspend,
525 .resume = radeon_pmops_resume,
526 .freeze = radeon_pmops_freeze,
527 .thaw = radeon_pmops_thaw,
528 .poweroff = radeon_pmops_freeze,
529 .restore = radeon_pmops_resume,
530 .runtime_suspend = radeon_pmops_runtime_suspend,
531 .runtime_resume = radeon_pmops_runtime_resume,
532 .runtime_idle = radeon_pmops_runtime_idle,
533};
534
535static const struct file_operations radeon_driver_kms_fops = {
536 .owner = THIS_MODULE,
537 .open = drm_open,
538 .release = drm_release,
539 .unlocked_ioctl = radeon_drm_ioctl,
540 .mmap = drm_gem_mmap,
541 .poll = drm_poll,
542 .read = drm_read,
543#ifdef CONFIG_COMPAT
544 .compat_ioctl = radeon_kms_compat_ioctl,
545#endif
546};
547
548static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
549 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
550 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
551 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
552 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
553 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
554 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
555 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
556 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
557 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
558 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
559 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
560 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
561 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
562 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
563 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
564 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
565 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
566 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
567 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
568 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
569 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
570 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
571 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
572 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
573 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
574 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
575 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
576 /* KMS */
577 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
578 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
579 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
580 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
581 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
582 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
583 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
584 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
585 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
586 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
587 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
588 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
589 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
590 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
591 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
592};
593
594static const struct drm_driver kms_driver = {
595 .driver_features =
596 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
597 .load = radeon_driver_load_kms,
598 .open = radeon_driver_open_kms,
599 .postclose = radeon_driver_postclose_kms,
600 .lastclose = radeon_driver_lastclose_kms,
601 .unload = radeon_driver_unload_kms,
602 .ioctls = radeon_ioctls_kms,
603 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
604 .dumb_create = radeon_mode_dumb_create,
605 .dumb_map_offset = radeon_mode_dumb_mmap,
606 .fops = &radeon_driver_kms_fops,
607
608 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
609 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
610 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
611 .gem_prime_mmap = drm_gem_prime_mmap,
612
613 .name = DRIVER_NAME,
614 .desc = DRIVER_DESC,
615 .date = DRIVER_DATE,
616 .major = KMS_DRIVER_MAJOR,
617 .minor = KMS_DRIVER_MINOR,
618 .patchlevel = KMS_DRIVER_PATCHLEVEL,
619};
620
621static struct pci_driver radeon_kms_pci_driver = {
622 .name = DRIVER_NAME,
623 .id_table = pciidlist,
624 .probe = radeon_pci_probe,
625 .remove = radeon_pci_remove,
626 .shutdown = radeon_pci_shutdown,
627 .driver.pm = &radeon_pm_ops,
628};
629
630static int __init radeon_module_init(void)
631{
632 if (drm_firmware_drivers_only() && radeon_modeset == -1)
633 radeon_modeset = 0;
634
635 if (radeon_modeset == 0)
636 return -EINVAL;
637
638 DRM_INFO("radeon kernel modesetting enabled.\n");
639 radeon_register_atpx_handler();
640
641 return pci_register_driver(&radeon_kms_pci_driver);
642}
643
644static void __exit radeon_module_exit(void)
645{
646 pci_unregister_driver(&radeon_kms_pci_driver);
647 radeon_unregister_atpx_handler();
648 mmu_notifier_synchronize();
649}
650
651module_init(radeon_module_init);
652module_exit(radeon_module_exit);
653
654MODULE_AUTHOR(DRIVER_AUTHOR);
655MODULE_DESCRIPTION(DRIVER_DESC);
656MODULE_LICENSE("GPL and additional rights");
1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33#include <linux/compat.h>
34#include <linux/console.h>
35#include <linux/module.h>
36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
38#include <linux/mmu_notifier.h>
39
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_drv.h>
42#include <drm/drm_fb_helper.h>
43#include <drm/drm_file.h>
44#include <drm/drm_gem.h>
45#include <drm/drm_ioctl.h>
46#include <drm/drm_pci.h>
47#include <drm/drm_pciids.h>
48#include <drm/drm_probe_helper.h>
49#include <drm/drm_vblank.h>
50#include <drm/radeon_drm.h>
51
52#include "radeon_drv.h"
53
54/*
55 * KMS wrapper.
56 * - 2.0.0 - initial interface
57 * - 2.1.0 - add square tiling interface
58 * - 2.2.0 - add r6xx/r7xx const buffer support
59 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
60 * - 2.4.0 - add crtc id query
61 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
62 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
63 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
64 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
65 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
66 * 2.10.0 - fusion 2D tiling
67 * 2.11.0 - backend map, initial compute support for the CS checker
68 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
69 * 2.13.0 - virtual memory support, streamout
70 * 2.14.0 - add evergreen tiling informations
71 * 2.15.0 - add max_pipes query
72 * 2.16.0 - fix evergreen 2D tiled surface calculation
73 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
74 * 2.18.0 - r600-eg: allow "invalid" DB formats
75 * 2.19.0 - r600-eg: MSAA textures
76 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
77 * 2.21.0 - r600-r700: FMASK and CMASK
78 * 2.22.0 - r600 only: RESOLVE_BOX allowed
79 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
80 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
81 * 2.25.0 - eg+: new info request for num SE and num SH
82 * 2.26.0 - r600-eg: fix htile size computation
83 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
84 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
85 * 2.29.0 - R500 FP16 color clear registers
86 * 2.30.0 - fix for FMASK texturing
87 * 2.31.0 - Add fastfb support for rs690
88 * 2.32.0 - new info request for rings working
89 * 2.33.0 - Add SI tiling mode array query
90 * 2.34.0 - Add CIK tiling mode array query
91 * 2.35.0 - Add CIK macrotile mode array query
92 * 2.36.0 - Fix CIK DCE tiling setup
93 * 2.37.0 - allow GS ring setup on r6xx/r7xx
94 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
95 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
96 * 2.39.0 - Add INFO query for number of active CUs
97 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
98 * CS to GPU on >= r600
99 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
100 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
101 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
102 * 2.44.0 - SET_APPEND_CNT packet3 support
103 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
104 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
105 * 2.47.0 - Add UVD_NO_OP register support
106 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
107 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
108 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
109 */
110#define KMS_DRIVER_MAJOR 2
111#define KMS_DRIVER_MINOR 50
112#define KMS_DRIVER_PATCHLEVEL 0
113int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
114void radeon_driver_unload_kms(struct drm_device *dev);
115void radeon_driver_lastclose_kms(struct drm_device *dev);
116int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
117void radeon_driver_postclose_kms(struct drm_device *dev,
118 struct drm_file *file_priv);
119int radeon_suspend_kms(struct drm_device *dev, bool suspend,
120 bool fbcon, bool freeze);
121int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
122u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
123int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
124void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
125void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
126int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
127void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
128irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
129void radeon_gem_object_free(struct drm_gem_object *obj);
130int radeon_gem_object_open(struct drm_gem_object *obj,
131 struct drm_file *file_priv);
132void radeon_gem_object_close(struct drm_gem_object *obj,
133 struct drm_file *file_priv);
134struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj,
135 int flags);
136extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
137 unsigned int flags, int *vpos, int *hpos,
138 ktime_t *stime, ktime_t *etime,
139 const struct drm_display_mode *mode);
140extern bool radeon_is_px(struct drm_device *dev);
141extern const struct drm_ioctl_desc radeon_ioctls_kms[];
142extern int radeon_max_kms_ioctl;
143int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
144int radeon_mode_dumb_mmap(struct drm_file *filp,
145 struct drm_device *dev,
146 uint32_t handle, uint64_t *offset_p);
147int radeon_mode_dumb_create(struct drm_file *file_priv,
148 struct drm_device *dev,
149 struct drm_mode_create_dumb *args);
150struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
151struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
152 struct dma_buf_attachment *,
153 struct sg_table *sg);
154int radeon_gem_prime_pin(struct drm_gem_object *obj);
155void radeon_gem_prime_unpin(struct drm_gem_object *obj);
156void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
157void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
158
159/* atpx handler */
160#if defined(CONFIG_VGA_SWITCHEROO)
161void radeon_register_atpx_handler(void);
162void radeon_unregister_atpx_handler(void);
163bool radeon_has_atpx_dgpu_power_cntl(void);
164bool radeon_is_atpx_hybrid(void);
165#else
166static inline void radeon_register_atpx_handler(void) {}
167static inline void radeon_unregister_atpx_handler(void) {}
168static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
169static inline bool radeon_is_atpx_hybrid(void) { return false; }
170#endif
171
172int radeon_no_wb;
173int radeon_modeset = -1;
174int radeon_dynclks = -1;
175int radeon_r4xx_atom = 0;
176#ifdef __powerpc__
177/* Default to PCI on PowerPC (fdo #95017) */
178int radeon_agpmode = -1;
179#else
180int radeon_agpmode = 0;
181#endif
182int radeon_vram_limit = 0;
183int radeon_gart_size = -1; /* auto */
184int radeon_benchmarking = 0;
185int radeon_testing = 0;
186int radeon_connector_table = 0;
187int radeon_tv = 1;
188int radeon_audio = -1;
189int radeon_disp_priority = 0;
190int radeon_hw_i2c = 0;
191int radeon_pcie_gen2 = -1;
192int radeon_msi = -1;
193int radeon_lockup_timeout = 10000;
194int radeon_fastfb = 0;
195int radeon_dpm = -1;
196int radeon_aspm = -1;
197int radeon_runtime_pm = -1;
198int radeon_hard_reset = 0;
199int radeon_vm_size = 8;
200int radeon_vm_block_size = -1;
201int radeon_deep_color = 0;
202int radeon_use_pflipirq = 2;
203int radeon_bapm = -1;
204int radeon_backlight = -1;
205int radeon_auxch = -1;
206int radeon_mst = 0;
207int radeon_uvd = 1;
208int radeon_vce = 1;
209
210MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
211module_param_named(no_wb, radeon_no_wb, int, 0444);
212
213MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
214module_param_named(modeset, radeon_modeset, int, 0400);
215
216MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
217module_param_named(dynclks, radeon_dynclks, int, 0444);
218
219MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
220module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
221
222MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
223module_param_named(vramlimit, radeon_vram_limit, int, 0600);
224
225MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
226module_param_named(agpmode, radeon_agpmode, int, 0444);
227
228MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
229module_param_named(gartsize, radeon_gart_size, int, 0600);
230
231MODULE_PARM_DESC(benchmark, "Run benchmark");
232module_param_named(benchmark, radeon_benchmarking, int, 0444);
233
234MODULE_PARM_DESC(test, "Run tests");
235module_param_named(test, radeon_testing, int, 0444);
236
237MODULE_PARM_DESC(connector_table, "Force connector table");
238module_param_named(connector_table, radeon_connector_table, int, 0444);
239
240MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
241module_param_named(tv, radeon_tv, int, 0444);
242
243MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
244module_param_named(audio, radeon_audio, int, 0444);
245
246MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
247module_param_named(disp_priority, radeon_disp_priority, int, 0444);
248
249MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
250module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
251
252MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
253module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
254
255MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
256module_param_named(msi, radeon_msi, int, 0444);
257
258MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
259module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
260
261MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
262module_param_named(fastfb, radeon_fastfb, int, 0444);
263
264MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
265module_param_named(dpm, radeon_dpm, int, 0444);
266
267MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
268module_param_named(aspm, radeon_aspm, int, 0444);
269
270MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
271module_param_named(runpm, radeon_runtime_pm, int, 0444);
272
273MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
274module_param_named(hard_reset, radeon_hard_reset, int, 0444);
275
276MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
277module_param_named(vm_size, radeon_vm_size, int, 0444);
278
279MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
280module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
281
282MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
283module_param_named(deep_color, radeon_deep_color, int, 0444);
284
285MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
286module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
287
288MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
289module_param_named(bapm, radeon_bapm, int, 0444);
290
291MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
292module_param_named(backlight, radeon_backlight, int, 0444);
293
294MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
295module_param_named(auxch, radeon_auxch, int, 0444);
296
297MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
298module_param_named(mst, radeon_mst, int, 0444);
299
300MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
301module_param_named(uvd, radeon_uvd, int, 0444);
302
303MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
304module_param_named(vce, radeon_vce, int, 0444);
305
306int radeon_si_support = 1;
307MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
308module_param_named(si_support, radeon_si_support, int, 0444);
309
310int radeon_cik_support = 1;
311MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
312module_param_named(cik_support, radeon_cik_support, int, 0444);
313
314static struct pci_device_id pciidlist[] = {
315 radeon_PCI_IDS
316};
317
318MODULE_DEVICE_TABLE(pci, pciidlist);
319
320static struct drm_driver kms_driver;
321
322bool radeon_device_is_virtual(void);
323
324static int radeon_pci_probe(struct pci_dev *pdev,
325 const struct pci_device_id *ent)
326{
327 unsigned long flags = 0;
328 int ret;
329
330 if (!ent)
331 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
332
333 flags = ent->driver_data;
334
335 if (!radeon_si_support) {
336 switch (flags & RADEON_FAMILY_MASK) {
337 case CHIP_TAHITI:
338 case CHIP_PITCAIRN:
339 case CHIP_VERDE:
340 case CHIP_OLAND:
341 case CHIP_HAINAN:
342 dev_info(&pdev->dev,
343 "SI support disabled by module param\n");
344 return -ENODEV;
345 }
346 }
347 if (!radeon_cik_support) {
348 switch (flags & RADEON_FAMILY_MASK) {
349 case CHIP_KAVERI:
350 case CHIP_BONAIRE:
351 case CHIP_HAWAII:
352 case CHIP_KABINI:
353 case CHIP_MULLINS:
354 dev_info(&pdev->dev,
355 "CIK support disabled by module param\n");
356 return -ENODEV;
357 }
358 }
359
360 if (vga_switcheroo_client_probe_defer(pdev))
361 return -EPROBE_DEFER;
362
363 /* Get rid of things like offb */
364 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "radeondrmfb");
365 if (ret)
366 return ret;
367
368 return drm_get_pci_dev(pdev, ent, &kms_driver);
369}
370
371static void
372radeon_pci_remove(struct pci_dev *pdev)
373{
374 struct drm_device *dev = pci_get_drvdata(pdev);
375
376 drm_put_dev(dev);
377}
378
379static void
380radeon_pci_shutdown(struct pci_dev *pdev)
381{
382#ifdef CONFIG_PPC64
383 struct drm_device *ddev = pci_get_drvdata(pdev);
384#endif
385
386 /* if we are running in a VM, make sure the device
387 * torn down properly on reboot/shutdown
388 */
389 if (radeon_device_is_virtual())
390 radeon_pci_remove(pdev);
391
392#ifdef CONFIG_PPC64
393 /* Some adapters need to be suspended before a
394 * shutdown occurs in order to prevent an error
395 * during kexec.
396 * Make this power specific becauase it breaks
397 * some non-power boards.
398 */
399 radeon_suspend_kms(ddev, true, true, false);
400#endif
401}
402
403static int radeon_pmops_suspend(struct device *dev)
404{
405 struct drm_device *drm_dev = dev_get_drvdata(dev);
406 return radeon_suspend_kms(drm_dev, true, true, false);
407}
408
409static int radeon_pmops_resume(struct device *dev)
410{
411 struct drm_device *drm_dev = dev_get_drvdata(dev);
412
413 /* GPU comes up enabled by the bios on resume */
414 if (radeon_is_px(drm_dev)) {
415 pm_runtime_disable(dev);
416 pm_runtime_set_active(dev);
417 pm_runtime_enable(dev);
418 }
419
420 return radeon_resume_kms(drm_dev, true, true);
421}
422
423static int radeon_pmops_freeze(struct device *dev)
424{
425 struct drm_device *drm_dev = dev_get_drvdata(dev);
426 return radeon_suspend_kms(drm_dev, false, true, true);
427}
428
429static int radeon_pmops_thaw(struct device *dev)
430{
431 struct drm_device *drm_dev = dev_get_drvdata(dev);
432 return radeon_resume_kms(drm_dev, false, true);
433}
434
435static int radeon_pmops_runtime_suspend(struct device *dev)
436{
437 struct pci_dev *pdev = to_pci_dev(dev);
438 struct drm_device *drm_dev = pci_get_drvdata(pdev);
439 int ret;
440
441 if (!radeon_is_px(drm_dev)) {
442 pm_runtime_forbid(dev);
443 return -EBUSY;
444 }
445
446 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
447 drm_kms_helper_poll_disable(drm_dev);
448
449 ret = radeon_suspend_kms(drm_dev, false, false, false);
450 pci_save_state(pdev);
451 pci_disable_device(pdev);
452 pci_ignore_hotplug(pdev);
453 if (radeon_is_atpx_hybrid())
454 pci_set_power_state(pdev, PCI_D3cold);
455 else if (!radeon_has_atpx_dgpu_power_cntl())
456 pci_set_power_state(pdev, PCI_D3hot);
457 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
458
459 return 0;
460}
461
462static int radeon_pmops_runtime_resume(struct device *dev)
463{
464 struct pci_dev *pdev = to_pci_dev(dev);
465 struct drm_device *drm_dev = pci_get_drvdata(pdev);
466 int ret;
467
468 if (!radeon_is_px(drm_dev))
469 return -EINVAL;
470
471 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
472
473 if (radeon_is_atpx_hybrid() ||
474 !radeon_has_atpx_dgpu_power_cntl())
475 pci_set_power_state(pdev, PCI_D0);
476 pci_restore_state(pdev);
477 ret = pci_enable_device(pdev);
478 if (ret)
479 return ret;
480 pci_set_master(pdev);
481
482 ret = radeon_resume_kms(drm_dev, false, false);
483 drm_kms_helper_poll_enable(drm_dev);
484 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
485 return 0;
486}
487
488static int radeon_pmops_runtime_idle(struct device *dev)
489{
490 struct drm_device *drm_dev = dev_get_drvdata(dev);
491 struct drm_crtc *crtc;
492
493 if (!radeon_is_px(drm_dev)) {
494 pm_runtime_forbid(dev);
495 return -EBUSY;
496 }
497
498 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
499 if (crtc->enabled) {
500 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
501 return -EBUSY;
502 }
503 }
504
505 pm_runtime_mark_last_busy(dev);
506 pm_runtime_autosuspend(dev);
507 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
508 return 1;
509}
510
511long radeon_drm_ioctl(struct file *filp,
512 unsigned int cmd, unsigned long arg)
513{
514 struct drm_file *file_priv = filp->private_data;
515 struct drm_device *dev;
516 long ret;
517 dev = file_priv->minor->dev;
518 ret = pm_runtime_get_sync(dev->dev);
519 if (ret < 0)
520 return ret;
521
522 ret = drm_ioctl(filp, cmd, arg);
523
524 pm_runtime_mark_last_busy(dev->dev);
525 pm_runtime_put_autosuspend(dev->dev);
526 return ret;
527}
528
529#ifdef CONFIG_COMPAT
530static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
531{
532 unsigned int nr = DRM_IOCTL_NR(cmd);
533 int ret;
534
535 if (nr < DRM_COMMAND_BASE)
536 return drm_compat_ioctl(filp, cmd, arg);
537
538 ret = radeon_drm_ioctl(filp, cmd, arg);
539
540 return ret;
541}
542#endif
543
544static const struct dev_pm_ops radeon_pm_ops = {
545 .suspend = radeon_pmops_suspend,
546 .resume = radeon_pmops_resume,
547 .freeze = radeon_pmops_freeze,
548 .thaw = radeon_pmops_thaw,
549 .poweroff = radeon_pmops_freeze,
550 .restore = radeon_pmops_resume,
551 .runtime_suspend = radeon_pmops_runtime_suspend,
552 .runtime_resume = radeon_pmops_runtime_resume,
553 .runtime_idle = radeon_pmops_runtime_idle,
554};
555
556static const struct file_operations radeon_driver_kms_fops = {
557 .owner = THIS_MODULE,
558 .open = drm_open,
559 .release = drm_release,
560 .unlocked_ioctl = radeon_drm_ioctl,
561 .mmap = radeon_mmap,
562 .poll = drm_poll,
563 .read = drm_read,
564#ifdef CONFIG_COMPAT
565 .compat_ioctl = radeon_kms_compat_ioctl,
566#endif
567};
568
569static bool
570radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
571 bool in_vblank_irq, int *vpos, int *hpos,
572 ktime_t *stime, ktime_t *etime,
573 const struct drm_display_mode *mode)
574{
575 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
576 stime, etime, mode);
577}
578
579static struct drm_driver kms_driver = {
580 .driver_features =
581 DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER,
582 .load = radeon_driver_load_kms,
583 .open = radeon_driver_open_kms,
584 .postclose = radeon_driver_postclose_kms,
585 .lastclose = radeon_driver_lastclose_kms,
586 .unload = radeon_driver_unload_kms,
587 .get_vblank_counter = radeon_get_vblank_counter_kms,
588 .enable_vblank = radeon_enable_vblank_kms,
589 .disable_vblank = radeon_disable_vblank_kms,
590 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
591 .get_scanout_position = radeon_get_crtc_scanout_position,
592 .irq_preinstall = radeon_driver_irq_preinstall_kms,
593 .irq_postinstall = radeon_driver_irq_postinstall_kms,
594 .irq_uninstall = radeon_driver_irq_uninstall_kms,
595 .irq_handler = radeon_driver_irq_handler_kms,
596 .ioctls = radeon_ioctls_kms,
597 .gem_free_object_unlocked = radeon_gem_object_free,
598 .gem_open_object = radeon_gem_object_open,
599 .gem_close_object = radeon_gem_object_close,
600 .dumb_create = radeon_mode_dumb_create,
601 .dumb_map_offset = radeon_mode_dumb_mmap,
602 .fops = &radeon_driver_kms_fops,
603
604 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
605 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
606 .gem_prime_export = radeon_gem_prime_export,
607 .gem_prime_pin = radeon_gem_prime_pin,
608 .gem_prime_unpin = radeon_gem_prime_unpin,
609 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
610 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
611 .gem_prime_vmap = radeon_gem_prime_vmap,
612 .gem_prime_vunmap = radeon_gem_prime_vunmap,
613
614 .name = DRIVER_NAME,
615 .desc = DRIVER_DESC,
616 .date = DRIVER_DATE,
617 .major = KMS_DRIVER_MAJOR,
618 .minor = KMS_DRIVER_MINOR,
619 .patchlevel = KMS_DRIVER_PATCHLEVEL,
620};
621
622static struct drm_driver *driver;
623static struct pci_driver *pdriver;
624
625static struct pci_driver radeon_kms_pci_driver = {
626 .name = DRIVER_NAME,
627 .id_table = pciidlist,
628 .probe = radeon_pci_probe,
629 .remove = radeon_pci_remove,
630 .shutdown = radeon_pci_shutdown,
631 .driver.pm = &radeon_pm_ops,
632};
633
634static int __init radeon_init(void)
635{
636 if (vgacon_text_force() && radeon_modeset == -1) {
637 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
638 radeon_modeset = 0;
639 }
640 /* set to modesetting by default if not nomodeset */
641 if (radeon_modeset == -1)
642 radeon_modeset = 1;
643
644 if (radeon_modeset == 1) {
645 DRM_INFO("radeon kernel modesetting enabled.\n");
646 driver = &kms_driver;
647 pdriver = &radeon_kms_pci_driver;
648 driver->driver_features |= DRIVER_MODESET;
649 driver->num_ioctls = radeon_max_kms_ioctl;
650 radeon_register_atpx_handler();
651
652 } else {
653 DRM_ERROR("No UMS support in radeon module!\n");
654 return -EINVAL;
655 }
656
657 return pci_register_driver(pdriver);
658}
659
660static void __exit radeon_exit(void)
661{
662 pci_unregister_driver(pdriver);
663 radeon_unregister_atpx_handler();
664 mmu_notifier_synchronize();
665}
666
667module_init(radeon_init);
668module_exit(radeon_exit);
669
670MODULE_AUTHOR(DRIVER_AUTHOR);
671MODULE_DESCRIPTION(DRIVER_DESC);
672MODULE_LICENSE("GPL and additional rights");