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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/**
27 * This file defines external dependencies of Display Core.
28 */
29
30#ifndef __DM_SERVICES_H__
31
32#define __DM_SERVICES_H__
33
34/* TODO: remove when DC is complete. */
35#include "dm_services_types.h"
36#include "logger_interface.h"
37#include "link_service_types.h"
38
39#undef DEPRECATED
40
41struct dmub_srv;
42struct dc_dmub_srv;
43
44irq_handler_idx dm_register_interrupt(
45 struct dc_context *ctx,
46 struct dc_interrupt_params *int_params,
47 interrupt_handler ih,
48 void *handler_args);
49
50/*
51 *
52 * GPU registers access
53 *
54 */
55uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
56 const char *func_name);
57
58/* enable for debugging new code, this adds 50k to the driver size. */
59/* #define DM_CHECK_ADDR_0 */
60
61void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
62 uint32_t value, const char *func_name);
63
64#define dm_read_reg(ctx, address) \
65 dm_read_reg_func(ctx, address, __func__)
66
67#define dm_write_reg(ctx, address, value) \
68 dm_write_reg_func(ctx, address, value, __func__)
69
70static inline uint32_t dm_read_index_reg(
71 const struct dc_context *ctx,
72 enum cgs_ind_reg addr_space,
73 uint32_t index)
74{
75 return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
76}
77
78static inline void dm_write_index_reg(
79 const struct dc_context *ctx,
80 enum cgs_ind_reg addr_space,
81 uint32_t index,
82 uint32_t value)
83{
84 cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
85}
86
87static inline uint32_t get_reg_field_value_ex(
88 uint32_t reg_value,
89 uint32_t mask,
90 uint8_t shift)
91{
92 return (mask & reg_value) >> shift;
93}
94
95#define get_reg_field_value(reg_value, reg_name, reg_field)\
96 get_reg_field_value_ex(\
97 (reg_value),\
98 reg_name ## __ ## reg_field ## _MASK,\
99 reg_name ## __ ## reg_field ## __SHIFT)
100
101static inline uint32_t set_reg_field_value_ex(
102 uint32_t reg_value,
103 uint32_t value,
104 uint32_t mask,
105 uint8_t shift)
106{
107 ASSERT(mask != 0);
108 return (reg_value & ~mask) | (mask & (value << shift));
109}
110
111#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
112 (reg_value) = set_reg_field_value_ex(\
113 (reg_value),\
114 (value),\
115 reg_name ## __ ## reg_field ## _MASK,\
116 reg_name ## __ ## reg_field ## __SHIFT)
117
118uint32_t generic_reg_set_ex(const struct dc_context *ctx,
119 uint32_t addr, uint32_t reg_val, int n,
120 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
121
122uint32_t generic_reg_update_ex(const struct dc_context *ctx,
123 uint32_t addr, int n,
124 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
125
126struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
127void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
128
129void reg_sequence_start_gather(const struct dc_context *ctx);
130void reg_sequence_start_execute(const struct dc_context *ctx);
131void reg_sequence_wait_done(const struct dc_context *ctx);
132
133#define FD(reg_field) reg_field ## __SHIFT, \
134 reg_field ## _MASK
135
136/*
137 * return number of poll before condition is met
138 * return 0 if condition is not meet after specified time out tries
139 */
140void generic_reg_wait(const struct dc_context *ctx,
141 uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
142 unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
143 const char *func_name, int line);
144
145unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
146
147/* These macros need to be used with soc15 registers in order to retrieve
148 * the actual offset.
149 */
150#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
151 dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
152
153#define dm_read_reg_soc15(ctx, reg, inst_offset) \
154 dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
155
156#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
157 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
158 n, __VA_ARGS__)
159
160#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
161 generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
162 n, __VA_ARGS__)
163
164#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
165 get_reg_field_value_ex(\
166 (reg_value),\
167 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
168 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
169
170#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
171 (reg_value) = set_reg_field_value_ex(\
172 (reg_value),\
173 (value),\
174 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
175 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
176
177/**************************************
178 * Power Play (PP) interfaces
179 **************************************/
180
181/* Gets valid clocks levels from pplib
182 *
183 * input: clk_type - display clk / sclk / mem clk
184 *
185 * output: array of valid clock levels for given type in ascending order,
186 * with invalid levels filtered out
187 *
188 */
189bool dm_pp_get_clock_levels_by_type(
190 const struct dc_context *ctx,
191 enum dm_pp_clock_type clk_type,
192 struct dm_pp_clock_levels *clk_level_info);
193
194bool dm_pp_get_clock_levels_by_type_with_latency(
195 const struct dc_context *ctx,
196 enum dm_pp_clock_type clk_type,
197 struct dm_pp_clock_levels_with_latency *clk_level_info);
198
199bool dm_pp_get_clock_levels_by_type_with_voltage(
200 const struct dc_context *ctx,
201 enum dm_pp_clock_type clk_type,
202 struct dm_pp_clock_levels_with_voltage *clk_level_info);
203
204bool dm_pp_notify_wm_clock_changes(
205 const struct dc_context *ctx,
206 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
207
208void dm_pp_get_funcs(struct dc_context *ctx,
209 struct pp_smu_funcs *funcs);
210
211/* DAL calls this function to notify PP about completion of Mode Set.
212 * For PP it means that current DCE clocks are those which were returned
213 * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
214 *
215 * If the clocks are higher than before, then PP does nothing.
216 *
217 * If the clocks are lower than before, then PP reduces the voltage.
218 *
219 * \returns true - call is successful
220 * false - call failed
221 */
222bool dm_pp_apply_display_requirements(
223 const struct dc_context *ctx,
224 const struct dm_pp_display_configuration *pp_display_cfg);
225
226bool dm_pp_apply_power_level_change_request(
227 const struct dc_context *ctx,
228 struct dm_pp_power_level_change_request *level_change_req);
229
230bool dm_pp_apply_clock_for_voltage_request(
231 const struct dc_context *ctx,
232 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
233
234bool dm_pp_get_static_clocks(
235 const struct dc_context *ctx,
236 struct dm_pp_static_clock_info *static_clk_info);
237
238/****** end of PP interfaces ******/
239
240struct persistent_data_flag {
241 bool save_per_link;
242 bool save_per_edid;
243};
244
245bool dm_query_extended_brightness_caps
246 (struct dc_context *ctx, enum dm_acpi_display_type display,
247 struct dm_acpi_atif_backlight_caps *pCaps);
248
249bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
250
251/*
252 *
253 * print-out services
254 *
255 */
256#define dm_log_to_buffer(buffer, size, fmt, args)\
257 vsnprintf(buffer, size, fmt, args)
258
259static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
260{
261 return ktime_get_raw_ns();
262}
263
264unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
265 unsigned long long current_time_stamp,
266 unsigned long long last_time_stamp);
267
268/*
269 * performance tracing
270 */
271void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
272
273#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
274#define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
275
276/*
277 * Debug and verification hooks
278 */
279
280void dm_dtn_log_begin(struct dc_context *ctx,
281 struct dc_log_buffer_ctx *log_ctx);
282void dm_dtn_log_append_v(struct dc_context *ctx,
283 struct dc_log_buffer_ctx *log_ctx,
284 const char *msg, ...);
285void dm_dtn_log_end(struct dc_context *ctx,
286 struct dc_log_buffer_ctx *log_ctx);
287
288#endif /* __DM_SERVICES_H__ */
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/**
27 * This file defines external dependencies of Display Core.
28 */
29
30#ifndef __DM_SERVICES_H__
31
32#define __DM_SERVICES_H__
33
34#include "amdgpu_dm_trace.h"
35
36/* TODO: remove when DC is complete. */
37#include "dm_services_types.h"
38#include "logger_interface.h"
39#include "link_service_types.h"
40
41#undef DEPRECATED
42
43irq_handler_idx dm_register_interrupt(
44 struct dc_context *ctx,
45 struct dc_interrupt_params *int_params,
46 interrupt_handler ih,
47 void *handler_args);
48
49
50/*
51 *
52 * GPU registers access
53 *
54 */
55uint32_t dm_read_reg_func(
56 const struct dc_context *ctx,
57 uint32_t address,
58 const char *func_name);
59/* enable for debugging new code, this adds 50k to the driver size. */
60/* #define DM_CHECK_ADDR_0 */
61
62#define dm_read_reg(ctx, address) \
63 dm_read_reg_func(ctx, address, __func__)
64
65
66
67#define dm_write_reg(ctx, address, value) \
68 dm_write_reg_func(ctx, address, value, __func__)
69
70static inline void dm_write_reg_func(
71 const struct dc_context *ctx,
72 uint32_t address,
73 uint32_t value,
74 const char *func_name)
75{
76#ifdef DM_CHECK_ADDR_0
77 if (address == 0) {
78 DC_ERR("invalid register write. address = 0");
79 return;
80 }
81#endif
82 cgs_write_register(ctx->cgs_device, address, value);
83 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
84}
85
86static inline uint32_t dm_read_index_reg(
87 const struct dc_context *ctx,
88 enum cgs_ind_reg addr_space,
89 uint32_t index)
90{
91 return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
92}
93
94static inline void dm_write_index_reg(
95 const struct dc_context *ctx,
96 enum cgs_ind_reg addr_space,
97 uint32_t index,
98 uint32_t value)
99{
100 cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
101}
102
103static inline uint32_t get_reg_field_value_ex(
104 uint32_t reg_value,
105 uint32_t mask,
106 uint8_t shift)
107{
108 return (mask & reg_value) >> shift;
109}
110
111#define get_reg_field_value(reg_value, reg_name, reg_field)\
112 get_reg_field_value_ex(\
113 (reg_value),\
114 reg_name ## __ ## reg_field ## _MASK,\
115 reg_name ## __ ## reg_field ## __SHIFT)
116
117static inline uint32_t set_reg_field_value_ex(
118 uint32_t reg_value,
119 uint32_t value,
120 uint32_t mask,
121 uint8_t shift)
122{
123 ASSERT(mask != 0);
124 return (reg_value & ~mask) | (mask & (value << shift));
125}
126
127#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
128 (reg_value) = set_reg_field_value_ex(\
129 (reg_value),\
130 (value),\
131 reg_name ## __ ## reg_field ## _MASK,\
132 reg_name ## __ ## reg_field ## __SHIFT)
133
134uint32_t generic_reg_set_ex(const struct dc_context *ctx,
135 uint32_t addr, uint32_t reg_val, int n,
136 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
137
138uint32_t generic_reg_update_ex(const struct dc_context *ctx,
139 uint32_t addr, int n,
140 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
141
142#define FD(reg_field) reg_field ## __SHIFT, \
143 reg_field ## _MASK
144
145/*
146 * return number of poll before condition is met
147 * return 0 if condition is not meet after specified time out tries
148 */
149void generic_reg_wait(const struct dc_context *ctx,
150 uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
151 unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
152 const char *func_name, int line);
153
154unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
155
156/* These macros need to be used with soc15 registers in order to retrieve
157 * the actual offset.
158 */
159#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
160 dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
161
162#define dm_read_reg_soc15(ctx, reg, inst_offset) \
163 dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
164
165#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
166 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
167 n, __VA_ARGS__)
168
169#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
170 generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
171 n, __VA_ARGS__)
172
173#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
174 get_reg_field_value_ex(\
175 (reg_value),\
176 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
177 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
178
179#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
180 (reg_value) = set_reg_field_value_ex(\
181 (reg_value),\
182 (value),\
183 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
184 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
185
186/**************************************
187 * Power Play (PP) interfaces
188 **************************************/
189
190/* Gets valid clocks levels from pplib
191 *
192 * input: clk_type - display clk / sclk / mem clk
193 *
194 * output: array of valid clock levels for given type in ascending order,
195 * with invalid levels filtered out
196 *
197 */
198bool dm_pp_get_clock_levels_by_type(
199 const struct dc_context *ctx,
200 enum dm_pp_clock_type clk_type,
201 struct dm_pp_clock_levels *clk_level_info);
202
203bool dm_pp_get_clock_levels_by_type_with_latency(
204 const struct dc_context *ctx,
205 enum dm_pp_clock_type clk_type,
206 struct dm_pp_clock_levels_with_latency *clk_level_info);
207
208bool dm_pp_get_clock_levels_by_type_with_voltage(
209 const struct dc_context *ctx,
210 enum dm_pp_clock_type clk_type,
211 struct dm_pp_clock_levels_with_voltage *clk_level_info);
212
213bool dm_pp_notify_wm_clock_changes(
214 const struct dc_context *ctx,
215 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
216
217void dm_pp_get_funcs(struct dc_context *ctx,
218 struct pp_smu_funcs *funcs);
219
220/* DAL calls this function to notify PP about completion of Mode Set.
221 * For PP it means that current DCE clocks are those which were returned
222 * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
223 *
224 * If the clocks are higher than before, then PP does nothing.
225 *
226 * If the clocks are lower than before, then PP reduces the voltage.
227 *
228 * \returns true - call is successful
229 * false - call failed
230 */
231bool dm_pp_apply_display_requirements(
232 const struct dc_context *ctx,
233 const struct dm_pp_display_configuration *pp_display_cfg);
234
235bool dm_pp_apply_power_level_change_request(
236 const struct dc_context *ctx,
237 struct dm_pp_power_level_change_request *level_change_req);
238
239bool dm_pp_apply_clock_for_voltage_request(
240 const struct dc_context *ctx,
241 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
242
243bool dm_pp_get_static_clocks(
244 const struct dc_context *ctx,
245 struct dm_pp_static_clock_info *static_clk_info);
246
247/****** end of PP interfaces ******/
248
249struct persistent_data_flag {
250 bool save_per_link;
251 bool save_per_edid;
252};
253
254/* Call to write data in registry editor for persistent data storage.
255 *
256 * \inputs sink - identify edid/link for registry folder creation
257 * module name - identify folders for registry
258 * key name - identify keys within folders for registry
259 * params - value to write in defined folder/key
260 * size - size of the input params
261 * flag - determine whether to save by link or edid
262 *
263 * \returns true - call is successful
264 * false - call failed
265 *
266 * sink module key
267 * -----------------------------------------------------------------------------
268 * NULL NULL NULL - failure
269 * NULL NULL - - create key with param value
270 * under base folder
271 * NULL - NULL - create module folder under base folder
272 * - NULL NULL - failure
273 * NULL - - - create key under module folder
274 * with no edid/link identification
275 * - NULL - - create key with param value
276 * under base folder
277 * - - NULL - create module folder under base folder
278 * - - - - create key under module folder
279 * with edid/link identification
280 */
281bool dm_write_persistent_data(struct dc_context *ctx,
282 const struct dc_sink *sink,
283 const char *module_name,
284 const char *key_name,
285 void *params,
286 unsigned int size,
287 struct persistent_data_flag *flag);
288
289
290/* Call to read data in registry editor for persistent data storage.
291 *
292 * \inputs sink - identify edid/link for registry folder creation
293 * module name - identify folders for registry
294 * key name - identify keys within folders for registry
295 * size - size of the output params
296 * flag - determine whether it was save by link or edid
297 *
298 * \returns params - value read from defined folder/key
299 * true - call is successful
300 * false - call failed
301 *
302 * sink module key
303 * -----------------------------------------------------------------------------
304 * NULL NULL NULL - failure
305 * NULL NULL - - read key under base folder
306 * NULL - NULL - failure
307 * - NULL NULL - failure
308 * NULL - - - read key under module folder
309 * with no edid/link identification
310 * - NULL - - read key under base folder
311 * - - NULL - failure
312 * - - - - read key under module folder
313 * with edid/link identification
314 */
315bool dm_read_persistent_data(struct dc_context *ctx,
316 const struct dc_sink *sink,
317 const char *module_name,
318 const char *key_name,
319 void *params,
320 unsigned int size,
321 struct persistent_data_flag *flag);
322
323bool dm_query_extended_brightness_caps
324 (struct dc_context *ctx, enum dm_acpi_display_type display,
325 struct dm_acpi_atif_backlight_caps *pCaps);
326
327bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
328
329/*
330 *
331 * print-out services
332 *
333 */
334#define dm_log_to_buffer(buffer, size, fmt, args)\
335 vsnprintf(buffer, size, fmt, args)
336
337static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
338{
339 return ktime_get_raw_ns();
340}
341
342unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
343 unsigned long long current_time_stamp,
344 unsigned long long last_time_stamp);
345
346/*
347 * performance tracing
348 */
349#define PERF_TRACE() trace_amdgpu_dc_performance(CTX->perf_trace->read_count,\
350 CTX->perf_trace->write_count, &CTX->perf_trace->last_entry_read,\
351 &CTX->perf_trace->last_entry_write, __func__, __LINE__)
352#define PERF_TRACE_CTX(__CTX) trace_amdgpu_dc_performance(__CTX->perf_trace->read_count,\
353 __CTX->perf_trace->write_count, &__CTX->perf_trace->last_entry_read,\
354 &__CTX->perf_trace->last_entry_write, __func__, __LINE__)
355
356
357/*
358 * Debug and verification hooks
359 */
360
361void dm_dtn_log_begin(struct dc_context *ctx,
362 struct dc_log_buffer_ctx *log_ctx);
363void dm_dtn_log_append_v(struct dc_context *ctx,
364 struct dc_log_buffer_ctx *log_ctx,
365 const char *msg, ...);
366void dm_dtn_log_end(struct dc_context *ctx,
367 struct dc_log_buffer_ctx *log_ctx);
368
369#endif /* __DM_SERVICES_H__ */