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1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef _DCE_ABM_H_
28#define _DCE_ABM_H_
29
30#include "abm.h"
31
32#define ABM_COMMON_REG_LIST_DCE_BASE() \
33 SR(MASTER_COMM_CNTL_REG), \
34 SR(MASTER_COMM_CMD_REG), \
35 SR(MASTER_COMM_DATA_REG1)
36
37#define ABM_DCE110_COMMON_REG_LIST() \
38 ABM_COMMON_REG_LIST_DCE_BASE(), \
39 SR(DC_ABM1_HG_SAMPLE_RATE), \
40 SR(DC_ABM1_LS_SAMPLE_RATE), \
41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
42 SR(DC_ABM1_HG_MISC_CTRL), \
43 SR(DC_ABM1_IPCSC_COEFF_SEL), \
44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
45 SR(BL1_PWM_TARGET_ABM_LEVEL), \
46 SR(BL1_PWM_USER_LEVEL), \
47 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
48 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
49 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
50 SR(DC_ABM1_ACE_THRES_12), \
51 SR(BIOS_SCRATCH_2)
52
53#define ABM_DCN10_REG_LIST(id)\
54 ABM_COMMON_REG_LIST_DCE_BASE(), \
55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
65 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
66 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
67 NBIO_SR(BIOS_SCRATCH_2)
68
69#define ABM_DCN20_REG_LIST() \
70 ABM_COMMON_REG_LIST_DCE_BASE(), \
71 SR(DC_ABM1_HG_SAMPLE_RATE), \
72 SR(DC_ABM1_LS_SAMPLE_RATE), \
73 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
74 SR(DC_ABM1_HG_MISC_CTRL), \
75 SR(DC_ABM1_IPCSC_COEFF_SEL), \
76 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
77 SR(BL1_PWM_TARGET_ABM_LEVEL), \
78 SR(BL1_PWM_USER_LEVEL), \
79 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
80 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
81 SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
82 SR(DC_ABM1_ACE_THRES_12), \
83 NBIO_SR(BIOS_SCRATCH_2)
84
85#define ABM_DCN301_REG_LIST(id)\
86 ABM_COMMON_REG_LIST_DCE_BASE(), \
87 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
88 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
89 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
90 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
91 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
92 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
93 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
94 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
95 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
96 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
97 NBIO_SR(BIOS_SCRATCH_2)
98
99#define ABM_DCN302_REG_LIST(id)\
100 ABM_COMMON_REG_LIST_DCE_BASE(), \
101 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
102 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
103 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
104 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
105 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
106 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
107 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
108 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
109 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
110 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
111 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
112 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
113 NBIO_SR(BIOS_SCRATCH_2)
114
115#define ABM_DCN30_REG_LIST(id)\
116 ABM_COMMON_REG_LIST_DCE_BASE(), \
117 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
118 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
119 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
120 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
121 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
122 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
123 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
124 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
125 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
126 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
127 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
128 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
129 NBIO_SR(BIOS_SCRATCH_2)
130
131#define ABM_DCN32_REG_LIST(id)\
132 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
133 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
134 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
135 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
136 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
137 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
138 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
139 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
140 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
141 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
142 SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
143 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
144 NBIO_SR(BIOS_SCRATCH_2)
145
146#define ABM_SF(reg_name, field_name, post_fix)\
147 .field_name = reg_name ## __ ## field_name ## post_fix
148
149#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
150 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
151 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
152 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
153 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
154
155#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
156 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
157 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
158 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
159 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
160 ABM1_HG_VMAX_SEL, mask_sh), \
161 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
162 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
163 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
164 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
165 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
166 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
167 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
168 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
169 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
170 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
171 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
172 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
173 ABM_SF(BL1_PWM_USER_LEVEL, \
174 BL1_PWM_USER_LEVEL, mask_sh), \
175 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
176 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
177 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
178 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
179 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
180 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
181 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
182 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
183 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
184 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
185
186#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
187 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
188 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
189 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
190 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
191 ABM1_HG_VMAX_SEL, mask_sh), \
192 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
193 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
194 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
195 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
196 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
197 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
198 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
199 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
200 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
201 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
202 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
203 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
204 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
205 BL1_PWM_USER_LEVEL, mask_sh), \
206 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
207 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
208 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
209 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
210 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
211 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
212 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
213 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
214 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
215 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
216
217#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
218
219#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
220
221#define ABM_MASK_SH_LIST_DCN32(mask_sh) \
222 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
223 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
224 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
225 ABM1_HG_VMAX_SEL, mask_sh), \
226 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
227 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
228 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
229 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
230 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
231 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
232 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
233 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
234 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
235 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
236 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
237 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
238 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
239 BL1_PWM_USER_LEVEL, mask_sh), \
240 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
241 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
242 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
243 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
244 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
245 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
246 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
247 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
248 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
249 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
250
251#define ABM_REG_FIELD_LIST(type) \
252 type ABM1_HG_NUM_OF_BINS_SEL; \
253 type ABM1_HG_VMAX_SEL; \
254 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
255 type ABM1_IPCSC_COEFF_SEL_R; \
256 type ABM1_IPCSC_COEFF_SEL_G; \
257 type ABM1_IPCSC_COEFF_SEL_B; \
258 type BL1_PWM_CURRENT_ABM_LEVEL; \
259 type BL1_PWM_TARGET_ABM_LEVEL; \
260 type BL1_PWM_USER_LEVEL; \
261 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
262 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
263 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
264 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
265 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
266 type MASTER_COMM_INTERRUPT; \
267 type MASTER_COMM_CMD_REG_BYTE0; \
268 type MASTER_COMM_CMD_REG_BYTE1; \
269 type MASTER_COMM_CMD_REG_BYTE2
270
271struct dce_abm_shift {
272 ABM_REG_FIELD_LIST(uint8_t);
273};
274
275struct dce_abm_mask {
276 ABM_REG_FIELD_LIST(uint32_t);
277};
278
279struct dce_abm_registers {
280 uint32_t DC_ABM1_HG_SAMPLE_RATE;
281 uint32_t DC_ABM1_LS_SAMPLE_RATE;
282 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
283 uint32_t DC_ABM1_HG_MISC_CTRL;
284 uint32_t DC_ABM1_IPCSC_COEFF_SEL;
285 uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
286 uint32_t BL1_PWM_TARGET_ABM_LEVEL;
287 uint32_t BL1_PWM_USER_LEVEL;
288 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
289 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
290 uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
291 uint32_t DC_ABM1_ACE_THRES_12;
292 uint32_t MASTER_COMM_CNTL_REG;
293 uint32_t MASTER_COMM_CMD_REG;
294 uint32_t MASTER_COMM_DATA_REG1;
295 uint32_t BIOS_SCRATCH_2;
296};
297
298struct dce_abm {
299 struct abm base;
300 const struct dce_abm_registers *regs;
301 const struct dce_abm_shift *abm_shift;
302 const struct dce_abm_mask *abm_mask;
303};
304
305struct abm *dce_abm_create(
306 struct dc_context *ctx,
307 const struct dce_abm_registers *regs,
308 const struct dce_abm_shift *abm_shift,
309 const struct dce_abm_mask *abm_mask);
310
311void dce_abm_destroy(struct abm **abm);
312
313#endif /* _DCE_ABM_H_ */
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef _DCE_ABM_H_
28#define _DCE_ABM_H_
29
30#include "abm.h"
31
32#define ABM_COMMON_REG_LIST_DCE_BASE() \
33 SR(BL_PWM_PERIOD_CNTL), \
34 SR(BL_PWM_CNTL), \
35 SR(BL_PWM_CNTL2), \
36 SR(BL_PWM_GRP1_REG_LOCK), \
37 SR(LVTMA_PWRSEQ_REF_DIV), \
38 SR(MASTER_COMM_CNTL_REG), \
39 SR(MASTER_COMM_CMD_REG), \
40 SR(MASTER_COMM_DATA_REG1)
41
42#define ABM_DCE110_COMMON_REG_LIST() \
43 ABM_COMMON_REG_LIST_DCE_BASE(), \
44 SR(DC_ABM1_HG_SAMPLE_RATE), \
45 SR(DC_ABM1_LS_SAMPLE_RATE), \
46 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
47 SR(DC_ABM1_HG_MISC_CTRL), \
48 SR(DC_ABM1_IPCSC_COEFF_SEL), \
49 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
50 SR(BL1_PWM_TARGET_ABM_LEVEL), \
51 SR(BL1_PWM_USER_LEVEL), \
52 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
53 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
54 SR(BIOS_SCRATCH_2)
55
56#define ABM_DCN10_REG_LIST(id)\
57 ABM_COMMON_REG_LIST_DCE_BASE(), \
58 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
59 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
60 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
61 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
62 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
63 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
64 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
65 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
66 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
67 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
68 NBIO_SR(BIOS_SCRATCH_2)
69
70#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
71#define ABM_DCN20_REG_LIST() \
72 ABM_COMMON_REG_LIST_DCE_BASE(), \
73 SR(DC_ABM1_HG_SAMPLE_RATE), \
74 SR(DC_ABM1_LS_SAMPLE_RATE), \
75 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
76 SR(DC_ABM1_HG_MISC_CTRL), \
77 SR(DC_ABM1_IPCSC_COEFF_SEL), \
78 SR(BL1_PWM_CURRENT_ABM_LEVEL), \
79 SR(BL1_PWM_TARGET_ABM_LEVEL), \
80 SR(BL1_PWM_USER_LEVEL), \
81 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
82 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
83 NBIO_SR(BIOS_SCRATCH_2)
84#endif
85
86#define ABM_SF(reg_name, field_name, post_fix)\
87 .field_name = reg_name ## __ ## field_name ## post_fix
88
89#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
90 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
91 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
92 ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
93 ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
94 ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
95 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
96 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
97 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
98 ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
99 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
100 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
101 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
102 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
103
104#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
105 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
106 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
107 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
108 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
109 ABM1_HG_VMAX_SEL, mask_sh), \
110 ABM_SF(DC_ABM1_HG_MISC_CTRL, \
111 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
112 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
113 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
114 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
115 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
116 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
117 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
118 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
119 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
120 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
121 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
122 ABM_SF(BL1_PWM_USER_LEVEL, \
123 BL1_PWM_USER_LEVEL, mask_sh), \
124 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
125 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
126 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
127 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
128 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
129 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
130 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
131 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
132 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
133 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
134
135#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
136 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
137 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
138 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
139 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
140 ABM1_HG_VMAX_SEL, mask_sh), \
141 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
142 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
143 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
144 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
145 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
146 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
147 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
148 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
149 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
150 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
151 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
152 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
153 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
154 BL1_PWM_USER_LEVEL, mask_sh), \
155 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
156 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
157 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
158 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
159 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
160 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
161 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
162 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
163 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
164 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
165
166#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
167#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
168#endif
169
170#define ABM_REG_FIELD_LIST(type) \
171 type ABM1_HG_NUM_OF_BINS_SEL; \
172 type ABM1_HG_VMAX_SEL; \
173 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
174 type ABM1_IPCSC_COEFF_SEL_R; \
175 type ABM1_IPCSC_COEFF_SEL_G; \
176 type ABM1_IPCSC_COEFF_SEL_B; \
177 type BL1_PWM_CURRENT_ABM_LEVEL; \
178 type BL1_PWM_TARGET_ABM_LEVEL; \
179 type BL1_PWM_USER_LEVEL; \
180 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
181 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
182 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
183 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
184 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
185 type BL_PWM_PERIOD; \
186 type BL_PWM_PERIOD_BITCNT; \
187 type BL_ACTIVE_INT_FRAC_CNT; \
188 type BL_PWM_FRACTIONAL_EN; \
189 type MASTER_COMM_INTERRUPT; \
190 type MASTER_COMM_CMD_REG_BYTE0; \
191 type MASTER_COMM_CMD_REG_BYTE1; \
192 type MASTER_COMM_CMD_REG_BYTE2; \
193 type BL_PWM_REF_DIV; \
194 type BL_PWM_EN; \
195 type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
196 type BL_PWM_GRP1_REG_LOCK; \
197 type BL_PWM_GRP1_REG_UPDATE_PENDING
198
199struct dce_abm_shift {
200 ABM_REG_FIELD_LIST(uint8_t);
201};
202
203struct dce_abm_mask {
204 ABM_REG_FIELD_LIST(uint32_t);
205};
206
207struct dce_abm_registers {
208 uint32_t BL_PWM_PERIOD_CNTL;
209 uint32_t BL_PWM_CNTL;
210 uint32_t BL_PWM_CNTL2;
211 uint32_t LVTMA_PWRSEQ_REF_DIV;
212 uint32_t DC_ABM1_HG_SAMPLE_RATE;
213 uint32_t DC_ABM1_LS_SAMPLE_RATE;
214 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
215 uint32_t DC_ABM1_HG_MISC_CTRL;
216 uint32_t DC_ABM1_IPCSC_COEFF_SEL;
217 uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
218 uint32_t BL1_PWM_TARGET_ABM_LEVEL;
219 uint32_t BL1_PWM_USER_LEVEL;
220 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
221 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
222 uint32_t MASTER_COMM_CNTL_REG;
223 uint32_t MASTER_COMM_CMD_REG;
224 uint32_t MASTER_COMM_DATA_REG1;
225 uint32_t BIOS_SCRATCH_2;
226 uint32_t BL_PWM_GRP1_REG_LOCK;
227};
228
229struct dce_abm {
230 struct abm base;
231 const struct dce_abm_registers *regs;
232 const struct dce_abm_shift *abm_shift;
233 const struct dce_abm_mask *abm_mask;
234};
235
236struct abm *dce_abm_create(
237 struct dc_context *ctx,
238 const struct dce_abm_registers *regs,
239 const struct dce_abm_shift *abm_shift,
240 const struct dce_abm_mask *abm_mask);
241
242void dce_abm_destroy(struct abm **abm);
243
244#endif /* _DCE_ABM_H_ */