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1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/slab.h>
27
28#include "dce_abm.h"
29#include "dm_services.h"
30#include "reg_helper.h"
31#include "fixed31_32.h"
32#include "dc.h"
33
34#include "atom.h"
35
36
37#define TO_DCE_ABM(abm)\
38 container_of(abm, struct dce_abm, base)
39
40#define REG(reg) \
41 (abm_dce->regs->reg)
42
43#undef FN
44#define FN(reg_name, field_name) \
45 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
46
47#define DC_LOGGER \
48 abm->ctx->logger
49#define CTX \
50 abm_dce->base.ctx
51
52#define MCP_ABM_LEVEL_SET 0x65
53#define MCP_ABM_PIPE_SET 0x66
54#define MCP_BL_SET 0x67
55
56#define MCP_DISABLE_ABM_IMMEDIATELY 255
57
58static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)
59{
60 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
61 uint32_t rampingBoundary = 0xFFFF;
62
63 if (abm->dmcu_is_running == false)
64 return true;
65
66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
67 1, 80000);
68
69 /* set ramping boundary */
70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
71
72 /* setDMCUParam_Pipe */
73 REG_UPDATE_2(MASTER_COMM_CMD_REG,
74 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
75 MASTER_COMM_CMD_REG_BYTE1, controller_id);
76
77 /* notifyDMCUMsg */
78 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
79
80 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
81 1, 80000);
82
83 return true;
84}
85
86static void dmcu_set_backlight_level(
87 struct dce_abm *abm_dce,
88 uint32_t backlight_pwm_u16_16,
89 uint32_t frame_ramp,
90 uint32_t controller_id,
91 uint32_t panel_id)
92{
93 unsigned int backlight_8_bit = 0;
94 uint32_t s2;
95
96 if (backlight_pwm_u16_16 & 0x10000)
97 // Check for max backlight condition
98 backlight_8_bit = 0xFF;
99 else
100 // Take MSB of fractional part since backlight is not max
101 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;
102
103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id);
104
105 /* waitDMCUReadyForCmd */
106 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
107 0, 1, 80000);
108
109 /* setDMCUParam_BL */
110 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
111
112 /* write ramp */
113 if (controller_id == 0)
114 frame_ramp = 0;
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
116
117 /* setDMCUParam_Cmd */
118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
119
120 /* notifyDMCUMsg */
121 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
122
123 /* UpdateRequestedBacklightLevel */
124 s2 = REG_READ(BIOS_SCRATCH_2);
125
126 s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
127 backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
128 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
129 s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
130
131 REG_WRITE(BIOS_SCRATCH_2, s2);
132
133 /* waitDMCUReadyForCmd */
134 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
135 0, 1, 80000);
136}
137
138static void dce_abm_init(struct abm *abm, uint32_t backlight)
139{
140 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
141
142 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
143 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
144 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
145 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
146 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
147
148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
149 ABM1_HG_NUM_OF_BINS_SEL, 0,
150 ABM1_HG_VMAX_SEL, 1,
151 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
152
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
154 ABM1_IPCSC_COEFF_SEL_R, 2,
155 ABM1_IPCSC_COEFF_SEL_G, 4,
156 ABM1_IPCSC_COEFF_SEL_B, 2);
157
158 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
159 BL1_PWM_CURRENT_ABM_LEVEL, backlight);
160
161 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
162 BL1_PWM_TARGET_ABM_LEVEL, backlight);
163
164 REG_UPDATE(BL1_PWM_USER_LEVEL,
165 BL1_PWM_USER_LEVEL, backlight);
166
167 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
168 ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
169 ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
170
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
172 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
173 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
174 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
175}
176
177static unsigned int dce_abm_get_current_backlight(struct abm *abm)
178{
179 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
180 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
181
182 /* return backlight in hardware format which is unsigned 17 bits, with
183 * 1 bit integer and 16 bit fractional
184 */
185 return backlight;
186}
187
188static unsigned int dce_abm_get_target_backlight(struct abm *abm)
189{
190 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
191 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
192
193 /* return backlight in hardware format which is unsigned 17 bits, with
194 * 1 bit integer and 16 bit fractional
195 */
196 return backlight;
197}
198
199static bool dce_abm_set_level(struct abm *abm, uint32_t level)
200{
201 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
202
203 if (abm->dmcu_is_running == false)
204 return true;
205
206 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
207 1, 80000);
208
209 /* setDMCUParam_ABMLevel */
210 REG_UPDATE_2(MASTER_COMM_CMD_REG,
211 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
212 MASTER_COMM_CMD_REG_BYTE2, level);
213
214 /* notifyDMCUMsg */
215 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
216
217 return true;
218}
219
220static bool dce_abm_immediate_disable(struct abm *abm, uint32_t panel_inst)
221{
222 if (abm->dmcu_is_running == false)
223 return true;
224
225 dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY, panel_inst);
226
227 return true;
228}
229
230static bool dce_abm_set_backlight_level_pwm(
231 struct abm *abm,
232 unsigned int backlight_pwm_u16_16,
233 unsigned int frame_ramp,
234 unsigned int controller_id,
235 unsigned int panel_inst)
236{
237 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
238
239 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
240 backlight_pwm_u16_16, backlight_pwm_u16_16);
241
242 dmcu_set_backlight_level(abm_dce,
243 backlight_pwm_u16_16,
244 frame_ramp,
245 controller_id,
246 panel_inst);
247
248 return true;
249}
250
251static const struct abm_funcs dce_funcs = {
252 .abm_init = dce_abm_init,
253 .set_abm_level = dce_abm_set_level,
254 .set_pipe = dce_abm_set_pipe,
255 .set_backlight_level_pwm = dce_abm_set_backlight_level_pwm,
256 .get_current_backlight = dce_abm_get_current_backlight,
257 .get_target_backlight = dce_abm_get_target_backlight,
258 .init_abm_config = NULL,
259 .set_abm_immediate_disable = dce_abm_immediate_disable,
260};
261
262static void dce_abm_construct(
263 struct dce_abm *abm_dce,
264 struct dc_context *ctx,
265 const struct dce_abm_registers *regs,
266 const struct dce_abm_shift *abm_shift,
267 const struct dce_abm_mask *abm_mask)
268{
269 struct abm *base = &abm_dce->base;
270
271 base->ctx = ctx;
272 base->funcs = &dce_funcs;
273 base->dmcu_is_running = false;
274
275 abm_dce->regs = regs;
276 abm_dce->abm_shift = abm_shift;
277 abm_dce->abm_mask = abm_mask;
278}
279
280struct abm *dce_abm_create(
281 struct dc_context *ctx,
282 const struct dce_abm_registers *regs,
283 const struct dce_abm_shift *abm_shift,
284 const struct dce_abm_mask *abm_mask)
285{
286 struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC);
287
288 if (abm_dce == NULL) {
289 BREAK_TO_DEBUGGER();
290 return NULL;
291 }
292
293 dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
294
295 abm_dce->base.funcs = &dce_funcs;
296
297 return &abm_dce->base;
298}
299
300void dce_abm_destroy(struct abm **abm)
301{
302 struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
303
304 kfree(abm_dce);
305 *abm = NULL;
306}
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/slab.h>
27
28#include "dce_abm.h"
29#include "dm_services.h"
30#include "reg_helper.h"
31#include "fixed31_32.h"
32#include "dc.h"
33
34#include "atom.h"
35
36
37#define TO_DCE_ABM(abm)\
38 container_of(abm, struct dce_abm, base)
39
40#define REG(reg) \
41 (abm_dce->regs->reg)
42
43#undef FN
44#define FN(reg_name, field_name) \
45 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
46
47#define DC_LOGGER \
48 abm->ctx->logger
49#define CTX \
50 abm_dce->base.ctx
51
52#define MCP_ABM_LEVEL_SET 0x65
53#define MCP_ABM_PIPE_SET 0x66
54#define MCP_BL_SET 0x67
55
56#define MCP_DISABLE_ABM_IMMEDIATELY 255
57
58static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
59{
60 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
61 uint32_t rampingBoundary = 0xFFFF;
62
63 if (abm->dmcu_is_running == false)
64 return true;
65
66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
67 1, 80000);
68
69 /* set ramping boundary */
70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
71
72 /* setDMCUParam_Pipe */
73 REG_UPDATE_2(MASTER_COMM_CMD_REG,
74 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
75 MASTER_COMM_CMD_REG_BYTE1, controller_id);
76
77 /* notifyDMCUMsg */
78 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
79
80 return true;
81}
82
83static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_abm *abm_dce)
84{
85 uint64_t current_backlight;
86 uint32_t round_result;
87 uint32_t pwm_period_cntl, bl_period, bl_int_count;
88 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
89 uint32_t bl_period_mask, bl_pwm_mask;
90
91 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
92 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
93 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
94
95 bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
96 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
97 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
98
99 if (bl_int_count == 0)
100 bl_int_count = 16;
101
102 bl_period_mask = (1 << bl_int_count) - 1;
103 bl_period &= bl_period_mask;
104
105 bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
106
107 if (fractional_duty_cycle_en == 0)
108 bl_pwm &= bl_pwm_mask;
109 else
110 bl_pwm &= 0xFFFF;
111
112 current_backlight = bl_pwm << (1 + bl_int_count);
113
114 if (bl_period == 0)
115 bl_period = 0xFFFF;
116
117 current_backlight = div_u64(current_backlight, bl_period);
118 current_backlight = (current_backlight + 1) >> 1;
119
120 current_backlight = (uint64_t)(current_backlight) * bl_period;
121
122 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
123
124 round_result = (round_result >> (bl_int_count-1)) & 1;
125
126 current_backlight >>= bl_int_count;
127 current_backlight += round_result;
128
129 return (uint32_t)(current_backlight);
130}
131
132static void driver_set_backlight_level(struct dce_abm *abm_dce,
133 uint32_t backlight_pwm_u16_16)
134{
135 uint32_t backlight_16bit;
136 uint32_t masked_pwm_period;
137 uint8_t bit_count;
138 uint64_t active_duty_cycle;
139 uint32_t pwm_period_bitcnt;
140
141 /*
142 * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight
143 * active duty cycle <= backlight period
144 */
145
146 /* 1.1 Apply bitmask for backlight period value based on value of BITCNT
147 */
148 REG_GET_2(BL_PWM_PERIOD_CNTL,
149 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
150 BL_PWM_PERIOD, &masked_pwm_period);
151
152 if (pwm_period_bitcnt == 0)
153 bit_count = 16;
154 else
155 bit_count = pwm_period_bitcnt;
156
157 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
158 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
159
160 /* 1.2 Calculate integer active duty cycle required upper 16 bits
161 * contain integer component, lower 16 bits contain fractional component
162 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
163 */
164 active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
165
166 /* 1.3 Calculate 16 bit active duty cycle from integer and fractional
167 * components shift by bitCount then mask 16 bits and add rounding bit
168 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
169 */
170 backlight_16bit = active_duty_cycle >> bit_count;
171 backlight_16bit &= 0xFFFF;
172 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
173
174 /*
175 * 2. Program register with updated value
176 */
177
178 /* 2.1 Lock group 2 backlight registers */
179
180 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
181 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
182 BL_PWM_GRP1_REG_LOCK, 1);
183
184 // 2.2 Write new active duty cycle
185 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
186
187 /* 2.3 Unlock group 2 backlight registers */
188 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
189 BL_PWM_GRP1_REG_LOCK, 0);
190
191 /* 3 Wait for pending bit to be cleared */
192 REG_WAIT(BL_PWM_GRP1_REG_LOCK,
193 BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
194 1, 10000);
195}
196
197static void dmcu_set_backlight_level(
198 struct dce_abm *abm_dce,
199 uint32_t backlight_pwm_u16_16,
200 uint32_t frame_ramp,
201 uint32_t controller_id)
202{
203 unsigned int backlight_8_bit = 0;
204 uint32_t s2;
205
206 if (backlight_pwm_u16_16 & 0x10000)
207 // Check for max backlight condition
208 backlight_8_bit = 0xFF;
209 else
210 // Take MSB of fractional part since backlight is not max
211 backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;
212
213 dce_abm_set_pipe(&abm_dce->base, controller_id);
214
215 /* waitDMCUReadyForCmd */
216 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
217 0, 1, 80000);
218
219 /* setDMCUParam_BL */
220 REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
221
222 /* write ramp */
223 if (controller_id == 0)
224 frame_ramp = 0;
225 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
226
227 /* setDMCUParam_Cmd */
228 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
229
230 /* notifyDMCUMsg */
231 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
232
233 /* UpdateRequestedBacklightLevel */
234 s2 = REG_READ(BIOS_SCRATCH_2);
235
236 s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
237 backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
238 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
239 s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
240
241 REG_WRITE(BIOS_SCRATCH_2, s2);
242
243 /* waitDMCUReadyForCmd */
244 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
245 0, 1, 80000);
246}
247
248static void dce_abm_init(struct abm *abm)
249{
250 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
251 unsigned int backlight = calculate_16_bit_backlight_from_pwm(abm_dce);
252
253 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
254 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
255 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
256 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
257 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
258
259 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
260 ABM1_HG_NUM_OF_BINS_SEL, 0,
261 ABM1_HG_VMAX_SEL, 1,
262 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
263
264 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
265 ABM1_IPCSC_COEFF_SEL_R, 2,
266 ABM1_IPCSC_COEFF_SEL_G, 4,
267 ABM1_IPCSC_COEFF_SEL_B, 2);
268
269 REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
270 BL1_PWM_CURRENT_ABM_LEVEL, backlight);
271
272 REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
273 BL1_PWM_TARGET_ABM_LEVEL, backlight);
274
275 REG_UPDATE(BL1_PWM_USER_LEVEL,
276 BL1_PWM_USER_LEVEL, backlight);
277
278 REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
279 ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
280 ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
281
282 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
283 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
284 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
285 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
286}
287
288static unsigned int dce_abm_get_current_backlight(struct abm *abm)
289{
290 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
291 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
292
293 /* return backlight in hardware format which is unsigned 17 bits, with
294 * 1 bit integer and 16 bit fractional
295 */
296 return backlight;
297}
298
299static unsigned int dce_abm_get_target_backlight(struct abm *abm)
300{
301 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
302 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
303
304 /* return backlight in hardware format which is unsigned 17 bits, with
305 * 1 bit integer and 16 bit fractional
306 */
307 return backlight;
308}
309
310static bool dce_abm_set_level(struct abm *abm, uint32_t level)
311{
312 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
313
314 if (abm->dmcu_is_running == false)
315 return true;
316
317 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
318 1, 80000);
319
320 /* setDMCUParam_ABMLevel */
321 REG_UPDATE_2(MASTER_COMM_CMD_REG,
322 MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
323 MASTER_COMM_CMD_REG_BYTE2, level);
324
325 /* notifyDMCUMsg */
326 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
327
328 return true;
329}
330
331static bool dce_abm_immediate_disable(struct abm *abm)
332{
333 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
334
335 if (abm->dmcu_is_running == false)
336 return true;
337
338 dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY);
339
340 abm->stored_backlight_registers.BL_PWM_CNTL =
341 REG_READ(BL_PWM_CNTL);
342 abm->stored_backlight_registers.BL_PWM_CNTL2 =
343 REG_READ(BL_PWM_CNTL2);
344 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
345 REG_READ(BL_PWM_PERIOD_CNTL);
346
347 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
348 &abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
349 return true;
350}
351
352static bool dce_abm_init_backlight(struct abm *abm)
353{
354 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
355 uint32_t value;
356
357 /* It must not be 0, so we have to restore them
358 * Bios bug w/a - period resets to zero,
359 * restoring to cache values which is always correct
360 */
361 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
362 if (value == 0 || value == 1) {
363 if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
364 REG_WRITE(BL_PWM_CNTL,
365 abm->stored_backlight_registers.BL_PWM_CNTL);
366 REG_WRITE(BL_PWM_CNTL2,
367 abm->stored_backlight_registers.BL_PWM_CNTL2);
368 REG_WRITE(BL_PWM_PERIOD_CNTL,
369 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
370 REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
371 BL_PWM_REF_DIV,
372 abm->stored_backlight_registers.
373 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
374 } else {
375 /* TODO: Note: This should not really happen since VBIOS
376 * should have initialized PWM registers on boot.
377 */
378 REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
379 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
380 }
381 } else {
382 abm->stored_backlight_registers.BL_PWM_CNTL =
383 REG_READ(BL_PWM_CNTL);
384 abm->stored_backlight_registers.BL_PWM_CNTL2 =
385 REG_READ(BL_PWM_CNTL2);
386 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
387 REG_READ(BL_PWM_PERIOD_CNTL);
388
389 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
390 &abm->stored_backlight_registers.
391 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
392 }
393
394 /* Have driver take backlight control
395 * TakeBacklightControl(true)
396 */
397 value = REG_READ(BIOS_SCRATCH_2);
398 value |= ATOM_S2_VRI_BRIGHT_ENABLE;
399 REG_WRITE(BIOS_SCRATCH_2, value);
400
401 /* Enable the backlight output */
402 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
403
404 /* Unlock group 2 backlight registers */
405 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
406 BL_PWM_GRP1_REG_LOCK, 0);
407
408 return true;
409}
410
411static bool dce_abm_set_backlight_level_pwm(
412 struct abm *abm,
413 unsigned int backlight_pwm_u16_16,
414 unsigned int frame_ramp,
415 unsigned int controller_id,
416 bool use_smooth_brightness)
417{
418 struct dce_abm *abm_dce = TO_DCE_ABM(abm);
419
420 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
421 backlight_pwm_u16_16, backlight_pwm_u16_16);
422
423 /* If DMCU is in reset state, DMCU is uninitialized */
424 if (use_smooth_brightness)
425 dmcu_set_backlight_level(abm_dce,
426 backlight_pwm_u16_16,
427 frame_ramp,
428 controller_id);
429 else
430 driver_set_backlight_level(abm_dce, backlight_pwm_u16_16);
431
432 return true;
433}
434
435static const struct abm_funcs dce_funcs = {
436 .abm_init = dce_abm_init,
437 .set_abm_level = dce_abm_set_level,
438 .init_backlight = dce_abm_init_backlight,
439 .set_pipe = dce_abm_set_pipe,
440 .set_backlight_level_pwm = dce_abm_set_backlight_level_pwm,
441 .get_current_backlight = dce_abm_get_current_backlight,
442 .get_target_backlight = dce_abm_get_target_backlight,
443 .set_abm_immediate_disable = dce_abm_immediate_disable
444};
445
446static void dce_abm_construct(
447 struct dce_abm *abm_dce,
448 struct dc_context *ctx,
449 const struct dce_abm_registers *regs,
450 const struct dce_abm_shift *abm_shift,
451 const struct dce_abm_mask *abm_mask)
452{
453 struct abm *base = &abm_dce->base;
454
455 base->ctx = ctx;
456 base->funcs = &dce_funcs;
457 base->stored_backlight_registers.BL_PWM_CNTL = 0;
458 base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
459 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
460 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
461 base->dmcu_is_running = false;
462
463 abm_dce->regs = regs;
464 abm_dce->abm_shift = abm_shift;
465 abm_dce->abm_mask = abm_mask;
466}
467
468struct abm *dce_abm_create(
469 struct dc_context *ctx,
470 const struct dce_abm_registers *regs,
471 const struct dce_abm_shift *abm_shift,
472 const struct dce_abm_mask *abm_mask)
473{
474 struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
475
476 if (abm_dce == NULL) {
477 BREAK_TO_DEBUGGER();
478 return NULL;
479 }
480
481 dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
482
483 abm_dce->base.funcs = &dce_funcs;
484
485 return &abm_dce->base;
486}
487
488void dce_abm_destroy(struct abm **abm)
489{
490 struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
491
492 if (abm_dce->base.dmcu_is_running == true)
493 abm_dce->base.funcs->set_abm_immediate_disable(*abm);
494
495 kfree(abm_dce);
496 *abm = NULL;
497}