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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/vmalloc.h>
26#include <drm/drm_drv.h>
27
28#include "amdgpu.h"
29#include "amdgpu_psp.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_ucode.h"
32#include "soc15_common.h"
33#include "psp_v11_0.h"
34
35#include "mp/mp_11_0_offset.h"
36#include "mp/mp_11_0_sh_mask.h"
37#include "gc/gc_9_0_offset.h"
38#include "sdma0/sdma0_4_0_offset.h"
39#include "nbio/nbio_7_4_offset.h"
40
41#include "oss/osssys_4_0_offset.h"
42#include "oss/osssys_4_0_sh_mask.h"
43
44MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
45MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
46MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
47MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
48MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
49MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
50MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
51MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
52MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
53MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
54MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
55MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
56MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
57MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
58MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
59MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
60MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
61MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
62MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
63MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
64MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
65MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
66MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
67MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
68MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
69MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
70MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
71
72/* address block */
73#define smnMP1_FIRMWARE_FLAGS 0x3010024
74/* navi10 reg offset define */
75#define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
76#define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
77#define mmSDMA0_UCODE_ADDR_NV10 0x5880
78#define mmSDMA0_UCODE_DATA_NV10 0x5881
79/* memory training timeout define */
80#define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
81
82/* For large FW files the time to complete can be very long */
83#define USBC_PD_POLLING_LIMIT_S 240
84
85/* Read USB-PD from LFB */
86#define GFX_CMD_USB_PD_USE_LFB 0x480
87
88static int psp_v11_0_init_microcode(struct psp_context *psp)
89{
90 struct amdgpu_device *adev = psp->adev;
91 const char *chip_name;
92 char fw_name[PSP_FW_NAME_LEN];
93 int err = 0;
94 const struct ta_firmware_header_v1_0 *ta_hdr;
95
96 DRM_DEBUG("\n");
97
98 switch (adev->ip_versions[MP0_HWIP][0]) {
99 case IP_VERSION(11, 0, 2):
100 chip_name = "vega20";
101 break;
102 case IP_VERSION(11, 0, 0):
103 chip_name = "navi10";
104 break;
105 case IP_VERSION(11, 0, 5):
106 chip_name = "navi14";
107 break;
108 case IP_VERSION(11, 0, 9):
109 chip_name = "navi12";
110 break;
111 case IP_VERSION(11, 0, 4):
112 chip_name = "arcturus";
113 break;
114 case IP_VERSION(11, 0, 7):
115 chip_name = "sienna_cichlid";
116 break;
117 case IP_VERSION(11, 0, 11):
118 chip_name = "navy_flounder";
119 break;
120 case IP_VERSION(11, 5, 0):
121 chip_name = "vangogh";
122 break;
123 case IP_VERSION(11, 0, 12):
124 chip_name = "dimgrey_cavefish";
125 break;
126 case IP_VERSION(11, 0, 13):
127 chip_name = "beige_goby";
128 break;
129 default:
130 BUG();
131 }
132
133
134 switch (adev->ip_versions[MP0_HWIP][0]) {
135 case IP_VERSION(11, 0, 2):
136 case IP_VERSION(11, 0, 4):
137 err = psp_init_sos_microcode(psp, chip_name);
138 if (err)
139 return err;
140 err = psp_init_asd_microcode(psp, chip_name);
141 if (err)
142 return err;
143 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
144 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
145 if (err) {
146 release_firmware(adev->psp.ta_fw);
147 adev->psp.ta_fw = NULL;
148 dev_info(adev->dev,
149 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
150 } else {
151 err = amdgpu_ucode_validate(adev->psp.ta_fw);
152 if (err)
153 goto out2;
154
155 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
156 adev->psp.xgmi_context.context.bin_desc.fw_version =
157 le32_to_cpu(ta_hdr->xgmi.fw_version);
158 adev->psp.xgmi_context.context.bin_desc.size_bytes =
159 le32_to_cpu(ta_hdr->xgmi.size_bytes);
160 adev->psp.xgmi_context.context.bin_desc.start_addr =
161 (uint8_t *)ta_hdr +
162 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
163 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
164 adev->psp.ras_context.context.bin_desc.fw_version =
165 le32_to_cpu(ta_hdr->ras.fw_version);
166 adev->psp.ras_context.context.bin_desc.size_bytes =
167 le32_to_cpu(ta_hdr->ras.size_bytes);
168 adev->psp.ras_context.context.bin_desc.start_addr =
169 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
170 le32_to_cpu(ta_hdr->ras.offset_bytes);
171 }
172 break;
173 case IP_VERSION(11, 0, 0):
174 case IP_VERSION(11, 0, 5):
175 case IP_VERSION(11, 0, 9):
176 err = psp_init_sos_microcode(psp, chip_name);
177 if (err)
178 return err;
179 err = psp_init_asd_microcode(psp, chip_name);
180 if (err)
181 return err;
182 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
183 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
184 if (err) {
185 release_firmware(adev->psp.ta_fw);
186 adev->psp.ta_fw = NULL;
187 dev_info(adev->dev,
188 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
189 } else {
190 err = amdgpu_ucode_validate(adev->psp.ta_fw);
191 if (err)
192 goto out2;
193
194 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
195 adev->psp.hdcp_context.context.bin_desc.fw_version =
196 le32_to_cpu(ta_hdr->hdcp.fw_version);
197 adev->psp.hdcp_context.context.bin_desc.size_bytes =
198 le32_to_cpu(ta_hdr->hdcp.size_bytes);
199 adev->psp.hdcp_context.context.bin_desc.start_addr =
200 (uint8_t *)ta_hdr +
201 le32_to_cpu(
202 ta_hdr->header.ucode_array_offset_bytes);
203
204 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
205
206 adev->psp.dtm_context.context.bin_desc.fw_version =
207 le32_to_cpu(ta_hdr->dtm.fw_version);
208 adev->psp.dtm_context.context.bin_desc.size_bytes =
209 le32_to_cpu(ta_hdr->dtm.size_bytes);
210 adev->psp.dtm_context.context.bin_desc.start_addr =
211 (uint8_t *)adev->psp.hdcp_context.context
212 .bin_desc.start_addr +
213 le32_to_cpu(ta_hdr->dtm.offset_bytes);
214 }
215 break;
216 case IP_VERSION(11, 0, 7):
217 case IP_VERSION(11, 0, 11):
218 case IP_VERSION(11, 0, 12):
219 case IP_VERSION(11, 0, 13):
220 err = psp_init_sos_microcode(psp, chip_name);
221 if (err)
222 return err;
223 err = psp_init_ta_microcode(psp, chip_name);
224 if (err)
225 return err;
226 break;
227 case IP_VERSION(11, 5, 0):
228 err = psp_init_asd_microcode(psp, chip_name);
229 if (err)
230 return err;
231 err = psp_init_toc_microcode(psp, chip_name);
232 if (err)
233 return err;
234 break;
235 default:
236 BUG();
237 }
238
239 return 0;
240
241out2:
242 release_firmware(adev->psp.ta_fw);
243 adev->psp.ta_fw = NULL;
244 return err;
245}
246
247static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
248{
249 struct amdgpu_device *adev = psp->adev;
250
251 int ret;
252 int retry_loop;
253
254 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
255 /* Wait for bootloader to signify that is
256 ready having bit 31 of C2PMSG_35 set to 1 */
257 ret = psp_wait_for(psp,
258 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
259 0x80000000,
260 0x80000000,
261 false);
262
263 if (ret == 0)
264 return 0;
265 }
266
267 return ret;
268}
269
270static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
271{
272 struct amdgpu_device *adev = psp->adev;
273 uint32_t sol_reg;
274
275 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
276
277 return sol_reg != 0x0;
278}
279
280static int psp_v11_0_bootloader_load_component(struct psp_context *psp,
281 struct psp_bin_desc *bin_desc,
282 enum psp_bootloader_cmd bl_cmd)
283{
284 int ret;
285 uint32_t psp_gfxdrv_command_reg = 0;
286 struct amdgpu_device *adev = psp->adev;
287
288 /* Check sOS sign of life register to confirm sys driver and sOS
289 * are already been loaded.
290 */
291 if (psp_v11_0_is_sos_alive(psp))
292 return 0;
293
294 ret = psp_v11_0_wait_for_bootloader(psp);
295 if (ret)
296 return ret;
297
298 /* Copy PSP System Driver binary to memory */
299 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
300
301 /* Provide the sys driver to bootloader */
302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
303 (uint32_t)(psp->fw_pri_mc_addr >> 20));
304 psp_gfxdrv_command_reg = bl_cmd;
305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
306 psp_gfxdrv_command_reg);
307
308 ret = psp_v11_0_wait_for_bootloader(psp);
309
310 return ret;
311}
312
313static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
314{
315 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
316}
317
318static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
319{
320 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
321}
322
323static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
324{
325 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
326}
327
328static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
329{
330 int ret;
331 unsigned int psp_gfxdrv_command_reg = 0;
332 struct amdgpu_device *adev = psp->adev;
333
334 /* Check sOS sign of life register to confirm sys driver and sOS
335 * are already been loaded.
336 */
337 if (psp_v11_0_is_sos_alive(psp))
338 return 0;
339
340 ret = psp_v11_0_wait_for_bootloader(psp);
341 if (ret)
342 return ret;
343
344 /* Copy Secure OS binary to PSP memory */
345 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
346
347 /* Provide the PSP secure OS to bootloader */
348 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
349 (uint32_t)(psp->fw_pri_mc_addr >> 20));
350 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
351 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
352 psp_gfxdrv_command_reg);
353
354 /* there might be handshake issue with hardware which needs delay */
355 mdelay(20);
356 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
357 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
358 0, true);
359
360 return ret;
361}
362
363static int psp_v11_0_ring_stop(struct psp_context *psp,
364 enum psp_ring_type ring_type)
365{
366 int ret = 0;
367 struct amdgpu_device *adev = psp->adev;
368
369 /* Write the ring destroy command*/
370 if (amdgpu_sriov_vf(adev))
371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
372 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
373 else
374 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
375 GFX_CTRL_CMD_ID_DESTROY_RINGS);
376
377 /* there might be handshake issue with hardware which needs delay */
378 mdelay(20);
379
380 /* Wait for response flag (bit 31) */
381 if (amdgpu_sriov_vf(adev))
382 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
383 0x80000000, 0x80000000, false);
384 else
385 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
386 0x80000000, 0x80000000, false);
387
388 return ret;
389}
390
391static int psp_v11_0_ring_create(struct psp_context *psp,
392 enum psp_ring_type ring_type)
393{
394 int ret = 0;
395 unsigned int psp_ring_reg = 0;
396 struct psp_ring *ring = &psp->km_ring;
397 struct amdgpu_device *adev = psp->adev;
398
399 if (amdgpu_sriov_vf(adev)) {
400 ring->ring_wptr = 0;
401 ret = psp_v11_0_ring_stop(psp, ring_type);
402 if (ret) {
403 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
404 return ret;
405 }
406
407 /* Write low address of the ring to C2PMSG_102 */
408 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
409 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
410 /* Write high address of the ring to C2PMSG_103 */
411 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
413
414 /* Write the ring initialization command to C2PMSG_101 */
415 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
416 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
417
418 /* there might be handshake issue with hardware which needs delay */
419 mdelay(20);
420
421 /* Wait for response flag (bit 31) in C2PMSG_101 */
422 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
423 0x80000000, 0x8000FFFF, false);
424
425 } else {
426 /* Wait for sOS ready for ring creation */
427 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
428 0x80000000, 0x80000000, false);
429 if (ret) {
430 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
431 return ret;
432 }
433
434 /* Write low address of the ring to C2PMSG_69 */
435 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
436 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
437 /* Write high address of the ring to C2PMSG_70 */
438 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
439 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
440 /* Write size of ring to C2PMSG_71 */
441 psp_ring_reg = ring->ring_size;
442 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
443 /* Write the ring initialization command to C2PMSG_64 */
444 psp_ring_reg = ring_type;
445 psp_ring_reg = psp_ring_reg << 16;
446 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
447
448 /* there might be handshake issue with hardware which needs delay */
449 mdelay(20);
450
451 /* Wait for response flag (bit 31) in C2PMSG_64 */
452 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
453 0x80000000, 0x8000FFFF, false);
454 }
455
456 return ret;
457}
458
459
460static int psp_v11_0_ring_destroy(struct psp_context *psp,
461 enum psp_ring_type ring_type)
462{
463 int ret = 0;
464 struct psp_ring *ring = &psp->km_ring;
465 struct amdgpu_device *adev = psp->adev;
466
467 ret = psp_v11_0_ring_stop(psp, ring_type);
468 if (ret)
469 DRM_ERROR("Fail to stop psp ring\n");
470
471 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
472 &ring->ring_mem_mc_addr,
473 (void **)&ring->ring_mem);
474
475 return ret;
476}
477
478static int psp_v11_0_mode1_reset(struct psp_context *psp)
479{
480 int ret;
481 uint32_t offset;
482 struct amdgpu_device *adev = psp->adev;
483
484 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
485
486 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
487
488 if (ret) {
489 DRM_INFO("psp is not working correctly before mode1 reset!\n");
490 return -EINVAL;
491 }
492
493 /*send the mode 1 reset command*/
494 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
495
496 msleep(500);
497
498 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
499
500 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
501
502 if (ret) {
503 DRM_INFO("psp mode 1 reset failed!\n");
504 return -EINVAL;
505 }
506
507 DRM_INFO("psp mode1 reset succeed \n");
508
509 return 0;
510}
511
512static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
513{
514 int ret;
515 int i;
516 uint32_t data_32;
517 int max_wait;
518 struct amdgpu_device *adev = psp->adev;
519
520 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
521 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
522 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
523
524 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
525 for (i = 0; i < max_wait; i++) {
526 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
527 0x80000000, 0x80000000, false);
528 if (ret == 0)
529 break;
530 }
531 if (i < max_wait)
532 ret = 0;
533 else
534 ret = -ETIME;
535
536 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
537 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
538 (ret == 0) ? "succeed" : "failed",
539 i, adev->usec_timeout/1000);
540 return ret;
541}
542
543/*
544 * save and restore process
545 */
546static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
547{
548 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
549 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
550 struct amdgpu_device *adev = psp->adev;
551 uint32_t p2c_header[4];
552 uint32_t sz;
553 void *buf;
554 int ret, idx;
555
556 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
557 DRM_DEBUG("Memory training is not supported.\n");
558 return 0;
559 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
560 DRM_ERROR("Memory training initialization failure.\n");
561 return -EINVAL;
562 }
563
564 if (psp_v11_0_is_sos_alive(psp)) {
565 DRM_DEBUG("SOS is alive, skip memory training.\n");
566 return 0;
567 }
568
569 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
570 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
571 pcache[0], pcache[1], pcache[2], pcache[3],
572 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
573
574 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
575 DRM_DEBUG("Short training depends on restore.\n");
576 ops |= PSP_MEM_TRAIN_RESTORE;
577 }
578
579 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
580 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
581 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
582 ops |= PSP_MEM_TRAIN_SAVE;
583 }
584
585 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
586 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
587 pcache[3] == p2c_header[3])) {
588 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
589 ops |= PSP_MEM_TRAIN_SAVE;
590 }
591
592 if ((ops & PSP_MEM_TRAIN_SAVE) &&
593 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
594 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
595 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
596 }
597
598 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
599 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
600 ops |= PSP_MEM_TRAIN_SAVE;
601 }
602
603 DRM_DEBUG("Memory training ops:%x.\n", ops);
604
605 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
606 /*
607 * Long training will encroach a certain amount on the bottom of VRAM;
608 * save the content from the bottom of VRAM to system memory
609 * before training, and restore it after training to avoid
610 * VRAM corruption.
611 */
612 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
613
614 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
615 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
616 adev->gmc.visible_vram_size,
617 adev->mman.aper_base_kaddr);
618 return -EINVAL;
619 }
620
621 buf = vmalloc(sz);
622 if (!buf) {
623 DRM_ERROR("failed to allocate system memory.\n");
624 return -ENOMEM;
625 }
626
627 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
628 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
629 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
630 if (ret) {
631 DRM_ERROR("Send long training msg failed.\n");
632 vfree(buf);
633 drm_dev_exit(idx);
634 return ret;
635 }
636
637 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
638 adev->hdp.funcs->flush_hdp(adev, NULL);
639 vfree(buf);
640 drm_dev_exit(idx);
641 } else {
642 vfree(buf);
643 return -ENODEV;
644 }
645 }
646
647 if (ops & PSP_MEM_TRAIN_SAVE) {
648 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
649 }
650
651 if (ops & PSP_MEM_TRAIN_RESTORE) {
652 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
653 }
654
655 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
656 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
657 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
658 if (ret) {
659 DRM_ERROR("send training msg failed.\n");
660 return ret;
661 }
662 }
663 ctx->training_cnt++;
664 return 0;
665}
666
667static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
668{
669 uint32_t data;
670 struct amdgpu_device *adev = psp->adev;
671
672 if (amdgpu_sriov_vf(adev))
673 data = psp->km_ring.ring_wptr;
674 else
675 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
676
677 return data;
678}
679
680static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
681{
682 struct amdgpu_device *adev = psp->adev;
683
684 if (amdgpu_sriov_vf(adev)) {
685 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
686 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
687 psp->km_ring.ring_wptr = value;
688 } else
689 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
690}
691
692static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
693{
694 struct amdgpu_device *adev = psp->adev;
695 uint32_t reg_status;
696 int ret, i = 0;
697
698 /*
699 * LFB address which is aligned to 1MB address and has to be
700 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
701 * register
702 */
703 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
704
705 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
706 0x80000000, 0x80000000, false);
707 if (ret)
708 return ret;
709
710 /* Fireup interrupt so PSP can pick up the address */
711 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
712
713 /* FW load takes very long time */
714 do {
715 msleep(1000);
716 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
717
718 if (reg_status & 0x80000000)
719 goto done;
720
721 } while (++i < USBC_PD_POLLING_LIMIT_S);
722
723 return -ETIME;
724done:
725
726 if ((reg_status & 0xFFFF) != 0) {
727 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
728 reg_status & 0xFFFF);
729 return -EIO;
730 }
731
732 return 0;
733}
734
735static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
736{
737 struct amdgpu_device *adev = psp->adev;
738 int ret;
739
740 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
741
742 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
743 0x80000000, 0x80000000, false);
744 if (!ret)
745 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
746
747 return ret;
748}
749
750static const struct psp_funcs psp_v11_0_funcs = {
751 .init_microcode = psp_v11_0_init_microcode,
752 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
753 .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
754 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
755 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
756 .ring_create = psp_v11_0_ring_create,
757 .ring_stop = psp_v11_0_ring_stop,
758 .ring_destroy = psp_v11_0_ring_destroy,
759 .mode1_reset = psp_v11_0_mode1_reset,
760 .mem_training = psp_v11_0_memory_training,
761 .ring_get_wptr = psp_v11_0_ring_get_wptr,
762 .ring_set_wptr = psp_v11_0_ring_set_wptr,
763 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
764 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
765};
766
767void psp_v11_0_set_psp_funcs(struct psp_context *psp)
768{
769 psp->funcs = &psp_v11_0_funcs;
770}
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25
26#include "amdgpu.h"
27#include "amdgpu_psp.h"
28#include "amdgpu_ucode.h"
29#include "soc15_common.h"
30#include "psp_v11_0.h"
31
32#include "mp/mp_11_0_offset.h"
33#include "mp/mp_11_0_sh_mask.h"
34#include "gc/gc_9_0_offset.h"
35#include "sdma0/sdma0_4_0_offset.h"
36#include "nbio/nbio_7_4_offset.h"
37
38#include "oss/osssys_4_0_offset.h"
39#include "oss/osssys_4_0_sh_mask.h"
40
41MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
42MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
43MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
44MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
45MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
46MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
47MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
48MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
49MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
50MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
51MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
52
53/* address block */
54#define smnMP1_FIRMWARE_FLAGS 0x3010024
55/* navi10 reg offset define */
56#define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
57#define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
58#define mmSDMA0_UCODE_ADDR_NV10 0x5880
59#define mmSDMA0_UCODE_DATA_NV10 0x5881
60
61static int psp_v11_0_init_microcode(struct psp_context *psp)
62{
63 struct amdgpu_device *adev = psp->adev;
64 const char *chip_name;
65 char fw_name[30];
66 int err = 0;
67 const struct psp_firmware_header_v1_0 *sos_hdr;
68 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
69 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
70 const struct psp_firmware_header_v1_0 *asd_hdr;
71 const struct ta_firmware_header_v1_0 *ta_hdr;
72
73 DRM_DEBUG("\n");
74
75 switch (adev->asic_type) {
76 case CHIP_VEGA20:
77 chip_name = "vega20";
78 break;
79 case CHIP_NAVI10:
80 chip_name = "navi10";
81 break;
82 case CHIP_NAVI14:
83 chip_name = "navi14";
84 break;
85 case CHIP_NAVI12:
86 chip_name = "navi12";
87 break;
88 case CHIP_ARCTURUS:
89 chip_name = "arcturus";
90 break;
91 default:
92 BUG();
93 }
94
95 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
96 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
97 if (err)
98 goto out;
99
100 err = amdgpu_ucode_validate(adev->psp.sos_fw);
101 if (err)
102 goto out;
103
104 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
105 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
106
107 switch (sos_hdr->header.header_version_major) {
108 case 1:
109 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
110 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
111 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
112 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
113 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
114 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
115 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
116 le32_to_cpu(sos_hdr->sos_offset_bytes);
117 if (sos_hdr->header.header_version_minor == 1) {
118 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
119 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
120 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
121 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
122 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
123 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
124 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
125 }
126 if (sos_hdr->header.header_version_minor == 2) {
127 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
128 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
129 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
130 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
131 }
132 break;
133 default:
134 dev_err(adev->dev,
135 "Unsupported psp sos firmware\n");
136 err = -EINVAL;
137 goto out;
138 }
139
140 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
141 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
142 if (err)
143 goto out1;
144
145 err = amdgpu_ucode_validate(adev->psp.asd_fw);
146 if (err)
147 goto out1;
148
149 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
150 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
151 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
152 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
153 adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
154 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
155
156 switch (adev->asic_type) {
157 case CHIP_VEGA20:
158 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
159 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
160 if (err) {
161 release_firmware(adev->psp.ta_fw);
162 adev->psp.ta_fw = NULL;
163 dev_info(adev->dev,
164 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
165 } else {
166 err = amdgpu_ucode_validate(adev->psp.ta_fw);
167 if (err)
168 goto out2;
169
170 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
171 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
172 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
173 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
174 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
175 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
176 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version);
177 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes);
178 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr +
179 le32_to_cpu(ta_hdr->ta_ras_offset_bytes);
180 }
181 break;
182 case CHIP_NAVI10:
183 case CHIP_NAVI14:
184 case CHIP_NAVI12:
185 case CHIP_ARCTURUS:
186 break;
187 default:
188 BUG();
189 }
190
191 return 0;
192
193out2:
194 release_firmware(adev->psp.ta_fw);
195 adev->psp.ta_fw = NULL;
196out1:
197 release_firmware(adev->psp.asd_fw);
198 adev->psp.asd_fw = NULL;
199out:
200 dev_err(adev->dev,
201 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
202 release_firmware(adev->psp.sos_fw);
203 adev->psp.sos_fw = NULL;
204
205 return err;
206}
207
208static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
209{
210 int ret;
211 uint32_t psp_gfxdrv_command_reg = 0;
212 struct amdgpu_device *adev = psp->adev;
213 uint32_t sol_reg;
214
215 /* Check tOS sign of life register to confirm sys driver and sOS
216 * are already been loaded.
217 */
218 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
219 if (sol_reg) {
220 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
221 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
222 return 0;
223 }
224
225 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
226 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
227 0x80000000, 0x80000000, false);
228 if (ret)
229 return ret;
230
231 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
232
233 /* Copy PSP KDB binary to memory */
234 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
235
236 /* Provide the sys driver to bootloader */
237 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
238 (uint32_t)(psp->fw_pri_mc_addr >> 20));
239 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
240 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
241 psp_gfxdrv_command_reg);
242
243 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/
244 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
245 0x80000000, 0x80000000, false);
246
247 return ret;
248}
249
250static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
251{
252 int ret;
253 uint32_t psp_gfxdrv_command_reg = 0;
254 struct amdgpu_device *adev = psp->adev;
255 uint32_t sol_reg;
256
257 /* Check sOS sign of life register to confirm sys driver and sOS
258 * are already been loaded.
259 */
260 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
261 if (sol_reg) {
262 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
263 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
264 return 0;
265 }
266
267 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
268 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
269 0x80000000, 0x80000000, false);
270 if (ret)
271 return ret;
272
273 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
274
275 /* Copy PSP System Driver binary to memory */
276 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
277
278 /* Provide the sys driver to bootloader */
279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
280 (uint32_t)(psp->fw_pri_mc_addr >> 20));
281 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
282 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
283 psp_gfxdrv_command_reg);
284
285 /* there might be handshake issue with hardware which needs delay */
286 mdelay(20);
287
288 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
289 0x80000000, 0x80000000, false);
290
291 return ret;
292}
293
294static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
295{
296 int ret;
297 unsigned int psp_gfxdrv_command_reg = 0;
298 struct amdgpu_device *adev = psp->adev;
299 uint32_t sol_reg;
300
301 /* Check sOS sign of life register to confirm sys driver and sOS
302 * are already been loaded.
303 */
304 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
305 if (sol_reg)
306 return 0;
307
308 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
310 0x80000000, 0x80000000, false);
311 if (ret)
312 return ret;
313
314 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
315
316 /* Copy Secure OS binary to PSP memory */
317 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
318
319 /* Provide the PSP secure OS to bootloader */
320 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
321 (uint32_t)(psp->fw_pri_mc_addr >> 20));
322 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
323 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
324 psp_gfxdrv_command_reg);
325
326 /* there might be handshake issue with hardware which needs delay */
327 mdelay(20);
328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
329 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
330 0, true);
331
332 return ret;
333}
334
335static void psp_v11_0_reroute_ih(struct psp_context *psp)
336{
337 struct amdgpu_device *adev = psp->adev;
338 uint32_t tmp;
339
340 /* Change IH ring for VMC */
341 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
342 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
343 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
344
345 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
346 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
347 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
348
349 mdelay(20);
350 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
351 0x80000000, 0x8000FFFF, false);
352
353 /* Change IH ring for UMC */
354 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
355 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
356
357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
358 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
359 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
360
361 mdelay(20);
362 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
363 0x80000000, 0x8000FFFF, false);
364}
365
366static int psp_v11_0_ring_init(struct psp_context *psp,
367 enum psp_ring_type ring_type)
368{
369 int ret = 0;
370 struct psp_ring *ring;
371 struct amdgpu_device *adev = psp->adev;
372
373 psp_v11_0_reroute_ih(psp);
374
375 ring = &psp->km_ring;
376
377 ring->ring_type = ring_type;
378
379 /* allocate 4k Page of Local Frame Buffer memory for ring */
380 ring->ring_size = 0x1000;
381 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
382 AMDGPU_GEM_DOMAIN_VRAM,
383 &adev->firmware.rbuf,
384 &ring->ring_mem_mc_addr,
385 (void **)&ring->ring_mem);
386 if (ret) {
387 ring->ring_size = 0;
388 return ret;
389 }
390
391 return 0;
392}
393
394static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
395{
396 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
397 return true;
398 return false;
399}
400
401static int psp_v11_0_ring_create(struct psp_context *psp,
402 enum psp_ring_type ring_type)
403{
404 int ret = 0;
405 unsigned int psp_ring_reg = 0;
406 struct psp_ring *ring = &psp->km_ring;
407 struct amdgpu_device *adev = psp->adev;
408
409 if (psp_v11_0_support_vmr_ring(psp)) {
410 /* Write low address of the ring to C2PMSG_102 */
411 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
413 /* Write high address of the ring to C2PMSG_103 */
414 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
415 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
416
417 /* Write the ring initialization command to C2PMSG_101 */
418 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
419 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
420
421 /* there might be handshake issue with hardware which needs delay */
422 mdelay(20);
423
424 /* Wait for response flag (bit 31) in C2PMSG_101 */
425 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
426 0x80000000, 0x8000FFFF, false);
427
428 } else {
429 /* Write low address of the ring to C2PMSG_69 */
430 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
431 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
432 /* Write high address of the ring to C2PMSG_70 */
433 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
434 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
435 /* Write size of ring to C2PMSG_71 */
436 psp_ring_reg = ring->ring_size;
437 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
438 /* Write the ring initialization command to C2PMSG_64 */
439 psp_ring_reg = ring_type;
440 psp_ring_reg = psp_ring_reg << 16;
441 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
442
443 /* there might be handshake issue with hardware which needs delay */
444 mdelay(20);
445
446 /* Wait for response flag (bit 31) in C2PMSG_64 */
447 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
448 0x80000000, 0x8000FFFF, false);
449 }
450
451 return ret;
452}
453
454static int psp_v11_0_ring_stop(struct psp_context *psp,
455 enum psp_ring_type ring_type)
456{
457 int ret = 0;
458 struct amdgpu_device *adev = psp->adev;
459
460 /* Write the ring destroy command*/
461 if (psp_v11_0_support_vmr_ring(psp))
462 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
463 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
464 else
465 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
466 GFX_CTRL_CMD_ID_DESTROY_RINGS);
467
468 /* there might be handshake issue with hardware which needs delay */
469 mdelay(20);
470
471 /* Wait for response flag (bit 31) */
472 if (psp_v11_0_support_vmr_ring(psp))
473 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
474 0x80000000, 0x80000000, false);
475 else
476 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
477 0x80000000, 0x80000000, false);
478
479 return ret;
480}
481
482static int psp_v11_0_ring_destroy(struct psp_context *psp,
483 enum psp_ring_type ring_type)
484{
485 int ret = 0;
486 struct psp_ring *ring = &psp->km_ring;
487 struct amdgpu_device *adev = psp->adev;
488
489 ret = psp_v11_0_ring_stop(psp, ring_type);
490 if (ret)
491 DRM_ERROR("Fail to stop psp ring\n");
492
493 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
494 &ring->ring_mem_mc_addr,
495 (void **)&ring->ring_mem);
496
497 return ret;
498}
499
500static int psp_v11_0_cmd_submit(struct psp_context *psp,
501 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
502 int index)
503{
504 unsigned int psp_write_ptr_reg = 0;
505 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
506 struct psp_ring *ring = &psp->km_ring;
507 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
508 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
509 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
510 struct amdgpu_device *adev = psp->adev;
511 uint32_t ring_size_dw = ring->ring_size / 4;
512 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
513
514 /* KM (GPCOM) prepare write pointer */
515 if (psp_v11_0_support_vmr_ring(psp))
516 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
517 else
518 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
519
520 /* Update KM RB frame pointer to new frame */
521 /* write_frame ptr increments by size of rb_frame in bytes */
522 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
523 if ((psp_write_ptr_reg % ring_size_dw) == 0)
524 write_frame = ring_buffer_start;
525 else
526 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
527 /* Check invalid write_frame ptr address */
528 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
529 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
530 ring_buffer_start, ring_buffer_end, write_frame);
531 DRM_ERROR("write_frame is pointing to address out of bounds\n");
532 return -EINVAL;
533 }
534
535 /* Initialize KM RB frame */
536 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
537
538 /* Update KM RB frame */
539 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
540 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
541 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
542 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
543 write_frame->fence_value = index;
544
545 /* Update the write Pointer in DWORDs */
546 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
547 if (psp_v11_0_support_vmr_ring(psp)) {
548 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
549 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
550 } else
551 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
552
553 return 0;
554}
555
556static int
557psp_v11_0_sram_map(struct amdgpu_device *adev,
558 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
559 unsigned int *sram_data_reg_offset,
560 enum AMDGPU_UCODE_ID ucode_id)
561{
562 int ret = 0;
563
564 switch (ucode_id) {
565/* TODO: needs to confirm */
566#if 0
567 case AMDGPU_UCODE_ID_SMC:
568 *sram_offset = 0;
569 *sram_addr_reg_offset = 0;
570 *sram_data_reg_offset = 0;
571 break;
572#endif
573
574 case AMDGPU_UCODE_ID_CP_CE:
575 *sram_offset = 0x0;
576 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
577 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
578 break;
579
580 case AMDGPU_UCODE_ID_CP_PFP:
581 *sram_offset = 0x0;
582 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
583 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
584 break;
585
586 case AMDGPU_UCODE_ID_CP_ME:
587 *sram_offset = 0x0;
588 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
589 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
590 break;
591
592 case AMDGPU_UCODE_ID_CP_MEC1:
593 *sram_offset = 0x10000;
594 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
595 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
596 break;
597
598 case AMDGPU_UCODE_ID_CP_MEC2:
599 *sram_offset = 0x10000;
600 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
601 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
602 break;
603
604 case AMDGPU_UCODE_ID_RLC_G:
605 *sram_offset = 0x2000;
606 if (adev->asic_type < CHIP_NAVI10) {
607 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
608 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
609 } else {
610 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10;
611 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10;
612 }
613 break;
614
615 case AMDGPU_UCODE_ID_SDMA0:
616 *sram_offset = 0x0;
617 if (adev->asic_type < CHIP_NAVI10) {
618 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
619 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
620 } else {
621 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10;
622 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10;
623 }
624 break;
625
626/* TODO: needs to confirm */
627#if 0
628 case AMDGPU_UCODE_ID_SDMA1:
629 *sram_offset = ;
630 *sram_addr_reg_offset = ;
631 break;
632
633 case AMDGPU_UCODE_ID_UVD:
634 *sram_offset = ;
635 *sram_addr_reg_offset = ;
636 break;
637
638 case AMDGPU_UCODE_ID_VCE:
639 *sram_offset = ;
640 *sram_addr_reg_offset = ;
641 break;
642#endif
643
644 case AMDGPU_UCODE_ID_MAXIMUM:
645 default:
646 ret = -EINVAL;
647 break;
648 }
649
650 return ret;
651}
652
653static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
654 struct amdgpu_firmware_info *ucode,
655 enum AMDGPU_UCODE_ID ucode_type)
656{
657 int err = 0;
658 unsigned int fw_sram_reg_val = 0;
659 unsigned int fw_sram_addr_reg_offset = 0;
660 unsigned int fw_sram_data_reg_offset = 0;
661 unsigned int ucode_size;
662 uint32_t *ucode_mem = NULL;
663 struct amdgpu_device *adev = psp->adev;
664
665 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
666 &fw_sram_data_reg_offset, ucode_type);
667 if (err)
668 return false;
669
670 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
671
672 ucode_size = ucode->ucode_size;
673 ucode_mem = (uint32_t *)ucode->kaddr;
674 while (ucode_size) {
675 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
676
677 if (*ucode_mem != fw_sram_reg_val)
678 return false;
679
680 ucode_mem++;
681 /* 4 bytes */
682 ucode_size -= 4;
683 }
684
685 return true;
686}
687
688static int psp_v11_0_mode1_reset(struct psp_context *psp)
689{
690 int ret;
691 uint32_t offset;
692 struct amdgpu_device *adev = psp->adev;
693
694 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
695
696 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
697
698 if (ret) {
699 DRM_INFO("psp is not working correctly before mode1 reset!\n");
700 return -EINVAL;
701 }
702
703 /*send the mode 1 reset command*/
704 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
705
706 msleep(500);
707
708 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
709
710 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
711
712 if (ret) {
713 DRM_INFO("psp mode 1 reset failed!\n");
714 return -EINVAL;
715 }
716
717 DRM_INFO("psp mode1 reset succeed \n");
718
719 return 0;
720}
721
722/* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
723 * For now, return success and hack the hive_id so high level code can
724 * start testing
725 */
726static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
727 int number_devices, struct psp_xgmi_topology_info *topology)
728{
729 struct ta_xgmi_shared_memory *xgmi_cmd;
730 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
731 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
732 int i;
733 int ret;
734
735 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
736 return -EINVAL;
737
738 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
739 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
740
741 /* Fill in the shared memory with topology information as input */
742 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
743 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
744 topology_info_input->num_nodes = number_devices;
745
746 for (i = 0; i < topology_info_input->num_nodes; i++) {
747 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
748 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
749 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
750 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
751 }
752
753 /* Invoke xgmi ta to get the topology information */
754 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
755 if (ret)
756 return ret;
757
758 /* Read the output topology information from the shared memory */
759 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
760 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
761 for (i = 0; i < topology->num_nodes; i++) {
762 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
763 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
764 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
765 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
766 }
767
768 return 0;
769}
770
771static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
772 int number_devices, struct psp_xgmi_topology_info *topology)
773{
774 struct ta_xgmi_shared_memory *xgmi_cmd;
775 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
776 int i;
777
778 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
779 return -EINVAL;
780
781 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
782 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
783
784 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
785 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
786 topology_info_input->num_nodes = number_devices;
787
788 for (i = 0; i < topology_info_input->num_nodes; i++) {
789 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
790 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
791 topology_info_input->nodes[i].is_sharing_enabled = 1;
792 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
793 }
794
795 /* Invoke xgmi ta to set topology information */
796 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
797}
798
799static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
800{
801 struct ta_xgmi_shared_memory *xgmi_cmd;
802 int ret;
803
804 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
805 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
806
807 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
808
809 /* Invoke xgmi ta to get hive id */
810 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
811 if (ret)
812 return ret;
813
814 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
815
816 return 0;
817}
818
819static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
820{
821 struct ta_xgmi_shared_memory *xgmi_cmd;
822 int ret;
823
824 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
825 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
826
827 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
828
829 /* Invoke xgmi ta to get the node id */
830 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
831 if (ret)
832 return ret;
833
834 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
835
836 return 0;
837}
838
839static int psp_v11_0_ras_trigger_error(struct psp_context *psp,
840 struct ta_ras_trigger_error_input *info)
841{
842 struct ta_ras_shared_memory *ras_cmd;
843 int ret;
844
845 if (!psp->ras.ras_initialized)
846 return -EINVAL;
847
848 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
849 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
850
851 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
852 ras_cmd->ras_in_message.trigger_error = *info;
853
854 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
855 if (ret)
856 return -EINVAL;
857
858 return ras_cmd->ras_status;
859}
860
861static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr)
862{
863#if 0
864 // not support yet.
865 struct ta_ras_shared_memory *ras_cmd;
866 int ret;
867
868 if (!psp->ras.ras_initialized)
869 return -EINVAL;
870
871 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
872 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
873
874 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON;
875 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr;
876
877 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
878 if (ret)
879 return -EINVAL;
880
881 return ras_cmd->ras_status;
882#else
883 return -EINVAL;
884#endif
885}
886
887static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
888{
889 return psp_rlc_autoload_start(psp);
890}
891
892static const struct psp_funcs psp_v11_0_funcs = {
893 .init_microcode = psp_v11_0_init_microcode,
894 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
895 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
896 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
897 .ring_init = psp_v11_0_ring_init,
898 .ring_create = psp_v11_0_ring_create,
899 .ring_stop = psp_v11_0_ring_stop,
900 .ring_destroy = psp_v11_0_ring_destroy,
901 .cmd_submit = psp_v11_0_cmd_submit,
902 .compare_sram_data = psp_v11_0_compare_sram_data,
903 .mode1_reset = psp_v11_0_mode1_reset,
904 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
905 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
906 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
907 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
908 .support_vmr_ring = psp_v11_0_support_vmr_ring,
909 .ras_trigger_error = psp_v11_0_ras_trigger_error,
910 .ras_cure_posion = psp_v11_0_ras_cure_posion,
911 .rlc_autoload_start = psp_v11_0_rlc_autoload_start,
912};
913
914void psp_v11_0_set_psp_funcs(struct psp_context *psp)
915{
916 psp->funcs = &psp_v11_0_funcs;
917}