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v6.2
   1/*
   2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 */
  24
  25#include <drm/amdgpu_drm.h>
  26#include <drm/drm_drv.h>
  27#include <drm/drm_fbdev_generic.h>
  28#include <drm/drm_gem.h>
  29#include <drm/drm_vblank.h>
  30#include <drm/drm_managed.h>
  31#include "amdgpu_drv.h"
  32
  33#include <drm/drm_pciids.h>
 
  34#include <linux/module.h>
 
  35#include <linux/pm_runtime.h>
  36#include <linux/vga_switcheroo.h>
  37#include <drm/drm_probe_helper.h>
  38#include <linux/mmu_notifier.h>
  39#include <linux/suspend.h>
  40#include <linux/cc_platform.h>
  41#include <linux/fb.h>
  42#include <linux/dynamic_debug.h>
  43
  44#include "amdgpu.h"
  45#include "amdgpu_irq.h"
  46#include "amdgpu_dma_buf.h"
  47#include "amdgpu_sched.h"
  48#include "amdgpu_fdinfo.h"
  49#include "amdgpu_amdkfd.h"
  50
  51#include "amdgpu_ras.h"
  52#include "amdgpu_xgmi.h"
  53#include "amdgpu_reset.h"
  54
  55/*
  56 * KMS wrapper.
  57 * - 3.0.0 - initial driver
  58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
  59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
  60 *           at the end of IBs.
  61 * - 3.3.0 - Add VM support for UVD on supported hardware.
  62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
  63 * - 3.5.0 - Add support for new UVD_NO_OP register.
  64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
  65 * - 3.7.0 - Add support for VCE clock list packet
  66 * - 3.8.0 - Add support raster config init in the kernel
  67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
  68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
  69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
  70 * - 3.12.0 - Add query for double offchip LDS buffers
  71 * - 3.13.0 - Add PRT support
  72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
  73 * - 3.15.0 - Export more gpu info for gfx9
  74 * - 3.16.0 - Add reserved vmid support
  75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
  76 * - 3.18.0 - Export gpu always on cu bitmap
  77 * - 3.19.0 - Add support for UVD MJPEG decode
  78 * - 3.20.0 - Add support for local BOs
  79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
  80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
  81 * - 3.23.0 - Add query for VRAM lost counter
  82 * - 3.24.0 - Add high priority compute support for gfx9
  83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
  86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
  89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
  91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
  92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
  93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
  94 * - 3.36.0 - Allow reading more status registers on si/cik
  95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
  96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
  97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
  98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
  99 * - 3.41.0 - Add video codec query
 100 * - 3.42.0 - Add 16bpc fixed point display support
 101 * - 3.43.0 - Add device hot plug/unplug support
 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
 103 * - 3.45.0 - Add context ioctl stable pstate interface
 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
 106 * - 3.48.0 - Add IP discovery version info to HW INFO
 107 *   3.49.0 - Add gang submit into CS IOCTL
 108 */
 109#define KMS_DRIVER_MAJOR	3
 110#define KMS_DRIVER_MINOR	49
 111#define KMS_DRIVER_PATCHLEVEL	0
 112
 113int amdgpu_vram_limit;
 114int amdgpu_vis_vram_limit;
 
 
 115int amdgpu_gart_size = -1; /* auto */
 116int amdgpu_gtt_size = -1; /* auto */
 117int amdgpu_moverate = -1; /* auto */
 
 
 118int amdgpu_audio = -1;
 119int amdgpu_disp_priority;
 120int amdgpu_hw_i2c;
 121int amdgpu_pcie_gen2 = -1;
 122int amdgpu_msi = -1;
 123char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
 124int amdgpu_dpm = -1;
 125int amdgpu_fw_load_type = -1;
 126int amdgpu_aspm = -1;
 127int amdgpu_runtime_pm = -1;
 128uint amdgpu_ip_block_mask = 0xffffffff;
 129int amdgpu_bapm = -1;
 130int amdgpu_deep_color;
 131int amdgpu_vm_size = -1;
 132int amdgpu_vm_fragment_size = -1;
 133int amdgpu_vm_block_size = -1;
 134int amdgpu_vm_fault_stop;
 135int amdgpu_vm_debug;
 136int amdgpu_vm_update_mode = -1;
 137int amdgpu_exp_hw_support;
 138int amdgpu_dc = -1;
 139int amdgpu_sched_jobs = 32;
 140int amdgpu_sched_hw_submission = 2;
 141uint amdgpu_pcie_gen_cap;
 142uint amdgpu_pcie_lane_cap;
 143u64 amdgpu_cg_mask = 0xffffffffffffffff;
 144uint amdgpu_pg_mask = 0xffffffff;
 145uint amdgpu_sdma_phase_quantum = 32;
 146char *amdgpu_disable_cu = NULL;
 147char *amdgpu_virtual_display = NULL;
 148
 149/*
 150 * OverDrive(bit 14) disabled by default
 151 * GFX DCS(bit 19) disabled by default
 152 */
 153uint amdgpu_pp_feature_mask = 0xfff7bfff;
 154uint amdgpu_force_long_training;
 155int amdgpu_job_hang_limit;
 156int amdgpu_lbpw = -1;
 157int amdgpu_compute_multipipe = -1;
 158int amdgpu_gpu_recovery = -1; /* auto */
 159int amdgpu_emu_mode;
 160uint amdgpu_smu_memory_pool_size;
 161int amdgpu_smu_pptable_id = -1;
 162/*
 163 * FBC (bit 0) disabled by default
 164 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
 165 *   - With this, for multiple monitors in sync(e.g. with the same model),
 166 *     mclk switching will be allowed. And the mclk will be not foced to the
 167 *     highest. That helps saving some idle power.
 168 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
 169 * PSR (bit 3) disabled by default
 170 * EDP NO POWER SEQUENCING (bit 4) disabled by default
 171 */
 172uint amdgpu_dc_feature_mask = 2;
 173uint amdgpu_dc_debug_mask;
 174uint amdgpu_dc_visual_confirm;
 175int amdgpu_async_gfx_ring = 1;
 176int amdgpu_mcbp;
 177int amdgpu_discovery = -1;
 178int amdgpu_mes;
 179int amdgpu_mes_kiq;
 180int amdgpu_noretry = -1;
 181int amdgpu_force_asic_type = -1;
 182int amdgpu_tmz = -1; /* auto */
 183uint amdgpu_freesync_vid_mode;
 184int amdgpu_reset_method = -1; /* auto */
 185int amdgpu_num_kcq = -1;
 186int amdgpu_smartshift_bias;
 187int amdgpu_use_xgmi_p2p = 1;
 188int amdgpu_vcnfw_log;
 189int amdgpu_sg_display = -1; /* auto */
 190
 191static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 192
 193DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
 194			"DRM_UT_CORE",
 195			"DRM_UT_DRIVER",
 196			"DRM_UT_KMS",
 197			"DRM_UT_PRIME",
 198			"DRM_UT_ATOMIC",
 199			"DRM_UT_VBL",
 200			"DRM_UT_STATE",
 201			"DRM_UT_LEASE",
 202			"DRM_UT_DP",
 203			"DRM_UT_DRMRES");
 204
 205struct amdgpu_mgpu_info mgpu_info = {
 206	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
 207	.delayed_reset_work = __DELAYED_WORK_INITIALIZER(
 208			mgpu_info.delayed_reset_work,
 209			amdgpu_drv_delayed_reset_work_handler, 0),
 210};
 211int amdgpu_ras_enable = -1;
 212uint amdgpu_ras_mask = 0xffffffff;
 213int amdgpu_bad_page_threshold = -1;
 214struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
 215	.timeout_fatal_disable = false,
 216	.period = 0x0, /* default to 0x0 (timeout disable) */
 217};
 218
 219/**
 220 * DOC: vramlimit (int)
 221 * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
 222 */
 223MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 224module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 225
 226/**
 227 * DOC: vis_vramlimit (int)
 228 * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
 229 */
 230MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
 231module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 232
 233/**
 234 * DOC: gartsize (uint)
 235 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
 236 * The default is -1 (The size depends on asic).
 237 */
 238MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
 239module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 240
 241/**
 242 * DOC: gttsize (int)
 243 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
 244 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
 245 */
 246MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
 247module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 248
 249/**
 250 * DOC: moverate (int)
 251 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
 252 */
 253MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
 254module_param_named(moverate, amdgpu_moverate, int, 0600);
 255
 256/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 257 * DOC: audio (int)
 258 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
 259 */
 260MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 261module_param_named(audio, amdgpu_audio, int, 0444);
 262
 263/**
 264 * DOC: disp_priority (int)
 265 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
 266 */
 267MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 268module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 269
 270/**
 271 * DOC: hw_i2c (int)
 272 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
 273 */
 274MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 275module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 276
 277/**
 278 * DOC: pcie_gen2 (int)
 279 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
 280 */
 281MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 282module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 283
 284/**
 285 * DOC: msi (int)
 286 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 287 */
 288MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 289module_param_named(msi, amdgpu_msi, int, 0444);
 290
 291/**
 292 * DOC: lockup_timeout (string)
 293 * Set GPU scheduler timeout value in ms.
 294 *
 295 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
 296 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
 297 * to the default timeout.
 298 *
 299 * - With one value specified, the setting will apply to all non-compute jobs.
 300 * - With multiple values specified, the first one will be for GFX.
 301 *   The second one is for Compute. The third and fourth ones are
 302 *   for SDMA and Video.
 303 *
 304 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
 305 * jobs is 10000. The timeout for compute is 60000.
 306 */
 307MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
 308		"for passthrough or sriov, 10000 for all jobs."
 309		" 0: keep default value. negative: infinity timeout), "
 310		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
 311		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
 312module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
 313
 314/**
 315 * DOC: dpm (int)
 316 * Override for dynamic power management setting
 317 * (0 = disable, 1 = enable)
 318 * The default is -1 (auto).
 319 */
 320MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 321module_param_named(dpm, amdgpu_dpm, int, 0444);
 322
 323/**
 324 * DOC: fw_load_type (int)
 325 * Set different firmware loading type for debugging, if supported.
 326 * Set to 0 to force direct loading if supported by the ASIC.  Set
 327 * to -1 to select the default loading mode for the ASIC, as defined
 328 * by the driver.  The default is -1 (auto).
 329 */
 330MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
 331module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 332
 333/**
 334 * DOC: aspm (int)
 335 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 336 */
 337MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 338module_param_named(aspm, amdgpu_aspm, int, 0444);
 339
 340/**
 341 * DOC: runpm (int)
 342 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
 343 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
 344 * Setting the value to 0 disables this functionality.
 345 */
 346MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
 347module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
 348
 349/**
 350 * DOC: ip_block_mask (uint)
 351 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
 352 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
 353 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
 354 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
 355 */
 356MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
 357module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
 358
 359/**
 360 * DOC: bapm (int)
 361 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
 362 * The default -1 (auto, enabled)
 363 */
 364MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
 365module_param_named(bapm, amdgpu_bapm, int, 0444);
 366
 367/**
 368 * DOC: deep_color (int)
 369 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
 370 */
 371MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 372module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 373
 374/**
 375 * DOC: vm_size (int)
 376 * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
 377 */
 378MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 379module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 380
 381/**
 382 * DOC: vm_fragment_size (int)
 383 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
 384 */
 385MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
 386module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
 387
 388/**
 389 * DOC: vm_block_size (int)
 390 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
 391 */
 392MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 393module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 394
 395/**
 396 * DOC: vm_fault_stop (int)
 397 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
 398 */
 399MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
 400module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
 401
 402/**
 403 * DOC: vm_debug (int)
 404 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
 405 */
 406MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
 407module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 408
 409/**
 410 * DOC: vm_update_mode (int)
 411 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
 412 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
 413 */
 414MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
 415module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
 416
 417/**
 418 * DOC: exp_hw_support (int)
 419 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
 420 */
 421MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
 422module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 423
 424/**
 425 * DOC: dc (int)
 426 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
 427 */
 428MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
 429module_param_named(dc, amdgpu_dc, int, 0444);
 430
 431/**
 432 * DOC: sched_jobs (int)
 433 * Override the max number of jobs supported in the sw queue. The default is 32.
 434 */
 435MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
 436module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
 437
 438/**
 439 * DOC: sched_hw_submission (int)
 440 * Override the max number of HW submissions. The default is 2.
 441 */
 442MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
 443module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
 444
 445/**
 446 * DOC: ppfeaturemask (hexint)
 447 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 448 * The default is the current set of stable power features.
 449 */
 450MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 451module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
 452
 453/**
 454 * DOC: forcelongtraining (uint)
 455 * Force long memory training in resume.
 456 * The default is zero, indicates short training in resume.
 457 */
 458MODULE_PARM_DESC(forcelongtraining, "force memory long training");
 459module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
 460
 461/**
 462 * DOC: pcie_gen_cap (uint)
 463 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 464 * The default is 0 (automatic for each asic).
 465 */
 466MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
 467module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
 468
 469/**
 470 * DOC: pcie_lane_cap (uint)
 471 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 472 * The default is 0 (automatic for each asic).
 473 */
 474MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
 475module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
 476
 477/**
 478 * DOC: cg_mask (ullong)
 479 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
 480 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
 481 */
 482MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
 483module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
 484
 485/**
 486 * DOC: pg_mask (uint)
 487 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
 488 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 489 */
 490MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
 491module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
 492
 493/**
 494 * DOC: sdma_phase_quantum (uint)
 495 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
 496 */
 497MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
 498module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
 499
 500/**
 501 * DOC: disable_cu (charp)
 502 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
 503 */
 504MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
 505module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
 506
 507/**
 508 * DOC: virtual_display (charp)
 509 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
 510 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
 511 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
 512 * device at 26:00.0. The default is NULL.
 513 */
 514MODULE_PARM_DESC(virtual_display,
 515		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
 516module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
 517
 518/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 519 * DOC: job_hang_limit (int)
 520 * Set how much time allow a job hang and not drop it. The default is 0.
 521 */
 522MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
 523module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
 524
 525/**
 526 * DOC: lbpw (int)
 527 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 528 */
 529MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
 530module_param_named(lbpw, amdgpu_lbpw, int, 0444);
 531
 532MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
 533module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
 534
 535/**
 536 * DOC: gpu_recovery (int)
 537 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
 538 */
 539MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
 540module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
 541
 542/**
 543 * DOC: emu_mode (int)
 544 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
 545 */
 546MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
 547module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 548
 549/**
 550 * DOC: ras_enable (int)
 551 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
 552 */
 553MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
 554module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
 555
 556/**
 557 * DOC: ras_mask (uint)
 558 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
 559 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
 560 */
 561MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
 562module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
 563
 564/**
 565 * DOC: timeout_fatal_disable (bool)
 566 * Disable Watchdog timeout fatal error event
 567 */
 568MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
 569module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
 570
 571/**
 572 * DOC: timeout_period (uint)
 573 * Modify the watchdog timeout max_cycles as (1 << period)
 574 */
 575MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
 576module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
 577
 578/**
 579 * DOC: si_support (int)
 580 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
 581 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 582 * otherwise using amdgpu driver.
 583 */
 584#ifdef CONFIG_DRM_AMDGPU_SI
 585
 586#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 587int amdgpu_si_support = 0;
 588MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
 589#else
 590int amdgpu_si_support = 1;
 591MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
 592#endif
 593
 594module_param_named(si_support, amdgpu_si_support, int, 0444);
 595#endif
 596
 597/**
 598 * DOC: cik_support (int)
 599 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
 600 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 601 * otherwise using amdgpu driver.
 602 */
 603#ifdef CONFIG_DRM_AMDGPU_CIK
 604
 605#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 606int amdgpu_cik_support = 0;
 607MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
 608#else
 609int amdgpu_cik_support = 1;
 610MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
 611#endif
 612
 613module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 614#endif
 615
 616/**
 617 * DOC: smu_memory_pool_size (uint)
 618 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
 619 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
 620 */
 621MODULE_PARM_DESC(smu_memory_pool_size,
 622	"reserve gtt for smu debug usage, 0 = disable,"
 623		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
 624module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 625
 626/**
 627 * DOC: async_gfx_ring (int)
 628 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
 629 */
 630MODULE_PARM_DESC(async_gfx_ring,
 631	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
 632module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
 633
 634/**
 635 * DOC: mcbp (int)
 636 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
 637 */
 638MODULE_PARM_DESC(mcbp,
 639	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
 640module_param_named(mcbp, amdgpu_mcbp, int, 0444);
 641
 642/**
 643 * DOC: discovery (int)
 644 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
 645 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
 646 */
 647MODULE_PARM_DESC(discovery,
 648	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
 649module_param_named(discovery, amdgpu_discovery, int, 0444);
 650
 651/**
 652 * DOC: mes (int)
 653 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
 654 * (0 = disabled (default), 1 = enabled)
 655 */
 656MODULE_PARM_DESC(mes,
 657	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
 658module_param_named(mes, amdgpu_mes, int, 0444);
 659
 660/**
 661 * DOC: mes_kiq (int)
 662 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
 663 * (0 = disabled (default), 1 = enabled)
 664 */
 665MODULE_PARM_DESC(mes_kiq,
 666	"Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
 667module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
 668
 669/**
 670 * DOC: noretry (int)
 671 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
 672 * do not support per-process XNACK this also disables retry page faults.
 673 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
 674 */
 675MODULE_PARM_DESC(noretry,
 676	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
 677module_param_named(noretry, amdgpu_noretry, int, 0644);
 678
 679/**
 680 * DOC: force_asic_type (int)
 681 * A non negative value used to specify the asic type for all supported GPUs.
 682 */
 683MODULE_PARM_DESC(force_asic_type,
 684	"A non negative value used to specify the asic type for all supported GPUs");
 685module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
 686
 687/**
 688 * DOC: use_xgmi_p2p (int)
 689 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
 690 */
 691MODULE_PARM_DESC(use_xgmi_p2p,
 692	"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
 693module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
 694
 695
 696#ifdef CONFIG_HSA_AMD
 697/**
 698 * DOC: sched_policy (int)
 699 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
 700 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
 701 * assigns queues to HQDs.
 702 */
 703int sched_policy = KFD_SCHED_POLICY_HWS;
 704module_param(sched_policy, int, 0444);
 705MODULE_PARM_DESC(sched_policy,
 706	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
 707
 708/**
 709 * DOC: hws_max_conc_proc (int)
 710 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
 711 * number of VMIDs assigned to the HWS, which is also the default.
 712 */
 713int hws_max_conc_proc = -1;
 714module_param(hws_max_conc_proc, int, 0444);
 715MODULE_PARM_DESC(hws_max_conc_proc,
 716	"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
 717
 718/**
 719 * DOC: cwsr_enable (int)
 720 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
 721 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
 722 * disables it.
 723 */
 724int cwsr_enable = 1;
 725module_param(cwsr_enable, int, 0444);
 726MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
 727
 728/**
 729 * DOC: max_num_of_queues_per_device (int)
 730 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
 731 * is 4096.
 732 */
 733int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
 734module_param(max_num_of_queues_per_device, int, 0444);
 735MODULE_PARM_DESC(max_num_of_queues_per_device,
 736	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
 737
 738/**
 739 * DOC: send_sigterm (int)
 740 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
 741 * but just print errors on dmesg. Setting 1 enables sending sigterm.
 742 */
 743int send_sigterm;
 744module_param(send_sigterm, int, 0444);
 745MODULE_PARM_DESC(send_sigterm,
 746	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
 747
 748/**
 749 * DOC: debug_largebar (int)
 750 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
 751 * system. This limits the VRAM size reported to ROCm applications to the visible
 752 * size, usually 256MB.
 753 * Default value is 0, diabled.
 754 */
 755int debug_largebar;
 756module_param(debug_largebar, int, 0444);
 757MODULE_PARM_DESC(debug_largebar,
 758	"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
 759
 760/**
 761 * DOC: ignore_crat (int)
 762 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
 763 * table to get information about AMD APUs. This option can serve as a workaround on
 764 * systems with a broken CRAT table.
 765 *
 766 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
 767 * whether use CRAT)
 768 */
 769int ignore_crat;
 770module_param(ignore_crat, int, 0444);
 771MODULE_PARM_DESC(ignore_crat,
 772	"Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
 773
 774/**
 775 * DOC: halt_if_hws_hang (int)
 776 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
 777 * Setting 1 enables halt on hang.
 778 */
 779int halt_if_hws_hang;
 780module_param(halt_if_hws_hang, int, 0644);
 781MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
 782
 783/**
 784 * DOC: hws_gws_support(bool)
 785 * Assume that HWS supports GWS barriers regardless of what firmware version
 786 * check says. Default value: false (rely on MEC2 firmware version check).
 
 787 */
 788bool hws_gws_support;
 789module_param(hws_gws_support, bool, 0444);
 790MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
 791
 792/**
 793  * DOC: queue_preemption_timeout_ms (int)
 794  * queue preemption timeout in ms (1 = Minimum, 9000 = default)
 795  */
 796int queue_preemption_timeout_ms = 9000;
 797module_param(queue_preemption_timeout_ms, int, 0644);
 798MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
 799
 800/**
 801 * DOC: debug_evictions(bool)
 802 * Enable extra debug messages to help determine the cause of evictions
 803 */
 804bool debug_evictions;
 805module_param(debug_evictions, bool, 0644);
 806MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
 807
 808/**
 809 * DOC: no_system_mem_limit(bool)
 810 * Disable system memory limit, to support multiple process shared memory
 811 */
 812bool no_system_mem_limit;
 813module_param(no_system_mem_limit, bool, 0644);
 814MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
 815
 816/**
 817 * DOC: no_queue_eviction_on_vm_fault (int)
 818 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
 819 */
 820int amdgpu_no_queue_eviction_on_vm_fault = 0;
 821MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
 822module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
 823#endif
 824
 825/**
 826 * DOC: pcie_p2p (bool)
 827 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
 828 */
 829#ifdef CONFIG_HSA_AMD_P2P
 830bool pcie_p2p = true;
 831module_param(pcie_p2p, bool, 0444);
 832MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
 833#endif
 834
 835/**
 836 * DOC: dcfeaturemask (uint)
 837 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 838 * The default is the current set of stable display features.
 839 */
 840MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
 841module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
 842
 843/**
 844 * DOC: dcdebugmask (uint)
 845 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 846 */
 847MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
 848module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
 849
 850MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
 851module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
 852
 853/**
 854 * DOC: abmlevel (uint)
 855 * Override the default ABM (Adaptive Backlight Management) level used for DC
 856 * enabled hardware. Requires DMCU to be supported and loaded.
 857 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
 858 * default. Values 1-4 control the maximum allowable brightness reduction via
 859 * the ABM algorithm, with 1 being the least reduction and 4 being the most
 860 * reduction.
 861 *
 862 * Defaults to 0, or disabled. Userspace can still override this level later
 863 * after boot.
 864 */
 865uint amdgpu_dm_abm_level;
 866MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
 867module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
 868
 869int amdgpu_backlight = -1;
 870MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
 871module_param_named(backlight, amdgpu_backlight, bint, 0444);
 872
 873/**
 874 * DOC: tmz (int)
 875 * Trusted Memory Zone (TMZ) is a method to protect data being written
 876 * to or read from memory.
 877 *
 878 * The default value: 0 (off).  TODO: change to auto till it is completed.
 879 */
 880MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
 881module_param_named(tmz, amdgpu_tmz, int, 0444);
 882
 883/**
 884 * DOC: freesync_video (uint)
 885 * Enable the optimization to adjust front porch timing to achieve seamless
 886 * mode change experience when setting a freesync supported mode for which full
 887 * modeset is not needed.
 888 *
 889 * The Display Core will add a set of modes derived from the base FreeSync
 890 * video mode into the corresponding connector's mode list based on commonly
 891 * used refresh rates and VRR range of the connected display, when users enable
 892 * this feature. From the userspace perspective, they can see a seamless mode
 893 * change experience when the change between different refresh rates under the
 894 * same resolution. Additionally, userspace applications such as Video playback
 895 * can read this modeset list and change the refresh rate based on the video
 896 * frame rate. Finally, the userspace can also derive an appropriate mode for a
 897 * particular refresh rate based on the FreeSync Mode and add it to the
 898 * connector's mode list.
 899 *
 900 * Note: This is an experimental feature.
 901 *
 902 * The default value: 0 (off).
 903 */
 904MODULE_PARM_DESC(
 905	freesync_video,
 906	"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
 907module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
 908
 909/**
 910 * DOC: reset_method (int)
 911 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
 912 */
 913MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
 914module_param_named(reset_method, amdgpu_reset_method, int, 0444);
 915
 916/**
 917 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
 918 * threshold value of faulty pages detected by RAS ECC, which may
 919 * result in the GPU entering bad status when the number of total
 920 * faulty pages by ECC exceeds the threshold value.
 921 */
 922MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
 923module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
 924
 925MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
 926module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
 927
 928/**
 929 * DOC: vcnfw_log (int)
 930 * Enable vcnfw log output for debugging, the default is disabled.
 931 */
 932MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
 933module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
 934
 935/**
 936 * DOC: sg_display (int)
 937 * Disable S/G (scatter/gather) display (i.e., display from system memory).
 938 * This option is only relevant on APUs.  Set this option to 0 to disable
 939 * S/G display if you experience flickering or other issues under memory
 940 * pressure and report the issue.
 941 */
 942MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
 943module_param_named(sg_display, amdgpu_sg_display, int, 0444);
 944
 945/**
 946 * DOC: smu_pptable_id (int)
 947 * Used to override pptable id. id = 0 use VBIOS pptable.
 948 * id > 0 use the soft pptable with specicfied id.
 949 */
 950MODULE_PARM_DESC(smu_pptable_id,
 951	"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
 952module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
 953
 954/* These devices are not supported by amdgpu.
 955 * They are supported by the mach64, r128, radeon drivers
 956 */
 957static const u16 amdgpu_unsupported_pciidlist[] = {
 958	/* mach64 */
 959	0x4354,
 960	0x4358,
 961	0x4554,
 962	0x4742,
 963	0x4744,
 964	0x4749,
 965	0x474C,
 966	0x474D,
 967	0x474E,
 968	0x474F,
 969	0x4750,
 970	0x4751,
 971	0x4752,
 972	0x4753,
 973	0x4754,
 974	0x4755,
 975	0x4756,
 976	0x4757,
 977	0x4758,
 978	0x4759,
 979	0x475A,
 980	0x4C42,
 981	0x4C44,
 982	0x4C47,
 983	0x4C49,
 984	0x4C4D,
 985	0x4C4E,
 986	0x4C50,
 987	0x4C51,
 988	0x4C52,
 989	0x4C53,
 990	0x5654,
 991	0x5655,
 992	0x5656,
 993	/* r128 */
 994	0x4c45,
 995	0x4c46,
 996	0x4d46,
 997	0x4d4c,
 998	0x5041,
 999	0x5042,
1000	0x5043,
1001	0x5044,
1002	0x5045,
1003	0x5046,
1004	0x5047,
1005	0x5048,
1006	0x5049,
1007	0x504A,
1008	0x504B,
1009	0x504C,
1010	0x504D,
1011	0x504E,
1012	0x504F,
1013	0x5050,
1014	0x5051,
1015	0x5052,
1016	0x5053,
1017	0x5054,
1018	0x5055,
1019	0x5056,
1020	0x5057,
1021	0x5058,
1022	0x5245,
1023	0x5246,
1024	0x5247,
1025	0x524b,
1026	0x524c,
1027	0x534d,
1028	0x5446,
1029	0x544C,
1030	0x5452,
1031	/* radeon */
1032	0x3150,
1033	0x3151,
1034	0x3152,
1035	0x3154,
1036	0x3155,
1037	0x3E50,
1038	0x3E54,
1039	0x4136,
1040	0x4137,
1041	0x4144,
1042	0x4145,
1043	0x4146,
1044	0x4147,
1045	0x4148,
1046	0x4149,
1047	0x414A,
1048	0x414B,
1049	0x4150,
1050	0x4151,
1051	0x4152,
1052	0x4153,
1053	0x4154,
1054	0x4155,
1055	0x4156,
1056	0x4237,
1057	0x4242,
1058	0x4336,
1059	0x4337,
1060	0x4437,
1061	0x4966,
1062	0x4967,
1063	0x4A48,
1064	0x4A49,
1065	0x4A4A,
1066	0x4A4B,
1067	0x4A4C,
1068	0x4A4D,
1069	0x4A4E,
1070	0x4A4F,
1071	0x4A50,
1072	0x4A54,
1073	0x4B48,
1074	0x4B49,
1075	0x4B4A,
1076	0x4B4B,
1077	0x4B4C,
1078	0x4C57,
1079	0x4C58,
1080	0x4C59,
1081	0x4C5A,
1082	0x4C64,
1083	0x4C66,
1084	0x4C67,
1085	0x4E44,
1086	0x4E45,
1087	0x4E46,
1088	0x4E47,
1089	0x4E48,
1090	0x4E49,
1091	0x4E4A,
1092	0x4E4B,
1093	0x4E50,
1094	0x4E51,
1095	0x4E52,
1096	0x4E53,
1097	0x4E54,
1098	0x4E56,
1099	0x5144,
1100	0x5145,
1101	0x5146,
1102	0x5147,
1103	0x5148,
1104	0x514C,
1105	0x514D,
1106	0x5157,
1107	0x5158,
1108	0x5159,
1109	0x515A,
1110	0x515E,
1111	0x5460,
1112	0x5462,
1113	0x5464,
1114	0x5548,
1115	0x5549,
1116	0x554A,
1117	0x554B,
1118	0x554C,
1119	0x554D,
1120	0x554E,
1121	0x554F,
1122	0x5550,
1123	0x5551,
1124	0x5552,
1125	0x5554,
1126	0x564A,
1127	0x564B,
1128	0x564F,
1129	0x5652,
1130	0x5653,
1131	0x5657,
1132	0x5834,
1133	0x5835,
1134	0x5954,
1135	0x5955,
1136	0x5974,
1137	0x5975,
1138	0x5960,
1139	0x5961,
1140	0x5962,
1141	0x5964,
1142	0x5965,
1143	0x5969,
1144	0x5a41,
1145	0x5a42,
1146	0x5a61,
1147	0x5a62,
1148	0x5b60,
1149	0x5b62,
1150	0x5b63,
1151	0x5b64,
1152	0x5b65,
1153	0x5c61,
1154	0x5c63,
1155	0x5d48,
1156	0x5d49,
1157	0x5d4a,
1158	0x5d4c,
1159	0x5d4d,
1160	0x5d4e,
1161	0x5d4f,
1162	0x5d50,
1163	0x5d52,
1164	0x5d57,
1165	0x5e48,
1166	0x5e4a,
1167	0x5e4b,
1168	0x5e4c,
1169	0x5e4d,
1170	0x5e4f,
1171	0x6700,
1172	0x6701,
1173	0x6702,
1174	0x6703,
1175	0x6704,
1176	0x6705,
1177	0x6706,
1178	0x6707,
1179	0x6708,
1180	0x6709,
1181	0x6718,
1182	0x6719,
1183	0x671c,
1184	0x671d,
1185	0x671f,
1186	0x6720,
1187	0x6721,
1188	0x6722,
1189	0x6723,
1190	0x6724,
1191	0x6725,
1192	0x6726,
1193	0x6727,
1194	0x6728,
1195	0x6729,
1196	0x6738,
1197	0x6739,
1198	0x673e,
1199	0x6740,
1200	0x6741,
1201	0x6742,
1202	0x6743,
1203	0x6744,
1204	0x6745,
1205	0x6746,
1206	0x6747,
1207	0x6748,
1208	0x6749,
1209	0x674A,
1210	0x6750,
1211	0x6751,
1212	0x6758,
1213	0x6759,
1214	0x675B,
1215	0x675D,
1216	0x675F,
1217	0x6760,
1218	0x6761,
1219	0x6762,
1220	0x6763,
1221	0x6764,
1222	0x6765,
1223	0x6766,
1224	0x6767,
1225	0x6768,
1226	0x6770,
1227	0x6771,
1228	0x6772,
1229	0x6778,
1230	0x6779,
1231	0x677B,
1232	0x6840,
1233	0x6841,
1234	0x6842,
1235	0x6843,
1236	0x6849,
1237	0x684C,
1238	0x6850,
1239	0x6858,
1240	0x6859,
1241	0x6880,
1242	0x6888,
1243	0x6889,
1244	0x688A,
1245	0x688C,
1246	0x688D,
1247	0x6898,
1248	0x6899,
1249	0x689b,
1250	0x689c,
1251	0x689d,
1252	0x689e,
1253	0x68a0,
1254	0x68a1,
1255	0x68a8,
1256	0x68a9,
1257	0x68b0,
1258	0x68b8,
1259	0x68b9,
1260	0x68ba,
1261	0x68be,
1262	0x68bf,
1263	0x68c0,
1264	0x68c1,
1265	0x68c7,
1266	0x68c8,
1267	0x68c9,
1268	0x68d8,
1269	0x68d9,
1270	0x68da,
1271	0x68de,
1272	0x68e0,
1273	0x68e1,
1274	0x68e4,
1275	0x68e5,
1276	0x68e8,
1277	0x68e9,
1278	0x68f1,
1279	0x68f2,
1280	0x68f8,
1281	0x68f9,
1282	0x68fa,
1283	0x68fe,
1284	0x7100,
1285	0x7101,
1286	0x7102,
1287	0x7103,
1288	0x7104,
1289	0x7105,
1290	0x7106,
1291	0x7108,
1292	0x7109,
1293	0x710A,
1294	0x710B,
1295	0x710C,
1296	0x710E,
1297	0x710F,
1298	0x7140,
1299	0x7141,
1300	0x7142,
1301	0x7143,
1302	0x7144,
1303	0x7145,
1304	0x7146,
1305	0x7147,
1306	0x7149,
1307	0x714A,
1308	0x714B,
1309	0x714C,
1310	0x714D,
1311	0x714E,
1312	0x714F,
1313	0x7151,
1314	0x7152,
1315	0x7153,
1316	0x715E,
1317	0x715F,
1318	0x7180,
1319	0x7181,
1320	0x7183,
1321	0x7186,
1322	0x7187,
1323	0x7188,
1324	0x718A,
1325	0x718B,
1326	0x718C,
1327	0x718D,
1328	0x718F,
1329	0x7193,
1330	0x7196,
1331	0x719B,
1332	0x719F,
1333	0x71C0,
1334	0x71C1,
1335	0x71C2,
1336	0x71C3,
1337	0x71C4,
1338	0x71C5,
1339	0x71C6,
1340	0x71C7,
1341	0x71CD,
1342	0x71CE,
1343	0x71D2,
1344	0x71D4,
1345	0x71D5,
1346	0x71D6,
1347	0x71DA,
1348	0x71DE,
1349	0x7200,
1350	0x7210,
1351	0x7211,
1352	0x7240,
1353	0x7243,
1354	0x7244,
1355	0x7245,
1356	0x7246,
1357	0x7247,
1358	0x7248,
1359	0x7249,
1360	0x724A,
1361	0x724B,
1362	0x724C,
1363	0x724D,
1364	0x724E,
1365	0x724F,
1366	0x7280,
1367	0x7281,
1368	0x7283,
1369	0x7284,
1370	0x7287,
1371	0x7288,
1372	0x7289,
1373	0x728B,
1374	0x728C,
1375	0x7290,
1376	0x7291,
1377	0x7293,
1378	0x7297,
1379	0x7834,
1380	0x7835,
1381	0x791e,
1382	0x791f,
1383	0x793f,
1384	0x7941,
1385	0x7942,
1386	0x796c,
1387	0x796d,
1388	0x796e,
1389	0x796f,
1390	0x9400,
1391	0x9401,
1392	0x9402,
1393	0x9403,
1394	0x9405,
1395	0x940A,
1396	0x940B,
1397	0x940F,
1398	0x94A0,
1399	0x94A1,
1400	0x94A3,
1401	0x94B1,
1402	0x94B3,
1403	0x94B4,
1404	0x94B5,
1405	0x94B9,
1406	0x9440,
1407	0x9441,
1408	0x9442,
1409	0x9443,
1410	0x9444,
1411	0x9446,
1412	0x944A,
1413	0x944B,
1414	0x944C,
1415	0x944E,
1416	0x9450,
1417	0x9452,
1418	0x9456,
1419	0x945A,
1420	0x945B,
1421	0x945E,
1422	0x9460,
1423	0x9462,
1424	0x946A,
1425	0x946B,
1426	0x947A,
1427	0x947B,
1428	0x9480,
1429	0x9487,
1430	0x9488,
1431	0x9489,
1432	0x948A,
1433	0x948F,
1434	0x9490,
1435	0x9491,
1436	0x9495,
1437	0x9498,
1438	0x949C,
1439	0x949E,
1440	0x949F,
1441	0x94C0,
1442	0x94C1,
1443	0x94C3,
1444	0x94C4,
1445	0x94C5,
1446	0x94C6,
1447	0x94C7,
1448	0x94C8,
1449	0x94C9,
1450	0x94CB,
1451	0x94CC,
1452	0x94CD,
1453	0x9500,
1454	0x9501,
1455	0x9504,
1456	0x9505,
1457	0x9506,
1458	0x9507,
1459	0x9508,
1460	0x9509,
1461	0x950F,
1462	0x9511,
1463	0x9515,
1464	0x9517,
1465	0x9519,
1466	0x9540,
1467	0x9541,
1468	0x9542,
1469	0x954E,
1470	0x954F,
1471	0x9552,
1472	0x9553,
1473	0x9555,
1474	0x9557,
1475	0x955f,
1476	0x9580,
1477	0x9581,
1478	0x9583,
1479	0x9586,
1480	0x9587,
1481	0x9588,
1482	0x9589,
1483	0x958A,
1484	0x958B,
1485	0x958C,
1486	0x958D,
1487	0x958E,
1488	0x958F,
1489	0x9590,
1490	0x9591,
1491	0x9593,
1492	0x9595,
1493	0x9596,
1494	0x9597,
1495	0x9598,
1496	0x9599,
1497	0x959B,
1498	0x95C0,
1499	0x95C2,
1500	0x95C4,
1501	0x95C5,
1502	0x95C6,
1503	0x95C7,
1504	0x95C9,
1505	0x95CC,
1506	0x95CD,
1507	0x95CE,
1508	0x95CF,
1509	0x9610,
1510	0x9611,
1511	0x9612,
1512	0x9613,
1513	0x9614,
1514	0x9615,
1515	0x9616,
1516	0x9640,
1517	0x9641,
1518	0x9642,
1519	0x9643,
1520	0x9644,
1521	0x9645,
1522	0x9647,
1523	0x9648,
1524	0x9649,
1525	0x964a,
1526	0x964b,
1527	0x964c,
1528	0x964e,
1529	0x964f,
1530	0x9710,
1531	0x9711,
1532	0x9712,
1533	0x9713,
1534	0x9714,
1535	0x9715,
1536	0x9802,
1537	0x9803,
1538	0x9804,
1539	0x9805,
1540	0x9806,
1541	0x9807,
1542	0x9808,
1543	0x9809,
1544	0x980A,
1545	0x9900,
1546	0x9901,
1547	0x9903,
1548	0x9904,
1549	0x9905,
1550	0x9906,
1551	0x9907,
1552	0x9908,
1553	0x9909,
1554	0x990A,
1555	0x990B,
1556	0x990C,
1557	0x990D,
1558	0x990E,
1559	0x990F,
1560	0x9910,
1561	0x9913,
1562	0x9917,
1563	0x9918,
1564	0x9919,
1565	0x9990,
1566	0x9991,
1567	0x9992,
1568	0x9993,
1569	0x9994,
1570	0x9995,
1571	0x9996,
1572	0x9997,
1573	0x9998,
1574	0x9999,
1575	0x999A,
1576	0x999B,
1577	0x999C,
1578	0x999D,
1579	0x99A0,
1580	0x99A2,
1581	0x99A4,
1582	/* radeon secondary ids */
1583	0x3171,
1584	0x3e70,
1585	0x4164,
1586	0x4165,
1587	0x4166,
1588	0x4168,
1589	0x4170,
1590	0x4171,
1591	0x4172,
1592	0x4173,
1593	0x496e,
1594	0x4a69,
1595	0x4a6a,
1596	0x4a6b,
1597	0x4a70,
1598	0x4a74,
1599	0x4b69,
1600	0x4b6b,
1601	0x4b6c,
1602	0x4c6e,
1603	0x4e64,
1604	0x4e65,
1605	0x4e66,
1606	0x4e67,
1607	0x4e68,
1608	0x4e69,
1609	0x4e6a,
1610	0x4e71,
1611	0x4f73,
1612	0x5569,
1613	0x556b,
1614	0x556d,
1615	0x556f,
1616	0x5571,
1617	0x5854,
1618	0x5874,
1619	0x5940,
1620	0x5941,
1621	0x5b72,
1622	0x5b73,
1623	0x5b74,
1624	0x5b75,
1625	0x5d44,
1626	0x5d45,
1627	0x5d6d,
1628	0x5d6f,
1629	0x5d72,
1630	0x5d77,
1631	0x5e6b,
1632	0x5e6d,
1633	0x7120,
1634	0x7124,
1635	0x7129,
1636	0x712e,
1637	0x712f,
1638	0x7162,
1639	0x7163,
1640	0x7166,
1641	0x7167,
1642	0x7172,
1643	0x7173,
1644	0x71a0,
1645	0x71a1,
1646	0x71a3,
1647	0x71a7,
1648	0x71bb,
1649	0x71e0,
1650	0x71e1,
1651	0x71e2,
1652	0x71e6,
1653	0x71e7,
1654	0x71f2,
1655	0x7269,
1656	0x726b,
1657	0x726e,
1658	0x72a0,
1659	0x72a8,
1660	0x72b1,
1661	0x72b3,
1662	0x793f,
1663};
1664
1665static const struct pci_device_id pciidlist[] = {
1666#ifdef  CONFIG_DRM_AMDGPU_SI
1667	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1668	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1669	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1670	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1671	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1672	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1673	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1674	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1675	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1676	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1677	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1678	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1679	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1680	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1681	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1682	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1683	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1684	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1685	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1686	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1687	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1688	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1689	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1690	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1691	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1692	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1693	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1694	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1695	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1696	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1697	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1698	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1699	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1700	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1701	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1702	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1703	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1704	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1705	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1706	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1707	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1708	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1709	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1710	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1711	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1712	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1713	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1714	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1715	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1716	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1717	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1718	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1719	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1720	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1721	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1722	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1723	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1724	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1725	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1726	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1727	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1728	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1729	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1730	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1731	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1732	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1733	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1734	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1735	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1736	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1737	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1738	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1739#endif
1740#ifdef CONFIG_DRM_AMDGPU_CIK
1741	/* Kaveri */
1742	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1743	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1744	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1745	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1746	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1747	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1748	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1749	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1750	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1751	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1752	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1753	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1754	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1755	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1756	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1757	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1758	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1759	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1760	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1761	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1762	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1763	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1764	/* Bonaire */
1765	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1766	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1767	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1768	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1769	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1770	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1771	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1772	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1773	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1774	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1775	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1776	/* Hawaii */
1777	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1778	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1779	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1780	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1781	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1782	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1783	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1784	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1785	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1786	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1787	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1788	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1789	/* Kabini */
1790	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1791	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1792	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1793	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1794	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1795	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1796	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1797	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1798	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1799	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1800	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1801	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1802	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1803	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1804	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1805	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1806	/* mullins */
1807	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1808	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1809	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1810	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1811	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1812	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1813	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1814	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1815	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1816	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1817	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1818	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1819	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1820	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1821	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1822	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1823#endif
1824	/* topaz */
1825	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1826	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1827	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1828	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1829	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1830	/* tonga */
1831	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1832	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1833	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1834	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1835	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1836	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1837	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1838	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1839	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1840	/* fiji */
1841	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1842	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1843	/* carrizo */
1844	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1845	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1846	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1847	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1848	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1849	/* stoney */
1850	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1851	/* Polaris11 */
1852	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1853	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1854	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1855	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1856	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1857	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1858	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1859	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1860	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1861	/* Polaris10 */
1862	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1863	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1864	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1865	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1866	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1867	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1868	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1869	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1870	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1871	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1872	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1873	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1874	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1875	/* Polaris12 */
1876	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1877	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1878	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1879	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1880	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1881	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1882	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1883	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1884	/* VEGAM */
1885	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1886	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1887	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1888	/* Vega 10 */
1889	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1890	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1891	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1892	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1893	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1894	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1895	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1896	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1897	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1898	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1899	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1900	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1901	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1902	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1903	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1904	/* Vega 12 */
1905	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1906	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1907	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1908	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1909	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1910	/* Vega 20 */
1911	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1912	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1913	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1914	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1915	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1916	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1917	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1918	/* Raven */
1919	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1920	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1921	/* Arcturus */
1922	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1923	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1924	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1925	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1926	/* Navi10 */
1927	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1928	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1929	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1930	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1931	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1932	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1933	{0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1934	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1935	/* Navi14 */
1936	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1937	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1938	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1939	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1940
1941	/* Renoir */
1942	{0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1943	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1944	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1945	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1946
1947	/* Navi12 */
1948	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1949	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1950
1951	/* Sienna_Cichlid */
1952	{0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1953	{0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1954	{0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1955	{0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1956	{0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1957	{0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1958	{0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1959	{0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1960	{0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1961	{0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1962	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1963	{0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1964	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1965
1966	/* Yellow Carp */
1967	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1968	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1969
1970	/* Navy_Flounder */
1971	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1972	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1973	{0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1974	{0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1975	{0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1976	{0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1977	{0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1978	{0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1979	{0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1980
1981	/* DIMGREY_CAVEFISH */
1982	{0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1983	{0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1984	{0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1985	{0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1986	{0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1987	{0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1988	{0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1989	{0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1990	{0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1991	{0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1992	{0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1993	{0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1994
1995	/* Aldebaran */
1996	{0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1997	{0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1998	{0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1999	{0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2000
2001	/* CYAN_SKILLFISH */
2002	{0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2003	{0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2004
2005	/* BEIGE_GOBY */
2006	{0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2007	{0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2008	{0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2009	{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2010	{0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2011	{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2012
2013	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2014	  .class = PCI_CLASS_DISPLAY_VGA << 8,
2015	  .class_mask = 0xffffff,
2016	  .driver_data = CHIP_IP_DISCOVERY },
2017
2018	{ PCI_DEVICE(0x1002, PCI_ANY_ID),
2019	  .class = PCI_CLASS_DISPLAY_OTHER << 8,
2020	  .class_mask = 0xffffff,
2021	  .driver_data = CHIP_IP_DISCOVERY },
2022
2023	{0, 0, 0}
2024};
2025
2026MODULE_DEVICE_TABLE(pci, pciidlist);
2027
2028static const struct drm_driver amdgpu_kms_driver;
2029
2030static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2031{
2032	struct pci_dev *p = NULL;
2033	int i;
2034
2035	/* 0 - GPU
2036	 * 1 - audio
2037	 * 2 - USB
2038	 * 3 - UCSI
2039	 */
2040	for (i = 1; i < 4; i++) {
2041		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2042						adev->pdev->bus->number, i);
2043		if (p) {
2044			pm_runtime_get_sync(&p->dev);
2045			pm_runtime_mark_last_busy(&p->dev);
2046			pm_runtime_put_autosuspend(&p->dev);
2047			pci_dev_put(p);
2048		}
2049	}
2050}
2051
2052static int amdgpu_pci_probe(struct pci_dev *pdev,
2053			    const struct pci_device_id *ent)
2054{
2055	struct drm_device *ddev;
2056	struct amdgpu_device *adev;
2057	unsigned long flags = ent->driver_data;
2058	int ret, retry = 0, i;
2059	bool supports_atomic = false;
2060
2061	/* skip devices which are owned by radeon */
2062	for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2063		if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2064			return -ENODEV;
2065	}
2066
2067	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2068		amdgpu_aspm = 0;
2069
2070	if (amdgpu_virtual_display ||
2071	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2072		supports_atomic = true;
2073
2074	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2075		DRM_INFO("This hardware requires experimental hardware support.\n"
2076			 "See modparam exp_hw_support\n");
2077		return -ENODEV;
2078	}
2079	/* differentiate between P10 and P11 asics with the same DID */
2080	if (pdev->device == 0x67FF &&
2081	    (pdev->revision == 0xE3 ||
2082	     pdev->revision == 0xE7 ||
2083	     pdev->revision == 0xF3 ||
2084	     pdev->revision == 0xF7)) {
2085		flags &= ~AMD_ASIC_MASK;
2086		flags |= CHIP_POLARIS10;
2087	}
2088
2089	/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2090	 * however, SME requires an indirect IOMMU mapping because the encryption
2091	 * bit is beyond the DMA mask of the chip.
2092	 */
2093	if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2094	    ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2095		dev_info(&pdev->dev,
2096			 "SME is not compatible with RAVEN\n");
2097		return -ENOTSUPP;
2098	}
2099
2100#ifdef CONFIG_DRM_AMDGPU_SI
2101	if (!amdgpu_si_support) {
2102		switch (flags & AMD_ASIC_MASK) {
2103		case CHIP_TAHITI:
2104		case CHIP_PITCAIRN:
2105		case CHIP_VERDE:
2106		case CHIP_OLAND:
2107		case CHIP_HAINAN:
2108			dev_info(&pdev->dev,
2109				 "SI support provided by radeon.\n");
2110			dev_info(&pdev->dev,
2111				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2112				);
2113			return -ENODEV;
2114		}
2115	}
2116#endif
2117#ifdef CONFIG_DRM_AMDGPU_CIK
2118	if (!amdgpu_cik_support) {
2119		switch (flags & AMD_ASIC_MASK) {
2120		case CHIP_KAVERI:
2121		case CHIP_BONAIRE:
2122		case CHIP_HAWAII:
2123		case CHIP_KABINI:
2124		case CHIP_MULLINS:
2125			dev_info(&pdev->dev,
2126				 "CIK support provided by radeon.\n");
2127			dev_info(&pdev->dev,
2128				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2129				);
2130			return -ENODEV;
2131		}
2132	}
2133#endif
2134
2135	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2136	if (IS_ERR(adev))
2137		return PTR_ERR(adev);
2138
2139	adev->dev  = &pdev->dev;
2140	adev->pdev = pdev;
2141	ddev = adev_to_drm(adev);
 
2142
2143	if (!supports_atomic)
2144		ddev->driver_features &= ~DRIVER_ATOMIC;
2145
2146	ret = pci_enable_device(pdev);
2147	if (ret)
2148		return ret;
2149
2150	pci_set_drvdata(pdev, ddev);
2151
2152	ret = amdgpu_driver_load_kms(adev, flags);
2153	if (ret)
2154		goto err_pci;
2155
2156retry_init:
2157	ret = drm_dev_register(ddev, flags);
2158	if (ret == -EAGAIN && ++retry <= 3) {
2159		DRM_INFO("retry init %d\n", retry);
2160		/* Don't request EX mode too frequently which is attacking */
2161		msleep(5000);
2162		goto retry_init;
2163	} else if (ret) {
2164		goto err_pci;
2165	}
2166
2167	/*
2168	 * 1. don't init fbdev on hw without DCE
2169	 * 2. don't init fbdev if there are no connectors
2170	 */
2171	if (adev->mode_info.mode_config_initialized &&
2172	    !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2173		/* select 8 bpp console on low vram cards */
2174		if (adev->gmc.real_vram_size <= (32*1024*1024))
2175			drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2176		else
2177			drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2178	}
2179
2180	ret = amdgpu_debugfs_init(adev);
2181	if (ret)
2182		DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2183
2184	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2185		/* only need to skip on ATPX */
2186		if (amdgpu_device_supports_px(ddev))
2187			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2188		/* we want direct complete for BOCO */
2189		if (amdgpu_device_supports_boco(ddev))
2190			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2191						DPM_FLAG_SMART_SUSPEND |
2192						DPM_FLAG_MAY_SKIP_RESUME);
2193		pm_runtime_use_autosuspend(ddev->dev);
2194		pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2195
2196		pm_runtime_allow(ddev->dev);
2197
2198		pm_runtime_mark_last_busy(ddev->dev);
2199		pm_runtime_put_autosuspend(ddev->dev);
2200
2201		/*
2202		 * For runpm implemented via BACO, PMFW will handle the
2203		 * timing for BACO in and out:
2204		 *   - put ASIC into BACO state only when both video and
2205		 *     audio functions are in D3 state.
2206		 *   - pull ASIC out of BACO state when either video or
2207		 *     audio function is in D0 state.
2208		 * Also, at startup, PMFW assumes both functions are in
2209		 * D0 state.
2210		 *
2211		 * So if snd driver was loaded prior to amdgpu driver
2212		 * and audio function was put into D3 state, there will
2213		 * be no PMFW-aware D-state transition(D0->D3) on runpm
2214		 * suspend. Thus the BACO will be not correctly kicked in.
2215		 *
2216		 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2217		 * into D0 state. Then there will be a PMFW-aware D-state
2218		 * transition(D0->D3) on runpm suspend.
2219		 */
2220		if (amdgpu_device_supports_baco(ddev) &&
2221		    !(adev->flags & AMD_IS_APU) &&
2222		    (adev->asic_type >= CHIP_NAVI10))
2223			amdgpu_get_secondary_funcs(adev);
2224	}
2225
2226	return 0;
2227
2228err_pci:
2229	pci_disable_device(pdev);
 
 
2230	return ret;
2231}
2232
2233static void
2234amdgpu_pci_remove(struct pci_dev *pdev)
2235{
2236	struct drm_device *dev = pci_get_drvdata(pdev);
2237	struct amdgpu_device *adev = drm_to_adev(dev);
2238
2239	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2240		pm_runtime_get_sync(dev->dev);
2241		pm_runtime_forbid(dev->dev);
2242	}
2243
2244	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2245	    !amdgpu_sriov_vf(adev)) {
2246		bool need_to_reset_gpu = false;
2247
2248		if (adev->gmc.xgmi.num_physical_nodes > 1) {
2249			struct amdgpu_hive_info *hive;
2250
2251			hive = amdgpu_get_xgmi_hive(adev);
2252			if (hive->device_remove_count == 0)
2253				need_to_reset_gpu = true;
2254			hive->device_remove_count++;
2255			amdgpu_put_xgmi_hive(hive);
2256		} else {
2257			need_to_reset_gpu = true;
2258		}
2259
2260		/* Workaround for ASICs need to reset SMU.
2261		 * Called only when the first device is removed.
2262		 */
2263		if (need_to_reset_gpu) {
2264			struct amdgpu_reset_context reset_context;
2265
2266			adev->shutdown = true;
2267			memset(&reset_context, 0, sizeof(reset_context));
2268			reset_context.method = AMD_RESET_METHOD_NONE;
2269			reset_context.reset_req_dev = adev;
2270			set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2271			set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2272			amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2273		}
2274	}
2275
2276	amdgpu_driver_unload_kms(dev);
2277
 
2278	drm_dev_unplug(dev);
2279
2280	/*
2281	 * Flush any in flight DMA operations from device.
2282	 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2283	 * StatusTransactions Pending bit.
2284	 */
2285	pci_disable_device(pdev);
2286	pci_wait_for_pending_transaction(pdev);
2287}
2288
2289static void
2290amdgpu_pci_shutdown(struct pci_dev *pdev)
2291{
2292	struct drm_device *dev = pci_get_drvdata(pdev);
2293	struct amdgpu_device *adev = drm_to_adev(dev);
2294
2295	if (amdgpu_ras_intr_triggered())
2296		return;
2297
2298	/* if we are running in a VM, make sure the device
2299	 * torn down properly on reboot/shutdown.
2300	 * unfortunately we can't detect certain
2301	 * hypervisors so just do this all the time.
2302	 */
2303	if (!amdgpu_passthrough(adev))
2304		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2305	amdgpu_device_ip_suspend(adev);
2306	adev->mp1_state = PP_MP1_STATE_NONE;
2307}
2308
2309/**
2310 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2311 *
2312 * @work: work_struct.
2313 */
2314static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2315{
2316	struct list_head device_list;
2317	struct amdgpu_device *adev;
2318	int i, r;
2319	struct amdgpu_reset_context reset_context;
2320
2321	memset(&reset_context, 0, sizeof(reset_context));
2322
2323	mutex_lock(&mgpu_info.mutex);
2324	if (mgpu_info.pending_reset == true) {
2325		mutex_unlock(&mgpu_info.mutex);
2326		return;
2327	}
2328	mgpu_info.pending_reset = true;
2329	mutex_unlock(&mgpu_info.mutex);
2330
2331	/* Use a common context, just need to make sure full reset is done */
2332	reset_context.method = AMD_RESET_METHOD_NONE;
2333	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2334
2335	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2336		adev = mgpu_info.gpu_ins[i].adev;
2337		reset_context.reset_req_dev = adev;
2338		r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2339		if (r) {
2340			dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2341				r, adev_to_drm(adev)->unique);
2342		}
2343		if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2344			r = -EALREADY;
2345	}
2346	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2347		adev = mgpu_info.gpu_ins[i].adev;
2348		flush_work(&adev->xgmi_reset_work);
2349		adev->gmc.xgmi.pending_reset = false;
2350	}
2351
2352	/* reset function will rebuild the xgmi hive info , clear it now */
2353	for (i = 0; i < mgpu_info.num_dgpu; i++)
2354		amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2355
2356	INIT_LIST_HEAD(&device_list);
2357
2358	for (i = 0; i < mgpu_info.num_dgpu; i++)
2359		list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2360
2361	/* unregister the GPU first, reset function will add them back */
2362	list_for_each_entry(adev, &device_list, reset_list)
2363		amdgpu_unregister_gpu_instance(adev);
2364
2365	/* Use a common context, just need to make sure full reset is done */
2366	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2367	r = amdgpu_do_asic_reset(&device_list, &reset_context);
2368
2369	if (r) {
2370		DRM_ERROR("reinit gpus failure");
2371		return;
2372	}
2373	for (i = 0; i < mgpu_info.num_dgpu; i++) {
2374		adev = mgpu_info.gpu_ins[i].adev;
2375		if (!adev->kfd.init_complete)
2376			amdgpu_amdkfd_device_init(adev);
2377		amdgpu_ttm_set_buffer_funcs_status(adev, true);
2378	}
2379	return;
2380}
2381
2382static int amdgpu_pmops_prepare(struct device *dev)
2383{
2384	struct drm_device *drm_dev = dev_get_drvdata(dev);
2385	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2386
2387	/* Return a positive number here so
2388	 * DPM_FLAG_SMART_SUSPEND works properly
2389	 */
2390	if (amdgpu_device_supports_boco(drm_dev))
2391		return pm_runtime_suspended(dev);
2392
2393	/* if we will not support s3 or s2i for the device
2394	 *  then skip suspend
2395	 */
2396	if (!amdgpu_acpi_is_s0ix_active(adev) &&
2397	    !amdgpu_acpi_is_s3_active(adev))
2398		return 1;
2399
2400	return 0;
2401}
2402
2403static void amdgpu_pmops_complete(struct device *dev)
2404{
2405	/* nothing to do */
2406}
2407
2408static int amdgpu_pmops_suspend(struct device *dev)
2409{
2410	struct drm_device *drm_dev = dev_get_drvdata(dev);
2411	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2412
2413	if (amdgpu_acpi_is_s0ix_active(adev))
2414		adev->in_s0ix = true;
2415	else
2416		adev->in_s3 = true;
2417	return amdgpu_device_suspend(drm_dev, true);
2418}
2419
2420static int amdgpu_pmops_suspend_noirq(struct device *dev)
2421{
2422	struct drm_device *drm_dev = dev_get_drvdata(dev);
2423	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2424
2425	if (amdgpu_acpi_should_gpu_reset(adev))
2426		return amdgpu_asic_reset(adev);
2427
2428	return 0;
2429}
2430
2431static int amdgpu_pmops_resume(struct device *dev)
2432{
2433	struct drm_device *drm_dev = dev_get_drvdata(dev);
2434	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2435	int r;
2436
2437	/* Avoids registers access if device is physically gone */
2438	if (!pci_device_is_present(adev->pdev))
2439		adev->no_hw_access = true;
2440
2441	r = amdgpu_device_resume(drm_dev, true);
2442	if (amdgpu_acpi_is_s0ix_active(adev))
2443		adev->in_s0ix = false;
2444	else
2445		adev->in_s3 = false;
2446	return r;
2447}
2448
2449static int amdgpu_pmops_freeze(struct device *dev)
2450{
2451	struct drm_device *drm_dev = dev_get_drvdata(dev);
2452	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2453	int r;
2454
2455	adev->in_s4 = true;
2456	r = amdgpu_device_suspend(drm_dev, true);
2457	adev->in_s4 = false;
2458	if (r)
2459		return r;
2460	return amdgpu_asic_reset(adev);
2461}
2462
2463static int amdgpu_pmops_thaw(struct device *dev)
2464{
2465	struct drm_device *drm_dev = dev_get_drvdata(dev);
2466
2467	return amdgpu_device_resume(drm_dev, true);
2468}
2469
2470static int amdgpu_pmops_poweroff(struct device *dev)
2471{
2472	struct drm_device *drm_dev = dev_get_drvdata(dev);
2473
2474	return amdgpu_device_suspend(drm_dev, true);
2475}
2476
2477static int amdgpu_pmops_restore(struct device *dev)
2478{
2479	struct drm_device *drm_dev = dev_get_drvdata(dev);
2480
2481	return amdgpu_device_resume(drm_dev, true);
2482}
2483
2484static int amdgpu_runtime_idle_check_display(struct device *dev)
2485{
2486	struct pci_dev *pdev = to_pci_dev(dev);
2487	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2488	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2489
2490	if (adev->mode_info.num_crtc) {
2491		struct drm_connector *list_connector;
2492		struct drm_connector_list_iter iter;
2493		int ret = 0;
2494
2495		/* XXX: Return busy if any displays are connected to avoid
2496		 * possible display wakeups after runtime resume due to
2497		 * hotplug events in case any displays were connected while
2498		 * the GPU was in suspend.  Remove this once that is fixed.
2499		 */
2500		mutex_lock(&drm_dev->mode_config.mutex);
2501		drm_connector_list_iter_begin(drm_dev, &iter);
2502		drm_for_each_connector_iter(list_connector, &iter) {
2503			if (list_connector->status == connector_status_connected) {
2504				ret = -EBUSY;
2505				break;
2506			}
2507		}
2508		drm_connector_list_iter_end(&iter);
2509		mutex_unlock(&drm_dev->mode_config.mutex);
2510
2511		if (ret)
2512			return ret;
2513
2514		if (adev->dc_enabled) {
2515			struct drm_crtc *crtc;
2516
2517			drm_for_each_crtc(crtc, drm_dev) {
2518				drm_modeset_lock(&crtc->mutex, NULL);
2519				if (crtc->state->active)
2520					ret = -EBUSY;
2521				drm_modeset_unlock(&crtc->mutex);
2522				if (ret < 0)
2523					break;
2524			}
2525		} else {
2526			mutex_lock(&drm_dev->mode_config.mutex);
2527			drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2528
2529			drm_connector_list_iter_begin(drm_dev, &iter);
2530			drm_for_each_connector_iter(list_connector, &iter) {
2531				if (list_connector->dpms ==  DRM_MODE_DPMS_ON) {
2532					ret = -EBUSY;
2533					break;
2534				}
2535			}
2536
2537			drm_connector_list_iter_end(&iter);
2538
2539			drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2540			mutex_unlock(&drm_dev->mode_config.mutex);
2541		}
2542		if (ret)
2543			return ret;
2544	}
2545
2546	return 0;
2547}
2548
2549static int amdgpu_pmops_runtime_suspend(struct device *dev)
2550{
2551	struct pci_dev *pdev = to_pci_dev(dev);
2552	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2553	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2554	int ret, i;
2555
2556	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2557		pm_runtime_forbid(dev);
2558		return -EBUSY;
2559	}
2560
2561	ret = amdgpu_runtime_idle_check_display(dev);
2562	if (ret)
2563		return ret;
2564
2565	/* wait for all rings to drain before suspending */
2566	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2567		struct amdgpu_ring *ring = adev->rings[i];
2568		if (ring && ring->sched.ready) {
2569			ret = amdgpu_fence_wait_empty(ring);
2570			if (ret)
2571				return -EBUSY;
2572		}
2573	}
2574
2575	adev->in_runpm = true;
2576	if (amdgpu_device_supports_px(drm_dev))
2577		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2578
2579	/*
2580	 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2581	 * proper cleanups and put itself into a state ready for PNP. That
2582	 * can address some random resuming failure observed on BOCO capable
2583	 * platforms.
2584	 * TODO: this may be also needed for PX capable platform.
2585	 */
2586	if (amdgpu_device_supports_boco(drm_dev))
2587		adev->mp1_state = PP_MP1_STATE_UNLOAD;
2588
2589	ret = amdgpu_device_suspend(drm_dev, false);
2590	if (ret) {
2591		adev->in_runpm = false;
2592		if (amdgpu_device_supports_boco(drm_dev))
2593			adev->mp1_state = PP_MP1_STATE_NONE;
2594		return ret;
2595	}
2596
2597	if (amdgpu_device_supports_boco(drm_dev))
2598		adev->mp1_state = PP_MP1_STATE_NONE;
2599
2600	if (amdgpu_device_supports_px(drm_dev)) {
2601		/* Only need to handle PCI state in the driver for ATPX
2602		 * PCI core handles it for _PR3.
2603		 */
2604		amdgpu_device_cache_pci_state(pdev);
2605		pci_disable_device(pdev);
2606		pci_ignore_hotplug(pdev);
2607		pci_set_power_state(pdev, PCI_D3cold);
2608		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2609	} else if (amdgpu_device_supports_boco(drm_dev)) {
2610		/* nothing to do */
2611	} else if (amdgpu_device_supports_baco(drm_dev)) {
2612		amdgpu_device_baco_enter(drm_dev);
2613	}
2614
2615	dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2616
2617	return 0;
2618}
2619
2620static int amdgpu_pmops_runtime_resume(struct device *dev)
2621{
2622	struct pci_dev *pdev = to_pci_dev(dev);
2623	struct drm_device *drm_dev = pci_get_drvdata(pdev);
2624	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2625	int ret;
2626
2627	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2628		return -EINVAL;
2629
2630	/* Avoids registers access if device is physically gone */
2631	if (!pci_device_is_present(adev->pdev))
2632		adev->no_hw_access = true;
2633
2634	if (amdgpu_device_supports_px(drm_dev)) {
2635		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2636
2637		/* Only need to handle PCI state in the driver for ATPX
2638		 * PCI core handles it for _PR3.
2639		 */
2640		pci_set_power_state(pdev, PCI_D0);
2641		amdgpu_device_load_pci_state(pdev);
2642		ret = pci_enable_device(pdev);
2643		if (ret)
2644			return ret;
2645		pci_set_master(pdev);
2646	} else if (amdgpu_device_supports_boco(drm_dev)) {
2647		/* Only need to handle PCI state in the driver for ATPX
2648		 * PCI core handles it for _PR3.
2649		 */
2650		pci_set_master(pdev);
2651	} else if (amdgpu_device_supports_baco(drm_dev)) {
2652		amdgpu_device_baco_exit(drm_dev);
2653	}
2654	ret = amdgpu_device_resume(drm_dev, false);
2655	if (ret) {
2656		if (amdgpu_device_supports_px(drm_dev))
2657			pci_disable_device(pdev);
2658		return ret;
2659	}
2660
2661	if (amdgpu_device_supports_px(drm_dev))
2662		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2663	adev->in_runpm = false;
2664	return 0;
2665}
2666
2667static int amdgpu_pmops_runtime_idle(struct device *dev)
2668{
2669	struct drm_device *drm_dev = dev_get_drvdata(dev);
2670	struct amdgpu_device *adev = drm_to_adev(drm_dev);
2671	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2672	int ret = 1;
2673
2674	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2675		pm_runtime_forbid(dev);
2676		return -EBUSY;
2677	}
2678
2679	ret = amdgpu_runtime_idle_check_display(dev);
 
 
 
 
 
2680
2681	pm_runtime_mark_last_busy(dev);
2682	pm_runtime_autosuspend(dev);
2683	return ret;
 
2684}
2685
2686long amdgpu_drm_ioctl(struct file *filp,
2687		      unsigned int cmd, unsigned long arg)
2688{
2689	struct drm_file *file_priv = filp->private_data;
2690	struct drm_device *dev;
2691	long ret;
2692	dev = file_priv->minor->dev;
2693	ret = pm_runtime_get_sync(dev->dev);
2694	if (ret < 0)
2695		goto out;
2696
2697	ret = drm_ioctl(filp, cmd, arg);
2698
2699	pm_runtime_mark_last_busy(dev->dev);
2700out:
2701	pm_runtime_put_autosuspend(dev->dev);
2702	return ret;
2703}
2704
2705static const struct dev_pm_ops amdgpu_pm_ops = {
2706	.prepare = amdgpu_pmops_prepare,
2707	.complete = amdgpu_pmops_complete,
2708	.suspend = amdgpu_pmops_suspend,
2709	.suspend_noirq = amdgpu_pmops_suspend_noirq,
2710	.resume = amdgpu_pmops_resume,
2711	.freeze = amdgpu_pmops_freeze,
2712	.thaw = amdgpu_pmops_thaw,
2713	.poweroff = amdgpu_pmops_poweroff,
2714	.restore = amdgpu_pmops_restore,
2715	.runtime_suspend = amdgpu_pmops_runtime_suspend,
2716	.runtime_resume = amdgpu_pmops_runtime_resume,
2717	.runtime_idle = amdgpu_pmops_runtime_idle,
2718};
2719
2720static int amdgpu_flush(struct file *f, fl_owner_t id)
2721{
2722	struct drm_file *file_priv = f->private_data;
2723	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2724	long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2725
2726	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2727	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2728
2729	return timeout >= 0 ? 0 : timeout;
2730}
2731
2732static const struct file_operations amdgpu_driver_kms_fops = {
2733	.owner = THIS_MODULE,
2734	.open = drm_open,
2735	.flush = amdgpu_flush,
2736	.release = drm_release,
2737	.unlocked_ioctl = amdgpu_drm_ioctl,
2738	.mmap = drm_gem_mmap,
2739	.poll = drm_poll,
2740	.read = drm_read,
2741#ifdef CONFIG_COMPAT
2742	.compat_ioctl = amdgpu_kms_compat_ioctl,
2743#endif
2744#ifdef CONFIG_PROC_FS
2745	.show_fdinfo = amdgpu_show_fdinfo
2746#endif
2747};
2748
2749int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2750{
2751	struct drm_file *file;
2752
2753	if (!filp)
2754		return -EINVAL;
2755
2756	if (filp->f_op != &amdgpu_driver_kms_fops) {
2757		return -EINVAL;
2758	}
2759
2760	file = filp->private_data;
2761	*fpriv = file->driver_priv;
2762	return 0;
2763}
2764
2765const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2766	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2767	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2768	DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2769	DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2770	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2771	DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2772	/* KMS */
2773	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2774	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2775	DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2776	DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2777	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2778	DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2779	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2780	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2781	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2782	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2783};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2784
2785static const struct drm_driver amdgpu_kms_driver = {
2786	.driver_features =
2787	    DRIVER_ATOMIC |
2788	    DRIVER_GEM |
2789	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2790	    DRIVER_SYNCOBJ_TIMELINE,
2791	.open = amdgpu_driver_open_kms,
2792	.postclose = amdgpu_driver_postclose_kms,
2793	.lastclose = amdgpu_driver_lastclose_kms,
 
 
 
 
 
 
 
2794	.ioctls = amdgpu_ioctls_kms,
2795	.num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
 
 
2796	.dumb_create = amdgpu_mode_dumb_create,
2797	.dumb_map_offset = amdgpu_mode_dumb_mmap,
2798	.fops = &amdgpu_driver_kms_fops,
2799	.release = &amdgpu_driver_release_kms,
2800
2801	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2802	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 
2803	.gem_prime_import = amdgpu_gem_prime_import,
2804	.gem_prime_mmap = drm_gem_prime_mmap,
 
 
 
 
2805
2806	.name = DRIVER_NAME,
2807	.desc = DRIVER_DESC,
2808	.date = DRIVER_DATE,
2809	.major = KMS_DRIVER_MAJOR,
2810	.minor = KMS_DRIVER_MINOR,
2811	.patchlevel = KMS_DRIVER_PATCHLEVEL,
2812};
2813
2814static struct pci_error_handlers amdgpu_pci_err_handler = {
2815	.error_detected	= amdgpu_pci_error_detected,
2816	.mmio_enabled	= amdgpu_pci_mmio_enabled,
2817	.slot_reset	= amdgpu_pci_slot_reset,
2818	.resume		= amdgpu_pci_resume,
2819};
2820
2821extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2822extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2823extern const struct attribute_group amdgpu_vbios_version_attr_group;
2824
2825static const struct attribute_group *amdgpu_sysfs_groups[] = {
2826	&amdgpu_vram_mgr_attr_group,
2827	&amdgpu_gtt_mgr_attr_group,
2828	&amdgpu_vbios_version_attr_group,
2829	NULL,
2830};
2831
2832
2833static struct pci_driver amdgpu_kms_pci_driver = {
2834	.name = DRIVER_NAME,
2835	.id_table = pciidlist,
2836	.probe = amdgpu_pci_probe,
2837	.remove = amdgpu_pci_remove,
2838	.shutdown = amdgpu_pci_shutdown,
2839	.driver.pm = &amdgpu_pm_ops,
2840	.err_handler = &amdgpu_pci_err_handler,
2841	.dev_groups = amdgpu_sysfs_groups,
2842};
2843
 
 
2844static int __init amdgpu_init(void)
2845{
2846	int r;
2847
2848	if (drm_firmware_drivers_only())
 
2849		return -EINVAL;
 
2850
2851	r = amdgpu_sync_init();
2852	if (r)
2853		goto error_sync;
2854
2855	r = amdgpu_fence_slab_init();
2856	if (r)
2857		goto error_fence;
2858
2859	DRM_INFO("amdgpu kernel modesetting enabled.\n");
 
2860	amdgpu_register_atpx_handler();
2861	amdgpu_acpi_detect();
2862
2863	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2864	amdgpu_amdkfd_init();
2865
2866	/* let modprobe override vga console setting */
2867	return pci_register_driver(&amdgpu_kms_pci_driver);
2868
2869error_fence:
2870	amdgpu_sync_fini();
2871
2872error_sync:
2873	return r;
2874}
2875
2876static void __exit amdgpu_exit(void)
2877{
2878	amdgpu_amdkfd_fini();
2879	pci_unregister_driver(&amdgpu_kms_pci_driver);
2880	amdgpu_unregister_atpx_handler();
2881	amdgpu_sync_fini();
2882	amdgpu_fence_slab_fini();
2883	mmu_notifier_synchronize();
2884}
2885
2886module_init(amdgpu_init);
2887module_exit(amdgpu_exit);
2888
2889MODULE_AUTHOR(DRIVER_AUTHOR);
2890MODULE_DESCRIPTION(DRIVER_DESC);
2891MODULE_LICENSE("GPL and additional rights");
v5.4
   1/*
   2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 */
  24
  25#include <drm/amdgpu_drm.h>
  26#include <drm/drm_drv.h>
 
  27#include <drm/drm_gem.h>
  28#include <drm/drm_vblank.h>
 
  29#include "amdgpu_drv.h"
  30
  31#include <drm/drm_pciids.h>
  32#include <linux/console.h>
  33#include <linux/module.h>
  34#include <linux/pci.h>
  35#include <linux/pm_runtime.h>
  36#include <linux/vga_switcheroo.h>
  37#include <drm/drm_probe_helper.h>
  38#include <linux/mmu_notifier.h>
 
 
 
 
  39
  40#include "amdgpu.h"
  41#include "amdgpu_irq.h"
  42#include "amdgpu_dma_buf.h"
 
 
 
  43
  44#include "amdgpu_amdkfd.h"
 
 
  45
  46/*
  47 * KMS wrapper.
  48 * - 3.0.0 - initial driver
  49 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
  50 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
  51 *           at the end of IBs.
  52 * - 3.3.0 - Add VM support for UVD on supported hardware.
  53 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
  54 * - 3.5.0 - Add support for new UVD_NO_OP register.
  55 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
  56 * - 3.7.0 - Add support for VCE clock list packet
  57 * - 3.8.0 - Add support raster config init in the kernel
  58 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
  59 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
  60 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
  61 * - 3.12.0 - Add query for double offchip LDS buffers
  62 * - 3.13.0 - Add PRT support
  63 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
  64 * - 3.15.0 - Export more gpu info for gfx9
  65 * - 3.16.0 - Add reserved vmid support
  66 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
  67 * - 3.18.0 - Export gpu always on cu bitmap
  68 * - 3.19.0 - Add support for UVD MJPEG decode
  69 * - 3.20.0 - Add support for local BOs
  70 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
  71 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
  72 * - 3.23.0 - Add query for VRAM lost counter
  73 * - 3.24.0 - Add high priority compute support for gfx9
  74 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
  75 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
  76 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
  77 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
  78 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
  79 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
  80 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
  81 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
  82 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
  83 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
  84 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  85 */
  86#define KMS_DRIVER_MAJOR	3
  87#define KMS_DRIVER_MINOR	35
  88#define KMS_DRIVER_PATCHLEVEL	0
  89
  90#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256
  91
  92int amdgpu_vram_limit = 0;
  93int amdgpu_vis_vram_limit = 0;
  94int amdgpu_gart_size = -1; /* auto */
  95int amdgpu_gtt_size = -1; /* auto */
  96int amdgpu_moverate = -1; /* auto */
  97int amdgpu_benchmarking = 0;
  98int amdgpu_testing = 0;
  99int amdgpu_audio = -1;
 100int amdgpu_disp_priority = 0;
 101int amdgpu_hw_i2c = 0;
 102int amdgpu_pcie_gen2 = -1;
 103int amdgpu_msi = -1;
 104char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
 105int amdgpu_dpm = -1;
 106int amdgpu_fw_load_type = -1;
 107int amdgpu_aspm = -1;
 108int amdgpu_runtime_pm = -1;
 109uint amdgpu_ip_block_mask = 0xffffffff;
 110int amdgpu_bapm = -1;
 111int amdgpu_deep_color = 0;
 112int amdgpu_vm_size = -1;
 113int amdgpu_vm_fragment_size = -1;
 114int amdgpu_vm_block_size = -1;
 115int amdgpu_vm_fault_stop = 0;
 116int amdgpu_vm_debug = 0;
 117int amdgpu_vm_update_mode = -1;
 118int amdgpu_exp_hw_support = 0;
 119int amdgpu_dc = -1;
 120int amdgpu_sched_jobs = 32;
 121int amdgpu_sched_hw_submission = 2;
 122uint amdgpu_pcie_gen_cap = 0;
 123uint amdgpu_pcie_lane_cap = 0;
 124uint amdgpu_cg_mask = 0xffffffff;
 125uint amdgpu_pg_mask = 0xffffffff;
 126uint amdgpu_sdma_phase_quantum = 32;
 127char *amdgpu_disable_cu = NULL;
 128char *amdgpu_virtual_display = NULL;
 129/* OverDrive(bit 14) disabled by default*/
 130uint amdgpu_pp_feature_mask = 0xffffbfff;
 131int amdgpu_ngg = 0;
 132int amdgpu_prim_buf_per_se = 0;
 133int amdgpu_pos_buf_per_se = 0;
 134int amdgpu_cntl_sb_buf_per_se = 0;
 135int amdgpu_param_buf_per_se = 0;
 136int amdgpu_job_hang_limit = 0;
 137int amdgpu_lbpw = -1;
 138int amdgpu_compute_multipipe = -1;
 139int amdgpu_gpu_recovery = -1; /* auto */
 140int amdgpu_emu_mode = 0;
 141uint amdgpu_smu_memory_pool_size = 0;
 142/* FBC (bit 0) disabled by default*/
 143uint amdgpu_dc_feature_mask = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 144int amdgpu_async_gfx_ring = 1;
 145int amdgpu_mcbp = 0;
 146int amdgpu_discovery = -1;
 147int amdgpu_mes = 0;
 148int amdgpu_noretry = 1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 149
 150struct amdgpu_mgpu_info mgpu_info = {
 151	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
 
 
 
 152};
 153int amdgpu_ras_enable = -1;
 154uint amdgpu_ras_mask = 0xfffffffb;
 
 
 
 
 
 155
 156/**
 157 * DOC: vramlimit (int)
 158 * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
 159 */
 160MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 161module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 162
 163/**
 164 * DOC: vis_vramlimit (int)
 165 * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 0 (Use full CPU visible VRAM).
 166 */
 167MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
 168module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 169
 170/**
 171 * DOC: gartsize (uint)
 172 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
 
 173 */
 174MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
 175module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 176
 177/**
 178 * DOC: gttsize (int)
 179 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
 180 * otherwise 3/4 RAM size).
 181 */
 182MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 183module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 184
 185/**
 186 * DOC: moverate (int)
 187 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
 188 */
 189MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
 190module_param_named(moverate, amdgpu_moverate, int, 0600);
 191
 192/**
 193 * DOC: benchmark (int)
 194 * Run benchmarks. The default is 0 (Skip benchmarks).
 195 */
 196MODULE_PARM_DESC(benchmark, "Run benchmark");
 197module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 198
 199/**
 200 * DOC: test (int)
 201 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
 202 */
 203MODULE_PARM_DESC(test, "Run tests");
 204module_param_named(test, amdgpu_testing, int, 0444);
 205
 206/**
 207 * DOC: audio (int)
 208 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
 209 */
 210MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 211module_param_named(audio, amdgpu_audio, int, 0444);
 212
 213/**
 214 * DOC: disp_priority (int)
 215 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
 216 */
 217MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
 218module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 219
 220/**
 221 * DOC: hw_i2c (int)
 222 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
 223 */
 224MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 225module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 226
 227/**
 228 * DOC: pcie_gen2 (int)
 229 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
 230 */
 231MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
 232module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 233
 234/**
 235 * DOC: msi (int)
 236 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 237 */
 238MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 239module_param_named(msi, amdgpu_msi, int, 0444);
 240
 241/**
 242 * DOC: lockup_timeout (string)
 243 * Set GPU scheduler timeout value in ms.
 244 *
 245 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
 246 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
 247 * to default timeout.
 248 *  - With one value specified, the setting will apply to all non-compute jobs.
 249 *  - With multiple values specified, the first one will be for GFX. The second one is for Compute.
 250 *    And the third and fourth ones are for SDMA and Video.
 
 
 
 251 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
 252 * jobs is 10000. And there is no timeout enforced on compute jobs.
 253 */
 254MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
 
 255		" 0: keep default value. negative: infinity timeout), "
 256		"format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
 
 257module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
 258
 259/**
 260 * DOC: dpm (int)
 261 * Override for dynamic power management setting
 262 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)
 263 * The default is -1 (auto).
 264 */
 265MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 266module_param_named(dpm, amdgpu_dpm, int, 0444);
 267
 268/**
 269 * DOC: fw_load_type (int)
 270 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
 
 
 
 271 */
 272MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
 273module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 274
 275/**
 276 * DOC: aspm (int)
 277 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 278 */
 279MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 280module_param_named(aspm, amdgpu_aspm, int, 0444);
 281
 282/**
 283 * DOC: runpm (int)
 284 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
 285 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
 
 286 */
 287MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
 288module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
 289
 290/**
 291 * DOC: ip_block_mask (uint)
 292 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
 293 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
 294 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
 295 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
 296 */
 297MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
 298module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
 299
 300/**
 301 * DOC: bapm (int)
 302 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
 303 * The default -1 (auto, enabled)
 304 */
 305MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
 306module_param_named(bapm, amdgpu_bapm, int, 0444);
 307
 308/**
 309 * DOC: deep_color (int)
 310 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
 311 */
 312MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 313module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 314
 315/**
 316 * DOC: vm_size (int)
 317 * Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (automatic for each asic).
 318 */
 319MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 320module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 321
 322/**
 323 * DOC: vm_fragment_size (int)
 324 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
 325 */
 326MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
 327module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
 328
 329/**
 330 * DOC: vm_block_size (int)
 331 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
 332 */
 333MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 334module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 335
 336/**
 337 * DOC: vm_fault_stop (int)
 338 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
 339 */
 340MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
 341module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
 342
 343/**
 344 * DOC: vm_debug (int)
 345 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
 346 */
 347MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
 348module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 349
 350/**
 351 * DOC: vm_update_mode (int)
 352 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
 353 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
 354 */
 355MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
 356module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
 357
 358/**
 359 * DOC: exp_hw_support (int)
 360 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
 361 */
 362MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
 363module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 364
 365/**
 366 * DOC: dc (int)
 367 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
 368 */
 369MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
 370module_param_named(dc, amdgpu_dc, int, 0444);
 371
 372/**
 373 * DOC: sched_jobs (int)
 374 * Override the max number of jobs supported in the sw queue. The default is 32.
 375 */
 376MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
 377module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
 378
 379/**
 380 * DOC: sched_hw_submission (int)
 381 * Override the max number of HW submissions. The default is 2.
 382 */
 383MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
 384module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
 385
 386/**
 387 * DOC: ppfeaturemask (uint)
 388 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 389 * The default is the current set of stable power features.
 390 */
 391MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
 392module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
 
 
 
 
 
 
 
 
 393
 394/**
 395 * DOC: pcie_gen_cap (uint)
 396 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 397 * The default is 0 (automatic for each asic).
 398 */
 399MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
 400module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
 401
 402/**
 403 * DOC: pcie_lane_cap (uint)
 404 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
 405 * The default is 0 (automatic for each asic).
 406 */
 407MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
 408module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
 409
 410/**
 411 * DOC: cg_mask (uint)
 412 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
 413 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 414 */
 415MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
 416module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
 417
 418/**
 419 * DOC: pg_mask (uint)
 420 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
 421 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
 422 */
 423MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
 424module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
 425
 426/**
 427 * DOC: sdma_phase_quantum (uint)
 428 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
 429 */
 430MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
 431module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
 432
 433/**
 434 * DOC: disable_cu (charp)
 435 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
 436 */
 437MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
 438module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
 439
 440/**
 441 * DOC: virtual_display (charp)
 442 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
 443 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
 444 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
 445 * device at 26:00.0. The default is NULL.
 446 */
 447MODULE_PARM_DESC(virtual_display,
 448		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
 449module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
 450
 451/**
 452 * DOC: ngg (int)
 453 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
 454 */
 455MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
 456module_param_named(ngg, amdgpu_ngg, int, 0444);
 457
 458/**
 459 * DOC: prim_buf_per_se (int)
 460 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 461 */
 462MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
 463module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
 464
 465/**
 466 * DOC: pos_buf_per_se (int)
 467 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
 468 */
 469MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
 470module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
 471
 472/**
 473 * DOC: cntl_sb_buf_per_se (int)
 474 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
 475 */
 476MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
 477module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
 478
 479/**
 480 * DOC: param_buf_per_se (int)
 481 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
 482 * The default is 0 (depending on gfx).
 483 */
 484MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
 485module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
 486
 487/**
 488 * DOC: job_hang_limit (int)
 489 * Set how much time allow a job hang and not drop it. The default is 0.
 490 */
 491MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
 492module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
 493
 494/**
 495 * DOC: lbpw (int)
 496 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
 497 */
 498MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
 499module_param_named(lbpw, amdgpu_lbpw, int, 0444);
 500
 501MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
 502module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
 503
 504/**
 505 * DOC: gpu_recovery (int)
 506 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
 507 */
 508MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
 509module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
 510
 511/**
 512 * DOC: emu_mode (int)
 513 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
 514 */
 515MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
 516module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
 517
 518/**
 519 * DOC: ras_enable (int)
 520 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
 521 */
 522MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
 523module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
 524
 525/**
 526 * DOC: ras_mask (uint)
 527 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
 528 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
 529 */
 530MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
 531module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
 532
 533/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 534 * DOC: si_support (int)
 535 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
 536 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 537 * otherwise using amdgpu driver.
 538 */
 539#ifdef CONFIG_DRM_AMDGPU_SI
 540
 541#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 542int amdgpu_si_support = 0;
 543MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
 544#else
 545int amdgpu_si_support = 1;
 546MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
 547#endif
 548
 549module_param_named(si_support, amdgpu_si_support, int, 0444);
 550#endif
 551
 552/**
 553 * DOC: cik_support (int)
 554 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
 555 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 556 * otherwise using amdgpu driver.
 557 */
 558#ifdef CONFIG_DRM_AMDGPU_CIK
 559
 560#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
 561int amdgpu_cik_support = 0;
 562MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
 563#else
 564int amdgpu_cik_support = 1;
 565MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
 566#endif
 567
 568module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 569#endif
 570
 571/**
 572 * DOC: smu_memory_pool_size (uint)
 573 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
 574 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
 575 */
 576MODULE_PARM_DESC(smu_memory_pool_size,
 577	"reserve gtt for smu debug usage, 0 = disable,"
 578		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
 579module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 580
 581/**
 582 * DOC: async_gfx_ring (int)
 583 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
 584 */
 585MODULE_PARM_DESC(async_gfx_ring,
 586	"Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
 587module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
 588
 589/**
 590 * DOC: mcbp (int)
 591 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
 592 */
 593MODULE_PARM_DESC(mcbp,
 594	"Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
 595module_param_named(mcbp, amdgpu_mcbp, int, 0444);
 596
 597/**
 598 * DOC: discovery (int)
 599 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
 600 * (-1 = auto (default), 0 = disabled, 1 = enabled)
 601 */
 602MODULE_PARM_DESC(discovery,
 603	"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
 604module_param_named(discovery, amdgpu_discovery, int, 0444);
 605
 606/**
 607 * DOC: mes (int)
 608 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
 609 * (0 = disabled (default), 1 = enabled)
 610 */
 611MODULE_PARM_DESC(mes,
 612	"Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
 613module_param_named(mes, amdgpu_mes, int, 0444);
 614
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 615MODULE_PARM_DESC(noretry,
 616	"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
 617module_param_named(noretry, amdgpu_noretry, int, 0644);
 618
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 619#ifdef CONFIG_HSA_AMD
 620/**
 621 * DOC: sched_policy (int)
 622 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
 623 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
 624 * assigns queues to HQDs.
 625 */
 626int sched_policy = KFD_SCHED_POLICY_HWS;
 627module_param(sched_policy, int, 0444);
 628MODULE_PARM_DESC(sched_policy,
 629	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
 630
 631/**
 632 * DOC: hws_max_conc_proc (int)
 633 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
 634 * number of VMIDs assigned to the HWS, which is also the default.
 635 */
 636int hws_max_conc_proc = 8;
 637module_param(hws_max_conc_proc, int, 0444);
 638MODULE_PARM_DESC(hws_max_conc_proc,
 639	"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
 640
 641/**
 642 * DOC: cwsr_enable (int)
 643 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
 644 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
 645 * disables it.
 646 */
 647int cwsr_enable = 1;
 648module_param(cwsr_enable, int, 0444);
 649MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
 650
 651/**
 652 * DOC: max_num_of_queues_per_device (int)
 653 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
 654 * is 4096.
 655 */
 656int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
 657module_param(max_num_of_queues_per_device, int, 0444);
 658MODULE_PARM_DESC(max_num_of_queues_per_device,
 659	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
 660
 661/**
 662 * DOC: send_sigterm (int)
 663 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
 664 * but just print errors on dmesg. Setting 1 enables sending sigterm.
 665 */
 666int send_sigterm;
 667module_param(send_sigterm, int, 0444);
 668MODULE_PARM_DESC(send_sigterm,
 669	"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
 670
 671/**
 672 * DOC: debug_largebar (int)
 673 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
 674 * system. This limits the VRAM size reported to ROCm applications to the visible
 675 * size, usually 256MB.
 676 * Default value is 0, diabled.
 677 */
 678int debug_largebar;
 679module_param(debug_largebar, int, 0444);
 680MODULE_PARM_DESC(debug_largebar,
 681	"Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
 682
 683/**
 684 * DOC: ignore_crat (int)
 685 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
 686 * table to get information about AMD APUs. This option can serve as a workaround on
 687 * systems with a broken CRAT table.
 
 
 
 688 */
 689int ignore_crat;
 690module_param(ignore_crat, int, 0444);
 691MODULE_PARM_DESC(ignore_crat,
 692	"Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
 693
 694/**
 695 * DOC: halt_if_hws_hang (int)
 696 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
 697 * Setting 1 enables halt on hang.
 698 */
 699int halt_if_hws_hang;
 700module_param(halt_if_hws_hang, int, 0644);
 701MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
 702
 703/**
 704 * DOC: hws_gws_support(bool)
 705 * Whether HWS support gws barriers. Default value: false (not supported)
 706 * This will be replaced with a MEC firmware version check once firmware
 707 * is ready
 708 */
 709bool hws_gws_support;
 710module_param(hws_gws_support, bool, 0444);
 711MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)");
 712
 713/**
 714  * DOC: queue_preemption_timeout_ms (int)
 715  * queue preemption timeout in ms (1 = Minimum, 9000 = default)
 716  */
 717int queue_preemption_timeout_ms = 9000;
 718module_param(queue_preemption_timeout_ms, int, 0644);
 719MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 720#endif
 721
 722/**
 723 * DOC: dcfeaturemask (uint)
 724 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
 725 * The default is the current set of stable display features.
 726 */
 727MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
 728module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
 729
 730/**
 
 
 
 
 
 
 
 
 
 
 731 * DOC: abmlevel (uint)
 732 * Override the default ABM (Adaptive Backlight Management) level used for DC
 733 * enabled hardware. Requires DMCU to be supported and loaded.
 734 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
 735 * default. Values 1-4 control the maximum allowable brightness reduction via
 736 * the ABM algorithm, with 1 being the least reduction and 4 being the most
 737 * reduction.
 738 *
 739 * Defaults to 0, or disabled. Userspace can still override this level later
 740 * after boot.
 741 */
 742uint amdgpu_dm_abm_level = 0;
 743MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
 744module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
 745
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 746static const struct pci_device_id pciidlist[] = {
 747#ifdef  CONFIG_DRM_AMDGPU_SI
 748	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 749	{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 750	{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 751	{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 752	{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 753	{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 754	{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 755	{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 756	{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 757	{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 758	{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 759	{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 760	{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
 761	{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 762	{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 763	{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
 764	{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 765	{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 766	{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 767	{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 768	{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 769	{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 770	{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 771	{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 772	{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
 773	{0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 774	{0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 775	{0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 776	{0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 777	{0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 778	{0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 779	{0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 780	{0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 781	{0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 782	{0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 783	{0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 784	{0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 785	{0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 786	{0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 787	{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 788	{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
 789	{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
 790	{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 791	{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 792	{0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 793	{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 794	{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 795	{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 796	{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 797	{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 798	{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 799	{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 800	{0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 801	{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 802	{0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 803	{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 804	{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 805	{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 806	{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
 807	{0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 808	{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 809	{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 810	{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 811	{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 812	{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 813	{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
 814	{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 815	{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 816	{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 817	{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 818	{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 819	{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
 820#endif
 821#ifdef CONFIG_DRM_AMDGPU_CIK
 822	/* Kaveri */
 823	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 824	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 825	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 826	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 827	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 828	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 829	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 830	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 831	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 832	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 833	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 834	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 835	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 836	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 837	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 838	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 839	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 840	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 841	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
 842	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 843	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 844	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
 845	/* Bonaire */
 846	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 847	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 848	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 849	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
 850	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 851	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 852	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 853	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 854	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 855	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 856	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
 857	/* Hawaii */
 858	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 859	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 860	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 861	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 862	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 863	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 864	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 865	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 866	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 867	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 868	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 869	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
 870	/* Kabini */
 871	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 872	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 873	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 874	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 875	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 876	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 877	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 878	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 879	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 880	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 881	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 882	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
 883	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 884	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 885	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 886	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
 887	/* mullins */
 888	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 889	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 890	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 891	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 892	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 893	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 894	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 895	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 896	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 897	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 898	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 899	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 900	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 901	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 902	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 903	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
 904#endif
 905	/* topaz */
 906	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 907	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 908	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 909	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 910	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
 911	/* tonga */
 912	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 913	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 914	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 915	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 916	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 917	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 918	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 919	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 920	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
 921	/* fiji */
 922	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 923	{0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
 924	/* carrizo */
 925	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 926	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 927	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 928	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 929	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 930	/* stoney */
 931	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
 932	/* Polaris11 */
 933	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 934	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 935	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 936	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 937	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 938	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 939	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 940	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 941	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
 942	/* Polaris10 */
 943	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 944	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 945	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 946	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 947	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 948	{0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 949	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 950	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 951	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 952	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 953	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 954	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 955	{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 956	/* Polaris12 */
 957	{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 958	{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 959	{0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 960	{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 961	{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 962	{0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 963	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 964	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
 965	/* VEGAM */
 966	{0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 967	{0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 968	{0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
 969	/* Vega 10 */
 970	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 971	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 972	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 973	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 974	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 975	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 976	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 977	{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 978	{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 979	{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 980	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 981	{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 982	{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 983	{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 984	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
 985	/* Vega 12 */
 986	{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 987	{0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 988	{0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 989	{0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 990	{0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
 991	/* Vega 20 */
 992	{0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 993	{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 994	{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 995	{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 996	{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 997	{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 998	{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
 999	/* Raven */
1000	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1001	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1002	/* Arcturus */
1003	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1004	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1005	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1006	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
1007	/* Navi10 */
1008	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1009	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1010	{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1011	{0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1012	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1013	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
 
1014	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1015	/* Navi14 */
1016	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1017	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1018	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1019	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1020
1021	/* Renoir */
1022	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
 
 
 
1023
1024	/* Navi12 */
1025	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1026
1027	{0, 0, 0}
1028};
1029
1030MODULE_DEVICE_TABLE(pci, pciidlist);
1031
1032static struct drm_driver kms_driver;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1033
1034static int amdgpu_pci_probe(struct pci_dev *pdev,
1035			    const struct pci_device_id *ent)
1036{
1037	struct drm_device *dev;
 
1038	unsigned long flags = ent->driver_data;
1039	int ret, retry = 0;
1040	bool supports_atomic = false;
1041
1042	if (!amdgpu_virtual_display &&
 
 
 
 
 
 
 
 
 
1043	    amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1044		supports_atomic = true;
1045
1046	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1047		DRM_INFO("This hardware requires experimental hardware support.\n"
1048			 "See modparam exp_hw_support\n");
1049		return -ENODEV;
1050	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1051
1052#ifdef CONFIG_DRM_AMDGPU_SI
1053	if (!amdgpu_si_support) {
1054		switch (flags & AMD_ASIC_MASK) {
1055		case CHIP_TAHITI:
1056		case CHIP_PITCAIRN:
1057		case CHIP_VERDE:
1058		case CHIP_OLAND:
1059		case CHIP_HAINAN:
1060			dev_info(&pdev->dev,
1061				 "SI support provided by radeon.\n");
1062			dev_info(&pdev->dev,
1063				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1064				);
1065			return -ENODEV;
1066		}
1067	}
1068#endif
1069#ifdef CONFIG_DRM_AMDGPU_CIK
1070	if (!amdgpu_cik_support) {
1071		switch (flags & AMD_ASIC_MASK) {
1072		case CHIP_KAVERI:
1073		case CHIP_BONAIRE:
1074		case CHIP_HAWAII:
1075		case CHIP_KABINI:
1076		case CHIP_MULLINS:
1077			dev_info(&pdev->dev,
1078				 "CIK support provided by radeon.\n");
1079			dev_info(&pdev->dev,
1080				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1081				);
1082			return -ENODEV;
1083		}
1084	}
1085#endif
1086
1087	/* Get rid of things like offb */
1088	ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
1089	if (ret)
1090		return ret;
1091
1092	dev = drm_dev_alloc(&kms_driver, &pdev->dev);
1093	if (IS_ERR(dev))
1094		return PTR_ERR(dev);
1095
1096	if (!supports_atomic)
1097		dev->driver_features &= ~DRIVER_ATOMIC;
1098
1099	ret = pci_enable_device(pdev);
1100	if (ret)
1101		goto err_free;
1102
1103	dev->pdev = pdev;
1104
1105	pci_set_drvdata(pdev, dev);
 
 
1106
1107retry_init:
1108	ret = drm_dev_register(dev, ent->driver_data);
1109	if (ret == -EAGAIN && ++retry <= 3) {
1110		DRM_INFO("retry init %d\n", retry);
1111		/* Don't request EX mode too frequently which is attacking */
1112		msleep(5000);
1113		goto retry_init;
1114	} else if (ret)
1115		goto err_pci;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1116
1117	return 0;
1118
1119err_pci:
1120	pci_disable_device(pdev);
1121err_free:
1122	drm_dev_put(dev);
1123	return ret;
1124}
1125
1126static void
1127amdgpu_pci_remove(struct pci_dev *pdev)
1128{
1129	struct drm_device *dev = pci_get_drvdata(pdev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1130
1131	DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
1132	drm_dev_unplug(dev);
1133	drm_dev_put(dev);
 
 
 
 
 
1134	pci_disable_device(pdev);
1135	pci_set_drvdata(pdev, NULL);
1136}
1137
1138static void
1139amdgpu_pci_shutdown(struct pci_dev *pdev)
1140{
1141	struct drm_device *dev = pci_get_drvdata(pdev);
1142	struct amdgpu_device *adev = dev->dev_private;
 
 
 
1143
1144	/* if we are running in a VM, make sure the device
1145	 * torn down properly on reboot/shutdown.
1146	 * unfortunately we can't detect certain
1147	 * hypervisors so just do this all the time.
1148	 */
1149	adev->mp1_state = PP_MP1_STATE_UNLOAD;
 
1150	amdgpu_device_ip_suspend(adev);
1151	adev->mp1_state = PP_MP1_STATE_NONE;
1152}
1153
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1154static int amdgpu_pmops_suspend(struct device *dev)
1155{
1156	struct drm_device *drm_dev = dev_get_drvdata(dev);
 
1157
1158	return amdgpu_device_suspend(drm_dev, true, true);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1159}
1160
1161static int amdgpu_pmops_resume(struct device *dev)
1162{
1163	struct drm_device *drm_dev = dev_get_drvdata(dev);
 
 
1164
1165	/* GPU comes up enabled by the bios on resume */
1166	if (amdgpu_device_is_px(drm_dev)) {
1167		pm_runtime_disable(dev);
1168		pm_runtime_set_active(dev);
1169		pm_runtime_enable(dev);
1170	}
1171
1172	return amdgpu_device_resume(drm_dev, true, true);
 
 
1173}
1174
1175static int amdgpu_pmops_freeze(struct device *dev)
1176{
1177	struct drm_device *drm_dev = dev_get_drvdata(dev);
 
 
1178
1179	return amdgpu_device_suspend(drm_dev, false, true);
 
 
 
 
 
1180}
1181
1182static int amdgpu_pmops_thaw(struct device *dev)
1183{
1184	struct drm_device *drm_dev = dev_get_drvdata(dev);
1185
1186	return amdgpu_device_resume(drm_dev, false, true);
1187}
1188
1189static int amdgpu_pmops_poweroff(struct device *dev)
1190{
1191	struct drm_device *drm_dev = dev_get_drvdata(dev);
1192
1193	return amdgpu_device_suspend(drm_dev, true, true);
1194}
1195
1196static int amdgpu_pmops_restore(struct device *dev)
1197{
1198	struct drm_device *drm_dev = dev_get_drvdata(dev);
1199
1200	return amdgpu_device_resume(drm_dev, false, true);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1201}
1202
1203static int amdgpu_pmops_runtime_suspend(struct device *dev)
1204{
1205	struct pci_dev *pdev = to_pci_dev(dev);
1206	struct drm_device *drm_dev = pci_get_drvdata(pdev);
1207	int ret;
 
1208
1209	if (!amdgpu_device_is_px(drm_dev)) {
1210		pm_runtime_forbid(dev);
1211		return -EBUSY;
1212	}
1213
1214	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1215	drm_kms_helper_poll_disable(drm_dev);
 
1216
1217	ret = amdgpu_device_suspend(drm_dev, false, false);
1218	pci_save_state(pdev);
1219	pci_disable_device(pdev);
1220	pci_ignore_hotplug(pdev);
1221	if (amdgpu_is_atpx_hybrid())
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1222		pci_set_power_state(pdev, PCI_D3cold);
1223	else if (!amdgpu_has_atpx_dgpu_power_cntl())
1224		pci_set_power_state(pdev, PCI_D3hot);
1225	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
 
 
 
 
 
1226
1227	return 0;
1228}
1229
1230static int amdgpu_pmops_runtime_resume(struct device *dev)
1231{
1232	struct pci_dev *pdev = to_pci_dev(dev);
1233	struct drm_device *drm_dev = pci_get_drvdata(pdev);
 
1234	int ret;
1235
1236	if (!amdgpu_device_is_px(drm_dev))
1237		return -EINVAL;
1238
1239	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
 
 
 
 
1240
1241	if (amdgpu_is_atpx_hybrid() ||
1242	    !amdgpu_has_atpx_dgpu_power_cntl())
 
1243		pci_set_power_state(pdev, PCI_D0);
1244	pci_restore_state(pdev);
1245	ret = pci_enable_device(pdev);
1246	if (ret)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1247		return ret;
1248	pci_set_master(pdev);
1249
1250	ret = amdgpu_device_resume(drm_dev, false, false);
1251	drm_kms_helper_poll_enable(drm_dev);
1252	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1253	return 0;
1254}
1255
1256static int amdgpu_pmops_runtime_idle(struct device *dev)
1257{
1258	struct drm_device *drm_dev = dev_get_drvdata(dev);
1259	struct drm_crtc *crtc;
 
 
1260
1261	if (!amdgpu_device_is_px(drm_dev)) {
1262		pm_runtime_forbid(dev);
1263		return -EBUSY;
1264	}
1265
1266	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1267		if (crtc->enabled) {
1268			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1269			return -EBUSY;
1270		}
1271	}
1272
1273	pm_runtime_mark_last_busy(dev);
1274	pm_runtime_autosuspend(dev);
1275	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1276	return 1;
1277}
1278
1279long amdgpu_drm_ioctl(struct file *filp,
1280		      unsigned int cmd, unsigned long arg)
1281{
1282	struct drm_file *file_priv = filp->private_data;
1283	struct drm_device *dev;
1284	long ret;
1285	dev = file_priv->minor->dev;
1286	ret = pm_runtime_get_sync(dev->dev);
1287	if (ret < 0)
1288		return ret;
1289
1290	ret = drm_ioctl(filp, cmd, arg);
1291
1292	pm_runtime_mark_last_busy(dev->dev);
 
1293	pm_runtime_put_autosuspend(dev->dev);
1294	return ret;
1295}
1296
1297static const struct dev_pm_ops amdgpu_pm_ops = {
 
 
1298	.suspend = amdgpu_pmops_suspend,
 
1299	.resume = amdgpu_pmops_resume,
1300	.freeze = amdgpu_pmops_freeze,
1301	.thaw = amdgpu_pmops_thaw,
1302	.poweroff = amdgpu_pmops_poweroff,
1303	.restore = amdgpu_pmops_restore,
1304	.runtime_suspend = amdgpu_pmops_runtime_suspend,
1305	.runtime_resume = amdgpu_pmops_runtime_resume,
1306	.runtime_idle = amdgpu_pmops_runtime_idle,
1307};
1308
1309static int amdgpu_flush(struct file *f, fl_owner_t id)
1310{
1311	struct drm_file *file_priv = f->private_data;
1312	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1313	long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1314
1315	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1316	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1317
1318	return timeout >= 0 ? 0 : timeout;
1319}
1320
1321static const struct file_operations amdgpu_driver_kms_fops = {
1322	.owner = THIS_MODULE,
1323	.open = drm_open,
1324	.flush = amdgpu_flush,
1325	.release = drm_release,
1326	.unlocked_ioctl = amdgpu_drm_ioctl,
1327	.mmap = amdgpu_mmap,
1328	.poll = drm_poll,
1329	.read = drm_read,
1330#ifdef CONFIG_COMPAT
1331	.compat_ioctl = amdgpu_kms_compat_ioctl,
1332#endif
 
 
 
1333};
1334
1335int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1336{
1337        struct drm_file *file;
1338
1339	if (!filp)
1340		return -EINVAL;
1341
1342	if (filp->f_op != &amdgpu_driver_kms_fops) {
1343		return -EINVAL;
1344	}
1345
1346	file = filp->private_data;
1347	*fpriv = file->driver_priv;
1348	return 0;
1349}
1350
1351int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
1352{
1353	char *input = amdgpu_lockup_timeout;
1354	char *timeout_setting = NULL;
1355	int index = 0;
1356	long timeout;
1357	int ret = 0;
1358
1359	/*
1360	 * By default timeout for non compute jobs is 10000.
1361	 * And there is no timeout enforced on compute jobs.
1362	 */
1363	adev->gfx_timeout = msecs_to_jiffies(10000);
1364	adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1365	adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
1366
1367	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1368		while ((timeout_setting = strsep(&input, ",")) &&
1369				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
1370			ret = kstrtol(timeout_setting, 0, &timeout);
1371			if (ret)
1372				return ret;
1373
1374			if (timeout == 0) {
1375				index++;
1376				continue;
1377			} else if (timeout < 0) {
1378				timeout = MAX_SCHEDULE_TIMEOUT;
1379			} else {
1380				timeout = msecs_to_jiffies(timeout);
1381			}
1382
1383			switch (index++) {
1384			case 0:
1385				adev->gfx_timeout = timeout;
1386				break;
1387			case 1:
1388				adev->compute_timeout = timeout;
1389				break;
1390			case 2:
1391				adev->sdma_timeout = timeout;
1392				break;
1393			case 3:
1394				adev->video_timeout = timeout;
1395				break;
1396			default:
1397				break;
1398			}
1399		}
1400		/*
1401		 * There is only one value specified and
1402		 * it should apply to all non-compute jobs.
1403		 */
1404		if (index == 1)
1405			adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
1406	}
1407
1408	return ret;
1409}
1410
1411static bool
1412amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1413				 bool in_vblank_irq, int *vpos, int *hpos,
1414				 ktime_t *stime, ktime_t *etime,
1415				 const struct drm_display_mode *mode)
1416{
1417	return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1418						  stime, etime, mode);
1419}
1420
1421static struct drm_driver kms_driver = {
1422	.driver_features =
1423	    DRIVER_USE_AGP | DRIVER_ATOMIC |
1424	    DRIVER_GEM |
1425	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
1426	.load = amdgpu_driver_load_kms,
1427	.open = amdgpu_driver_open_kms,
1428	.postclose = amdgpu_driver_postclose_kms,
1429	.lastclose = amdgpu_driver_lastclose_kms,
1430	.unload = amdgpu_driver_unload_kms,
1431	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
1432	.enable_vblank = amdgpu_enable_vblank_kms,
1433	.disable_vblank = amdgpu_disable_vblank_kms,
1434	.get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1435	.get_scanout_position = amdgpu_get_crtc_scanout_position,
1436	.irq_handler = amdgpu_irq_handler,
1437	.ioctls = amdgpu_ioctls_kms,
1438	.gem_free_object_unlocked = amdgpu_gem_object_free,
1439	.gem_open_object = amdgpu_gem_object_open,
1440	.gem_close_object = amdgpu_gem_object_close,
1441	.dumb_create = amdgpu_mode_dumb_create,
1442	.dumb_map_offset = amdgpu_mode_dumb_mmap,
1443	.fops = &amdgpu_driver_kms_fops,
 
1444
1445	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1446	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1447	.gem_prime_export = amdgpu_gem_prime_export,
1448	.gem_prime_import = amdgpu_gem_prime_import,
1449	.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
1450	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
1451	.gem_prime_vmap = amdgpu_gem_prime_vmap,
1452	.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1453	.gem_prime_mmap = amdgpu_gem_prime_mmap,
1454
1455	.name = DRIVER_NAME,
1456	.desc = DRIVER_DESC,
1457	.date = DRIVER_DATE,
1458	.major = KMS_DRIVER_MAJOR,
1459	.minor = KMS_DRIVER_MINOR,
1460	.patchlevel = KMS_DRIVER_PATCHLEVEL,
1461};
1462
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1463static struct pci_driver amdgpu_kms_pci_driver = {
1464	.name = DRIVER_NAME,
1465	.id_table = pciidlist,
1466	.probe = amdgpu_pci_probe,
1467	.remove = amdgpu_pci_remove,
1468	.shutdown = amdgpu_pci_shutdown,
1469	.driver.pm = &amdgpu_pm_ops,
 
 
1470};
1471
1472
1473
1474static int __init amdgpu_init(void)
1475{
1476	int r;
1477
1478	if (vgacon_text_force()) {
1479		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1480		return -EINVAL;
1481	}
1482
1483	r = amdgpu_sync_init();
1484	if (r)
1485		goto error_sync;
1486
1487	r = amdgpu_fence_slab_init();
1488	if (r)
1489		goto error_fence;
1490
1491	DRM_INFO("amdgpu kernel modesetting enabled.\n");
1492	kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1493	amdgpu_register_atpx_handler();
 
1494
1495	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
1496	amdgpu_amdkfd_init();
1497
1498	/* let modprobe override vga console setting */
1499	return pci_register_driver(&amdgpu_kms_pci_driver);
1500
1501error_fence:
1502	amdgpu_sync_fini();
1503
1504error_sync:
1505	return r;
1506}
1507
1508static void __exit amdgpu_exit(void)
1509{
1510	amdgpu_amdkfd_fini();
1511	pci_unregister_driver(&amdgpu_kms_pci_driver);
1512	amdgpu_unregister_atpx_handler();
1513	amdgpu_sync_fini();
1514	amdgpu_fence_slab_fini();
1515	mmu_notifier_synchronize();
1516}
1517
1518module_init(amdgpu_init);
1519module_exit(amdgpu_exit);
1520
1521MODULE_AUTHOR(DRIVER_AUTHOR);
1522MODULE_DESCRIPTION(DRIVER_DESC);
1523MODULE_LICENSE("GPL and additional rights");