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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27/**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34#include "amdgpu.h"
35#include "amdgpu_display.h"
36#include "amdgpu_gem.h"
37#include "amdgpu_dma_buf.h"
38#include "amdgpu_xgmi.h"
39#include <drm/amdgpu_drm.h>
40#include <linux/dma-buf.h>
41#include <linux/dma-fence-array.h>
42#include <linux/pci-p2pdma.h>
43#include <linux/pm_runtime.h>
44
45/**
46 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
47 *
48 * @dmabuf: DMA-buf where we attach to
49 * @attach: attachment to add
50 *
51 * Add the attachment as user to the exported DMA-buf.
52 */
53static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
54 struct dma_buf_attachment *attach)
55{
56 struct drm_gem_object *obj = dmabuf->priv;
57 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
58 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
59 int r;
60
61 if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
62 attach->peer2peer = false;
63
64 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
65 if (r < 0)
66 goto out;
67
68 return 0;
69
70out:
71 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
72 return r;
73}
74
75/**
76 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
77 *
78 * @dmabuf: DMA-buf where we remove the attachment from
79 * @attach: the attachment to remove
80 *
81 * Called when an attachment is removed from the DMA-buf.
82 */
83static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
84 struct dma_buf_attachment *attach)
85{
86 struct drm_gem_object *obj = dmabuf->priv;
87 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
88 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
89
90 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
91 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
92}
93
94/**
95 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
96 *
97 * @attach: attachment to pin down
98 *
99 * Pin the BO which is backing the DMA-buf so that it can't move any more.
100 */
101static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
102{
103 struct drm_gem_object *obj = attach->dmabuf->priv;
104 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
105
106 /* pin buffer into GTT */
107 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
108}
109
110/**
111 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
112 *
113 * @attach: attachment to unpin
114 *
115 * Unpin a previously pinned BO to make it movable again.
116 */
117static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
118{
119 struct drm_gem_object *obj = attach->dmabuf->priv;
120 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
121
122 amdgpu_bo_unpin(bo);
123}
124
125/**
126 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
127 * @attach: DMA-buf attachment
128 * @dir: DMA direction
129 *
130 * Makes sure that the shared DMA buffer can be accessed by the target device.
131 * For now, simply pins it to the GTT domain, where it should be accessible by
132 * all DMA devices.
133 *
134 * Returns:
135 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
136 * code.
137 */
138static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
139 enum dma_data_direction dir)
140{
141 struct dma_buf *dma_buf = attach->dmabuf;
142 struct drm_gem_object *obj = dma_buf->priv;
143 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
144 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
145 struct sg_table *sgt;
146 long r;
147
148 if (!bo->tbo.pin_count) {
149 /* move buffer into GTT or VRAM */
150 struct ttm_operation_ctx ctx = { false, false };
151 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
152
153 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
154 attach->peer2peer) {
155 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
156 domains |= AMDGPU_GEM_DOMAIN_VRAM;
157 }
158 amdgpu_bo_placement_from_domain(bo, domains);
159 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
160 if (r)
161 return ERR_PTR(r);
162
163 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
164 AMDGPU_GEM_DOMAIN_GTT)) {
165 return ERR_PTR(-EBUSY);
166 }
167
168 switch (bo->tbo.resource->mem_type) {
169 case TTM_PL_TT:
170 sgt = drm_prime_pages_to_sg(obj->dev,
171 bo->tbo.ttm->pages,
172 bo->tbo.ttm->num_pages);
173 if (IS_ERR(sgt))
174 return sgt;
175
176 if (dma_map_sgtable(attach->dev, sgt, dir,
177 DMA_ATTR_SKIP_CPU_SYNC))
178 goto error_free;
179 break;
180
181 case TTM_PL_VRAM:
182 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
183 bo->tbo.base.size, attach->dev,
184 dir, &sgt);
185 if (r)
186 return ERR_PTR(r);
187 break;
188 default:
189 return ERR_PTR(-EINVAL);
190 }
191
192 return sgt;
193
194error_free:
195 sg_free_table(sgt);
196 kfree(sgt);
197 return ERR_PTR(-EBUSY);
198}
199
200/**
201 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
202 * @attach: DMA-buf attachment
203 * @sgt: sg_table to unmap
204 * @dir: DMA direction
205 *
206 * This is called when a shared DMA buffer no longer needs to be accessible by
207 * another device. For now, simply unpins the buffer from GTT.
208 */
209static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
210 struct sg_table *sgt,
211 enum dma_data_direction dir)
212{
213 if (sgt->sgl->page_link) {
214 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
215 sg_free_table(sgt);
216 kfree(sgt);
217 } else {
218 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
219 }
220}
221
222/**
223 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
224 * @dma_buf: Shared DMA buffer
225 * @direction: Direction of DMA transfer
226 *
227 * This is called before CPU access to the shared DMA buffer's memory. If it's
228 * a read access, the buffer is moved to the GTT domain if possible, for optimal
229 * CPU read performance.
230 *
231 * Returns:
232 * 0 on success or a negative error code on failure.
233 */
234static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
235 enum dma_data_direction direction)
236{
237 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
238 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
239 struct ttm_operation_ctx ctx = { true, false };
240 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
241 int ret;
242 bool reads = (direction == DMA_BIDIRECTIONAL ||
243 direction == DMA_FROM_DEVICE);
244
245 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
246 return 0;
247
248 /* move to gtt */
249 ret = amdgpu_bo_reserve(bo, false);
250 if (unlikely(ret != 0))
251 return ret;
252
253 if (!bo->tbo.pin_count &&
254 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
255 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
256 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
257 }
258
259 amdgpu_bo_unreserve(bo);
260 return ret;
261}
262
263const struct dma_buf_ops amdgpu_dmabuf_ops = {
264 .attach = amdgpu_dma_buf_attach,
265 .detach = amdgpu_dma_buf_detach,
266 .pin = amdgpu_dma_buf_pin,
267 .unpin = amdgpu_dma_buf_unpin,
268 .map_dma_buf = amdgpu_dma_buf_map,
269 .unmap_dma_buf = amdgpu_dma_buf_unmap,
270 .release = drm_gem_dmabuf_release,
271 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
272 .mmap = drm_gem_dmabuf_mmap,
273 .vmap = drm_gem_dmabuf_vmap,
274 .vunmap = drm_gem_dmabuf_vunmap,
275};
276
277/**
278 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
279 * @gobj: GEM BO
280 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
281 *
282 * The main work is done by the &drm_gem_prime_export helper.
283 *
284 * Returns:
285 * Shared DMA buffer representing the GEM BO from the given device.
286 */
287struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
288 int flags)
289{
290 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
291 struct dma_buf *buf;
292
293 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
294 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
295 return ERR_PTR(-EPERM);
296
297 buf = drm_gem_prime_export(gobj, flags);
298 if (!IS_ERR(buf))
299 buf->ops = &amdgpu_dmabuf_ops;
300
301 return buf;
302}
303
304/**
305 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
306 *
307 * @dev: DRM device
308 * @dma_buf: DMA-buf
309 *
310 * Creates an empty SG BO for DMA-buf import.
311 *
312 * Returns:
313 * A new GEM BO of the given DRM device, representing the memory
314 * described by the given DMA-buf attachment and scatter/gather table.
315 */
316static struct drm_gem_object *
317amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
318{
319 struct dma_resv *resv = dma_buf->resv;
320 struct amdgpu_device *adev = drm_to_adev(dev);
321 struct drm_gem_object *gobj;
322 struct amdgpu_bo *bo;
323 uint64_t flags = 0;
324 int ret;
325
326 dma_resv_lock(resv, NULL);
327
328 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
329 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
330
331 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
332 AMDGPU_GEM_CREATE_COHERENT |
333 AMDGPU_GEM_CREATE_UNCACHED);
334 }
335
336 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
337 AMDGPU_GEM_DOMAIN_CPU, flags,
338 ttm_bo_type_sg, resv, &gobj);
339 if (ret)
340 goto error;
341
342 bo = gem_to_amdgpu_bo(gobj);
343 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
344 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
345
346 dma_resv_unlock(resv);
347 return gobj;
348
349error:
350 dma_resv_unlock(resv);
351 return ERR_PTR(ret);
352}
353
354/**
355 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
356 *
357 * @attach: the DMA-buf attachment
358 *
359 * Invalidate the DMA-buf attachment, making sure that the we re-create the
360 * mapping before the next use.
361 */
362static void
363amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
364{
365 struct drm_gem_object *obj = attach->importer_priv;
366 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
367 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
368 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
369 struct ttm_operation_ctx ctx = { false, false };
370 struct ttm_placement placement = {};
371 struct amdgpu_vm_bo_base *bo_base;
372 int r;
373
374 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
375 return;
376
377 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
378 if (r) {
379 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
380 return;
381 }
382
383 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
384 struct amdgpu_vm *vm = bo_base->vm;
385 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
386
387 if (ticket) {
388 /* When we get an error here it means that somebody
389 * else is holding the VM lock and updating page tables
390 * So we can just continue here.
391 */
392 r = dma_resv_lock(resv, ticket);
393 if (r)
394 continue;
395
396 } else {
397 /* TODO: This is more problematic and we actually need
398 * to allow page tables updates without holding the
399 * lock.
400 */
401 if (!dma_resv_trylock(resv))
402 continue;
403 }
404
405 r = amdgpu_vm_clear_freed(adev, vm, NULL);
406 if (!r)
407 r = amdgpu_vm_handle_moved(adev, vm);
408
409 if (r && r != -EBUSY)
410 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
411 r);
412
413 dma_resv_unlock(resv);
414 }
415}
416
417static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
418 .allow_peer2peer = true,
419 .move_notify = amdgpu_dma_buf_move_notify
420};
421
422/**
423 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
424 * @dev: DRM device
425 * @dma_buf: Shared DMA buffer
426 *
427 * Import a dma_buf into a the driver and potentially create a new GEM object.
428 *
429 * Returns:
430 * GEM BO representing the shared DMA buffer for the given device.
431 */
432struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
433 struct dma_buf *dma_buf)
434{
435 struct dma_buf_attachment *attach;
436 struct drm_gem_object *obj;
437
438 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
439 obj = dma_buf->priv;
440 if (obj->dev == dev) {
441 /*
442 * Importing dmabuf exported from out own gem increases
443 * refcount on gem itself instead of f_count of dmabuf.
444 */
445 drm_gem_object_get(obj);
446 return obj;
447 }
448 }
449
450 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
451 if (IS_ERR(obj))
452 return obj;
453
454 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
455 &amdgpu_dma_buf_attach_ops, obj);
456 if (IS_ERR(attach)) {
457 drm_gem_object_put(obj);
458 return ERR_CAST(attach);
459 }
460
461 get_dma_buf(dma_buf);
462 obj->import_attach = attach;
463 return obj;
464}
465
466/**
467 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
468 *
469 * @adev: amdgpu_device pointer of the importer
470 * @bo: amdgpu buffer object
471 *
472 * Returns:
473 * True if dmabuf accessible over xgmi, false otherwise.
474 */
475bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
476 struct amdgpu_bo *bo)
477{
478 struct drm_gem_object *obj = &bo->tbo.base;
479 struct drm_gem_object *gobj;
480
481 if (obj->import_attach) {
482 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
483
484 if (dma_buf->ops != &amdgpu_dmabuf_ops)
485 /* No XGMI with non AMD GPUs */
486 return false;
487
488 gobj = dma_buf->priv;
489 bo = gem_to_amdgpu_bo(gobj);
490 }
491
492 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
493 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
494 return true;
495
496 return false;
497}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27/**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34#include "amdgpu.h"
35#include "amdgpu_display.h"
36#include "amdgpu_gem.h"
37#include <drm/amdgpu_drm.h>
38#include <linux/dma-buf.h>
39#include <linux/dma-fence-array.h>
40
41/**
42 * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
43 * implementation
44 * @obj: GEM buffer object (BO)
45 *
46 * Returns:
47 * A scatter/gather table for the pinned pages of the BO's memory.
48 */
49struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
50{
51 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
52 int npages = bo->tbo.num_pages;
53
54 return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
55}
56
57/**
58 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
59 * @obj: GEM BO
60 *
61 * Sets up an in-kernel virtual mapping of the BO's memory.
62 *
63 * Returns:
64 * The virtual address of the mapping or an error pointer.
65 */
66void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
67{
68 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
69 int ret;
70
71 ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
72 &bo->dma_buf_vmap);
73 if (ret)
74 return ERR_PTR(ret);
75
76 return bo->dma_buf_vmap.virtual;
77}
78
79/**
80 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
81 * @obj: GEM BO
82 * @vaddr: Virtual address (unused)
83 *
84 * Tears down the in-kernel virtual mapping of the BO's memory.
85 */
86void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
87{
88 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
89
90 ttm_bo_kunmap(&bo->dma_buf_vmap);
91}
92
93/**
94 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
95 * @obj: GEM BO
96 * @vma: Virtual memory area
97 *
98 * Sets up a userspace mapping of the BO's memory in the given
99 * virtual memory area.
100 *
101 * Returns:
102 * 0 on success or a negative error code on failure.
103 */
104int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
105 struct vm_area_struct *vma)
106{
107 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
108 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
109 unsigned asize = amdgpu_bo_size(bo);
110 int ret;
111
112 if (!vma->vm_file)
113 return -ENODEV;
114
115 if (adev == NULL)
116 return -ENODEV;
117
118 /* Check for valid size. */
119 if (asize < vma->vm_end - vma->vm_start)
120 return -EINVAL;
121
122 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
123 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
124 return -EPERM;
125 }
126 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
127
128 /* prime mmap does not need to check access, so allow here */
129 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
130 if (ret)
131 return ret;
132
133 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
134 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
135
136 return ret;
137}
138
139static int
140__dma_resv_make_exclusive(struct dma_resv *obj)
141{
142 struct dma_fence **fences;
143 unsigned int count;
144 int r;
145
146 if (!dma_resv_get_list(obj)) /* no shared fences to convert */
147 return 0;
148
149 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
150 if (r)
151 return r;
152
153 if (count == 0) {
154 /* Now that was unexpected. */
155 } else if (count == 1) {
156 dma_resv_add_excl_fence(obj, fences[0]);
157 dma_fence_put(fences[0]);
158 kfree(fences);
159 } else {
160 struct dma_fence_array *array;
161
162 array = dma_fence_array_create(count, fences,
163 dma_fence_context_alloc(1), 0,
164 false);
165 if (!array)
166 goto err_fences_put;
167
168 dma_resv_add_excl_fence(obj, &array->base);
169 dma_fence_put(&array->base);
170 }
171
172 return 0;
173
174err_fences_put:
175 while (count--)
176 dma_fence_put(fences[count]);
177 kfree(fences);
178 return -ENOMEM;
179}
180
181/**
182 * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation
183 * @dma_buf: Shared DMA buffer
184 * @attach: DMA-buf attachment
185 *
186 * Makes sure that the shared DMA buffer can be accessed by the target device.
187 * For now, simply pins it to the GTT domain, where it should be accessible by
188 * all DMA devices.
189 *
190 * Returns:
191 * 0 on success or a negative error code on failure.
192 */
193static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf,
194 struct dma_buf_attachment *attach)
195{
196 struct drm_gem_object *obj = dma_buf->priv;
197 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
198 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
199 long r;
200
201 r = drm_gem_map_attach(dma_buf, attach);
202 if (r)
203 return r;
204
205 r = amdgpu_bo_reserve(bo, false);
206 if (unlikely(r != 0))
207 goto error_detach;
208
209
210 if (attach->dev->driver != adev->dev->driver) {
211 /*
212 * We only create shared fences for internal use, but importers
213 * of the dmabuf rely on exclusive fences for implicitly
214 * tracking write hazards. As any of the current fences may
215 * correspond to a write, we need to convert all existing
216 * fences on the reservation object into a single exclusive
217 * fence.
218 */
219 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
220 if (r)
221 goto error_unreserve;
222 }
223
224 /* pin buffer into GTT */
225 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
226 if (r)
227 goto error_unreserve;
228
229 if (attach->dev->driver != adev->dev->driver)
230 bo->prime_shared_count++;
231
232error_unreserve:
233 amdgpu_bo_unreserve(bo);
234
235error_detach:
236 if (r)
237 drm_gem_map_detach(dma_buf, attach);
238 return r;
239}
240
241/**
242 * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation
243 * @dma_buf: Shared DMA buffer
244 * @attach: DMA-buf attachment
245 *
246 * This is called when a shared DMA buffer no longer needs to be accessible by
247 * another device. For now, simply unpins the buffer from GTT.
248 */
249static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf,
250 struct dma_buf_attachment *attach)
251{
252 struct drm_gem_object *obj = dma_buf->priv;
253 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
254 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
255 int ret = 0;
256
257 ret = amdgpu_bo_reserve(bo, true);
258 if (unlikely(ret != 0))
259 goto error;
260
261 amdgpu_bo_unpin(bo);
262 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
263 bo->prime_shared_count--;
264 amdgpu_bo_unreserve(bo);
265
266error:
267 drm_gem_map_detach(dma_buf, attach);
268}
269
270/**
271 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
272 * @dma_buf: Shared DMA buffer
273 * @direction: Direction of DMA transfer
274 *
275 * This is called before CPU access to the shared DMA buffer's memory. If it's
276 * a read access, the buffer is moved to the GTT domain if possible, for optimal
277 * CPU read performance.
278 *
279 * Returns:
280 * 0 on success or a negative error code on failure.
281 */
282static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
283 enum dma_data_direction direction)
284{
285 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
287 struct ttm_operation_ctx ctx = { true, false };
288 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
289 int ret;
290 bool reads = (direction == DMA_BIDIRECTIONAL ||
291 direction == DMA_FROM_DEVICE);
292
293 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
294 return 0;
295
296 /* move to gtt */
297 ret = amdgpu_bo_reserve(bo, false);
298 if (unlikely(ret != 0))
299 return ret;
300
301 if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
302 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
303 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
304 }
305
306 amdgpu_bo_unreserve(bo);
307 return ret;
308}
309
310const struct dma_buf_ops amdgpu_dmabuf_ops = {
311 .attach = amdgpu_dma_buf_map_attach,
312 .detach = amdgpu_dma_buf_map_detach,
313 .map_dma_buf = drm_gem_map_dma_buf,
314 .unmap_dma_buf = drm_gem_unmap_dma_buf,
315 .release = drm_gem_dmabuf_release,
316 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
317 .mmap = drm_gem_dmabuf_mmap,
318 .vmap = drm_gem_dmabuf_vmap,
319 .vunmap = drm_gem_dmabuf_vunmap,
320};
321
322/**
323 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
324 * @dev: DRM device
325 * @gobj: GEM BO
326 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
327 *
328 * The main work is done by the &drm_gem_prime_export helper.
329 *
330 * Returns:
331 * Shared DMA buffer representing the GEM BO from the given device.
332 */
333struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
334 int flags)
335{
336 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
337 struct dma_buf *buf;
338
339 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
340 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
341 return ERR_PTR(-EPERM);
342
343 buf = drm_gem_prime_export(gobj, flags);
344 if (!IS_ERR(buf)) {
345 buf->file->f_mapping = gobj->dev->anon_inode->i_mapping;
346 buf->ops = &amdgpu_dmabuf_ops;
347 }
348
349 return buf;
350}
351
352/**
353 * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
354 * implementation
355 * @dev: DRM device
356 * @attach: DMA-buf attachment
357 * @sg: Scatter/gather table
358 *
359 * Imports shared DMA buffer memory exported by another device.
360 *
361 * Returns:
362 * A new GEM BO of the given DRM device, representing the memory
363 * described by the given DMA-buf attachment and scatter/gather table.
364 */
365struct drm_gem_object *
366amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
367 struct dma_buf_attachment *attach,
368 struct sg_table *sg)
369{
370 struct dma_resv *resv = attach->dmabuf->resv;
371 struct amdgpu_device *adev = dev->dev_private;
372 struct amdgpu_bo *bo;
373 struct amdgpu_bo_param bp;
374 int ret;
375
376 memset(&bp, 0, sizeof(bp));
377 bp.size = attach->dmabuf->size;
378 bp.byte_align = PAGE_SIZE;
379 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
380 bp.flags = 0;
381 bp.type = ttm_bo_type_sg;
382 bp.resv = resv;
383 dma_resv_lock(resv, NULL);
384 ret = amdgpu_bo_create(adev, &bp, &bo);
385 if (ret)
386 goto error;
387
388 bo->tbo.sg = sg;
389 bo->tbo.ttm->sg = sg;
390 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
391 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
392 if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
393 bo->prime_shared_count = 1;
394
395 dma_resv_unlock(resv);
396 return &bo->tbo.base;
397
398error:
399 dma_resv_unlock(resv);
400 return ERR_PTR(ret);
401}
402
403/**
404 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
405 * @dev: DRM device
406 * @dma_buf: Shared DMA buffer
407 *
408 * The main work is done by the &drm_gem_prime_import helper, which in turn
409 * uses &amdgpu_gem_prime_import_sg_table.
410 *
411 * Returns:
412 * GEM BO representing the shared DMA buffer for the given device.
413 */
414struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
415 struct dma_buf *dma_buf)
416{
417 struct drm_gem_object *obj;
418
419 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
420 obj = dma_buf->priv;
421 if (obj->dev == dev) {
422 /*
423 * Importing dmabuf exported from out own gem increases
424 * refcount on gem itself instead of f_count of dmabuf.
425 */
426 drm_gem_object_get(obj);
427 return obj;
428 }
429 }
430
431 return drm_gem_prime_import(dev, dma_buf);
432}