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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitmap.h>
7#include <linux/device.h>
8#include <linux/errno.h>
9#include <linux/gpio/driver.h>
10#include <linux/io.h>
11#include <linux/ioport.h>
12#include <linux/interrupt.h>
13#include <linux/irqdesc.h>
14#include <linux/isa.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/spinlock.h>
19#include <linux/types.h>
20
21#define WS16C48_EXTENT 10
22#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
23
24static unsigned int base[MAX_NUM_WS16C48];
25static unsigned int num_ws16c48;
26module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
28
29static unsigned int irq[MAX_NUM_WS16C48];
30static unsigned int num_irq;
31module_param_hw_array(irq, uint, irq, &num_irq, 0);
32MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
33
34/**
35 * struct ws16c48_reg - device register structure
36 * @port: Port 0 through 5 I/O
37 * @int_pending: Interrupt Pending
38 * @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
39 * @pol_enab_int_id: Interrupt polarity, enable, and ID
40 */
41struct ws16c48_reg {
42 u8 port[6];
43 u8 int_pending;
44 u8 page_lock;
45 u8 pol_enab_int_id[3];
46};
47
48/**
49 * struct ws16c48_gpio - GPIO device private data structure
50 * @chip: instance of the gpio_chip
51 * @io_state: bit I/O state (whether bit is set to input or output)
52 * @out_state: output bits state
53 * @lock: synchronization lock to prevent I/O race conditions
54 * @irq_mask: I/O bits affected by interrupts
55 * @flow_mask: IRQ flow type mask for the respective I/O bits
56 * @reg: I/O address offset for the device registers
57 */
58struct ws16c48_gpio {
59 struct gpio_chip chip;
60 unsigned char io_state[6];
61 unsigned char out_state[6];
62 raw_spinlock_t lock;
63 unsigned long irq_mask;
64 unsigned long flow_mask;
65 struct ws16c48_reg __iomem *reg;
66};
67
68static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
69{
70 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
71 const unsigned port = offset / 8;
72 const unsigned mask = BIT(offset % 8);
73
74 if (ws16c48gpio->io_state[port] & mask)
75 return GPIO_LINE_DIRECTION_IN;
76
77 return GPIO_LINE_DIRECTION_OUT;
78}
79
80static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
81{
82 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
83 const unsigned port = offset / 8;
84 const unsigned mask = BIT(offset % 8);
85 unsigned long flags;
86
87 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
88
89 ws16c48gpio->io_state[port] |= mask;
90 ws16c48gpio->out_state[port] &= ~mask;
91 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
92
93 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
94
95 return 0;
96}
97
98static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
99 unsigned offset, int value)
100{
101 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
102 const unsigned port = offset / 8;
103 const unsigned mask = BIT(offset % 8);
104 unsigned long flags;
105
106 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
107
108 ws16c48gpio->io_state[port] &= ~mask;
109 if (value)
110 ws16c48gpio->out_state[port] |= mask;
111 else
112 ws16c48gpio->out_state[port] &= ~mask;
113 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
114
115 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
116
117 return 0;
118}
119
120static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
121{
122 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
123 const unsigned port = offset / 8;
124 const unsigned mask = BIT(offset % 8);
125 unsigned long flags;
126 unsigned port_state;
127
128 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
129
130 /* ensure that GPIO is set for input */
131 if (!(ws16c48gpio->io_state[port] & mask)) {
132 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
133 return -EINVAL;
134 }
135
136 port_state = ioread8(ws16c48gpio->reg->port + port);
137
138 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
139
140 return !!(port_state & mask);
141}
142
143static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
144 unsigned long *mask, unsigned long *bits)
145{
146 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
147 unsigned long offset;
148 unsigned long gpio_mask;
149 size_t index;
150 u8 __iomem *port_addr;
151 unsigned long port_state;
152
153 /* clear bits array to a clean slate */
154 bitmap_zero(bits, chip->ngpio);
155
156 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
157 index = offset / 8;
158 port_addr = ws16c48gpio->reg->port + index;
159 port_state = ioread8(port_addr) & gpio_mask;
160
161 bitmap_set_value8(bits, port_state, offset);
162 }
163
164 return 0;
165}
166
167static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
168{
169 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
170 const unsigned port = offset / 8;
171 const unsigned mask = BIT(offset % 8);
172 unsigned long flags;
173
174 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
175
176 /* ensure that GPIO is set for output */
177 if (ws16c48gpio->io_state[port] & mask) {
178 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
179 return;
180 }
181
182 if (value)
183 ws16c48gpio->out_state[port] |= mask;
184 else
185 ws16c48gpio->out_state[port] &= ~mask;
186 iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
187
188 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
189}
190
191static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
192 unsigned long *mask, unsigned long *bits)
193{
194 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
195 unsigned long offset;
196 unsigned long gpio_mask;
197 size_t index;
198 u8 __iomem *port_addr;
199 unsigned long bitmask;
200 unsigned long flags;
201
202 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
203 index = offset / 8;
204 port_addr = ws16c48gpio->reg->port + index;
205
206 /* mask out GPIO configured for input */
207 gpio_mask &= ~ws16c48gpio->io_state[index];
208 bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
209
210 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
211
212 /* update output state data and set device gpio register */
213 ws16c48gpio->out_state[index] &= ~gpio_mask;
214 ws16c48gpio->out_state[index] |= bitmask;
215 iowrite8(ws16c48gpio->out_state[index], port_addr);
216
217 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
218 }
219}
220
221static void ws16c48_irq_ack(struct irq_data *data)
222{
223 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
224 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
225 const unsigned long offset = irqd_to_hwirq(data);
226 const unsigned port = offset / 8;
227 const unsigned mask = BIT(offset % 8);
228 unsigned long flags;
229 unsigned port_state;
230
231 /* only the first 3 ports support interrupts */
232 if (port > 2)
233 return;
234
235 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
236
237 port_state = ws16c48gpio->irq_mask >> (8*port);
238
239 /* Select Register Page 2; Unlock all I/O ports */
240 iowrite8(0x80, &ws16c48gpio->reg->page_lock);
241
242 /* Clear pending interrupt */
243 iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
244 iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
245
246 /* Select Register Page 3; Unlock all I/O ports */
247 iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
248
249 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
250}
251
252static void ws16c48_irq_mask(struct irq_data *data)
253{
254 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
255 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
256 const unsigned long offset = irqd_to_hwirq(data);
257 const unsigned long mask = BIT(offset);
258 const unsigned port = offset / 8;
259 unsigned long flags;
260 unsigned long port_state;
261
262 /* only the first 3 ports support interrupts */
263 if (port > 2)
264 return;
265
266 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
267
268 ws16c48gpio->irq_mask &= ~mask;
269 gpiochip_disable_irq(chip, offset);
270 port_state = ws16c48gpio->irq_mask >> (8 * port);
271
272 /* Select Register Page 2; Unlock all I/O ports */
273 iowrite8(0x80, &ws16c48gpio->reg->page_lock);
274
275 /* Disable interrupt */
276 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
277
278 /* Select Register Page 3; Unlock all I/O ports */
279 iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
280
281 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
282}
283
284static void ws16c48_irq_unmask(struct irq_data *data)
285{
286 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
287 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
288 const unsigned long offset = irqd_to_hwirq(data);
289 const unsigned long mask = BIT(offset);
290 const unsigned port = offset / 8;
291 unsigned long flags;
292 unsigned long port_state;
293
294 /* only the first 3 ports support interrupts */
295 if (port > 2)
296 return;
297
298 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
299
300 gpiochip_enable_irq(chip, offset);
301 ws16c48gpio->irq_mask |= mask;
302 port_state = ws16c48gpio->irq_mask >> (8 * port);
303
304 /* Select Register Page 2; Unlock all I/O ports */
305 iowrite8(0x80, &ws16c48gpio->reg->page_lock);
306
307 /* Enable interrupt */
308 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
309
310 /* Select Register Page 3; Unlock all I/O ports */
311 iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
312
313 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
314}
315
316static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
317{
318 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
319 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
320 const unsigned long offset = irqd_to_hwirq(data);
321 const unsigned long mask = BIT(offset);
322 const unsigned port = offset / 8;
323 unsigned long flags;
324 unsigned long port_state;
325
326 /* only the first 3 ports support interrupts */
327 if (port > 2)
328 return -EINVAL;
329
330 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
331
332 switch (flow_type) {
333 case IRQ_TYPE_NONE:
334 break;
335 case IRQ_TYPE_EDGE_RISING:
336 ws16c48gpio->flow_mask |= mask;
337 break;
338 case IRQ_TYPE_EDGE_FALLING:
339 ws16c48gpio->flow_mask &= ~mask;
340 break;
341 default:
342 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
343 return -EINVAL;
344 }
345
346 port_state = ws16c48gpio->flow_mask >> (8 * port);
347
348 /* Select Register Page 1; Unlock all I/O ports */
349 iowrite8(0x40, &ws16c48gpio->reg->page_lock);
350
351 /* Set interrupt polarity */
352 iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
353
354 /* Select Register Page 3; Unlock all I/O ports */
355 iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
356
357 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
358
359 return 0;
360}
361
362static const struct irq_chip ws16c48_irqchip = {
363 .name = "ws16c48",
364 .irq_ack = ws16c48_irq_ack,
365 .irq_mask = ws16c48_irq_mask,
366 .irq_unmask = ws16c48_irq_unmask,
367 .irq_set_type = ws16c48_irq_set_type,
368 .flags = IRQCHIP_IMMUTABLE,
369 GPIOCHIP_IRQ_RESOURCE_HELPERS,
370};
371
372static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
373{
374 struct ws16c48_gpio *const ws16c48gpio = dev_id;
375 struct gpio_chip *const chip = &ws16c48gpio->chip;
376 struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
377 unsigned long int_pending;
378 unsigned long port;
379 unsigned long int_id;
380 unsigned long gpio;
381
382 int_pending = ioread8(®->int_pending) & 0x7;
383 if (!int_pending)
384 return IRQ_NONE;
385
386 /* loop until all pending interrupts are handled */
387 do {
388 for_each_set_bit(port, &int_pending, 3) {
389 int_id = ioread8(reg->pol_enab_int_id + port);
390 for_each_set_bit(gpio, &int_id, 8)
391 generic_handle_domain_irq(chip->irq.domain,
392 gpio + 8*port);
393 }
394
395 int_pending = ioread8(®->int_pending) & 0x7;
396 } while (int_pending);
397
398 return IRQ_HANDLED;
399}
400
401#define WS16C48_NGPIO 48
402static const char *ws16c48_names[WS16C48_NGPIO] = {
403 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
404 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
405 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
406 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
407 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
408 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
409 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
410 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
411 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
412 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
413 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
414 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
415};
416
417static int ws16c48_irq_init_hw(struct gpio_chip *gc)
418{
419 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
420
421 /* Select Register Page 2; Unlock all I/O ports */
422 iowrite8(0x80, &ws16c48gpio->reg->page_lock);
423
424 /* Disable interrupts for all lines */
425 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
426 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
427 iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
428
429 /* Select Register Page 3; Unlock all I/O ports */
430 iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
431
432 return 0;
433}
434
435static int ws16c48_probe(struct device *dev, unsigned int id)
436{
437 struct ws16c48_gpio *ws16c48gpio;
438 const char *const name = dev_name(dev);
439 struct gpio_irq_chip *girq;
440 int err;
441
442 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
443 if (!ws16c48gpio)
444 return -ENOMEM;
445
446 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
447 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
448 base[id], base[id] + WS16C48_EXTENT);
449 return -EBUSY;
450 }
451
452 ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
453 if (!ws16c48gpio->reg)
454 return -ENOMEM;
455
456 ws16c48gpio->chip.label = name;
457 ws16c48gpio->chip.parent = dev;
458 ws16c48gpio->chip.owner = THIS_MODULE;
459 ws16c48gpio->chip.base = -1;
460 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
461 ws16c48gpio->chip.names = ws16c48_names;
462 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
463 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
464 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
465 ws16c48gpio->chip.get = ws16c48_gpio_get;
466 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
467 ws16c48gpio->chip.set = ws16c48_gpio_set;
468 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
469
470 girq = &ws16c48gpio->chip.irq;
471 gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
472 /* This will let us handle the parent IRQ in the driver */
473 girq->parent_handler = NULL;
474 girq->num_parents = 0;
475 girq->parents = NULL;
476 girq->default_type = IRQ_TYPE_NONE;
477 girq->handler = handle_edge_irq;
478 girq->init_hw = ws16c48_irq_init_hw;
479
480 raw_spin_lock_init(&ws16c48gpio->lock);
481
482 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
483 if (err) {
484 dev_err(dev, "GPIO registering failed (%d)\n", err);
485 return err;
486 }
487
488 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
489 name, ws16c48gpio);
490 if (err) {
491 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
492 return err;
493 }
494
495 return 0;
496}
497
498static struct isa_driver ws16c48_driver = {
499 .probe = ws16c48_probe,
500 .driver = {
501 .name = "ws16c48"
502 },
503};
504
505module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
506
507MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
508MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
509MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitmap.h>
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/errno.h>
10#include <linux/gpio/driver.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/interrupt.h>
14#include <linux/irqdesc.h>
15#include <linux/isa.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/spinlock.h>
20
21#define WS16C48_EXTENT 16
22#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
23
24static unsigned int base[MAX_NUM_WS16C48];
25static unsigned int num_ws16c48;
26module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
27MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
28
29static unsigned int irq[MAX_NUM_WS16C48];
30module_param_hw_array(irq, uint, irq, NULL, 0);
31MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
33/**
34 * struct ws16c48_gpio - GPIO device private data structure
35 * @chip: instance of the gpio_chip
36 * @io_state: bit I/O state (whether bit is set to input or output)
37 * @out_state: output bits state
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @irq_mask: I/O bits affected by interrupts
40 * @flow_mask: IRQ flow type mask for the respective I/O bits
41 * @base: base port address of the GPIO device
42 */
43struct ws16c48_gpio {
44 struct gpio_chip chip;
45 unsigned char io_state[6];
46 unsigned char out_state[6];
47 raw_spinlock_t lock;
48 unsigned long irq_mask;
49 unsigned long flow_mask;
50 unsigned base;
51};
52
53static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
54{
55 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
56 const unsigned port = offset / 8;
57 const unsigned mask = BIT(offset % 8);
58
59 return !!(ws16c48gpio->io_state[port] & mask);
60}
61
62static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
63{
64 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
65 const unsigned port = offset / 8;
66 const unsigned mask = BIT(offset % 8);
67 unsigned long flags;
68
69 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
70
71 ws16c48gpio->io_state[port] |= mask;
72 ws16c48gpio->out_state[port] &= ~mask;
73 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
74
75 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
76
77 return 0;
78}
79
80static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
81 unsigned offset, int value)
82{
83 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
84 const unsigned port = offset / 8;
85 const unsigned mask = BIT(offset % 8);
86 unsigned long flags;
87
88 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
89
90 ws16c48gpio->io_state[port] &= ~mask;
91 if (value)
92 ws16c48gpio->out_state[port] |= mask;
93 else
94 ws16c48gpio->out_state[port] &= ~mask;
95 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
96
97 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
98
99 return 0;
100}
101
102static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
103{
104 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
105 const unsigned port = offset / 8;
106 const unsigned mask = BIT(offset % 8);
107 unsigned long flags;
108 unsigned port_state;
109
110 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
111
112 /* ensure that GPIO is set for input */
113 if (!(ws16c48gpio->io_state[port] & mask)) {
114 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
115 return -EINVAL;
116 }
117
118 port_state = inb(ws16c48gpio->base + port);
119
120 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
121
122 return !!(port_state & mask);
123}
124
125static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
126 unsigned long *mask, unsigned long *bits)
127{
128 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
129 const unsigned int gpio_reg_size = 8;
130 size_t i;
131 const size_t num_ports = chip->ngpio / gpio_reg_size;
132 unsigned int bits_offset;
133 size_t word_index;
134 unsigned int word_offset;
135 unsigned long word_mask;
136 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
137 unsigned long port_state;
138
139 /* clear bits array to a clean slate */
140 bitmap_zero(bits, chip->ngpio);
141
142 /* get bits are evaluated a gpio port register at a time */
143 for (i = 0; i < num_ports; i++) {
144 /* gpio offset in bits array */
145 bits_offset = i * gpio_reg_size;
146
147 /* word index for bits array */
148 word_index = BIT_WORD(bits_offset);
149
150 /* gpio offset within current word of bits array */
151 word_offset = bits_offset % BITS_PER_LONG;
152
153 /* mask of get bits for current gpio within current word */
154 word_mask = mask[word_index] & (port_mask << word_offset);
155 if (!word_mask) {
156 /* no get bits in this port so skip to next one */
157 continue;
158 }
159
160 /* read bits from current gpio port */
161 port_state = inb(ws16c48gpio->base + i);
162
163 /* store acquired bits at respective bits array offset */
164 bits[word_index] |= (port_state << word_offset) & word_mask;
165 }
166
167 return 0;
168}
169
170static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
171{
172 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
173 const unsigned port = offset / 8;
174 const unsigned mask = BIT(offset % 8);
175 unsigned long flags;
176
177 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
178
179 /* ensure that GPIO is set for output */
180 if (ws16c48gpio->io_state[port] & mask) {
181 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
182 return;
183 }
184
185 if (value)
186 ws16c48gpio->out_state[port] |= mask;
187 else
188 ws16c48gpio->out_state[port] &= ~mask;
189 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
190
191 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
192}
193
194static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
195 unsigned long *mask, unsigned long *bits)
196{
197 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
198 unsigned int i;
199 const unsigned int gpio_reg_size = 8;
200 unsigned int port;
201 unsigned int iomask;
202 unsigned int bitmask;
203 unsigned long flags;
204
205 /* set bits are evaluated a gpio register size at a time */
206 for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
207 /* no more set bits in this mask word; skip to the next word */
208 if (!mask[BIT_WORD(i)]) {
209 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
210 continue;
211 }
212
213 port = i / gpio_reg_size;
214
215 /* mask out GPIO configured for input */
216 iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
217 bitmask = iomask & bits[BIT_WORD(i)];
218
219 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
220
221 /* update output state data and set device gpio register */
222 ws16c48gpio->out_state[port] &= ~iomask;
223 ws16c48gpio->out_state[port] |= bitmask;
224 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
225
226 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
227
228 /* prepare for next gpio register set */
229 mask[BIT_WORD(i)] >>= gpio_reg_size;
230 bits[BIT_WORD(i)] >>= gpio_reg_size;
231 }
232}
233
234static void ws16c48_irq_ack(struct irq_data *data)
235{
236 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
237 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
238 const unsigned long offset = irqd_to_hwirq(data);
239 const unsigned port = offset / 8;
240 const unsigned mask = BIT(offset % 8);
241 unsigned long flags;
242 unsigned port_state;
243
244 /* only the first 3 ports support interrupts */
245 if (port > 2)
246 return;
247
248 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
249
250 port_state = ws16c48gpio->irq_mask >> (8*port);
251
252 outb(0x80, ws16c48gpio->base + 7);
253 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
254 outb(port_state | mask, ws16c48gpio->base + 8 + port);
255 outb(0xC0, ws16c48gpio->base + 7);
256
257 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
258}
259
260static void ws16c48_irq_mask(struct irq_data *data)
261{
262 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
263 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
264 const unsigned long offset = irqd_to_hwirq(data);
265 const unsigned long mask = BIT(offset);
266 const unsigned port = offset / 8;
267 unsigned long flags;
268
269 /* only the first 3 ports support interrupts */
270 if (port > 2)
271 return;
272
273 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
274
275 ws16c48gpio->irq_mask &= ~mask;
276
277 outb(0x80, ws16c48gpio->base + 7);
278 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
279 outb(0xC0, ws16c48gpio->base + 7);
280
281 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
282}
283
284static void ws16c48_irq_unmask(struct irq_data *data)
285{
286 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
287 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
288 const unsigned long offset = irqd_to_hwirq(data);
289 const unsigned long mask = BIT(offset);
290 const unsigned port = offset / 8;
291 unsigned long flags;
292
293 /* only the first 3 ports support interrupts */
294 if (port > 2)
295 return;
296
297 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
298
299 ws16c48gpio->irq_mask |= mask;
300
301 outb(0x80, ws16c48gpio->base + 7);
302 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
303 outb(0xC0, ws16c48gpio->base + 7);
304
305 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
306}
307
308static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
309{
310 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
311 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
312 const unsigned long offset = irqd_to_hwirq(data);
313 const unsigned long mask = BIT(offset);
314 const unsigned port = offset / 8;
315 unsigned long flags;
316
317 /* only the first 3 ports support interrupts */
318 if (port > 2)
319 return -EINVAL;
320
321 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
322
323 switch (flow_type) {
324 case IRQ_TYPE_NONE:
325 break;
326 case IRQ_TYPE_EDGE_RISING:
327 ws16c48gpio->flow_mask |= mask;
328 break;
329 case IRQ_TYPE_EDGE_FALLING:
330 ws16c48gpio->flow_mask &= ~mask;
331 break;
332 default:
333 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
334 return -EINVAL;
335 }
336
337 outb(0x40, ws16c48gpio->base + 7);
338 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
339 outb(0xC0, ws16c48gpio->base + 7);
340
341 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
342
343 return 0;
344}
345
346static struct irq_chip ws16c48_irqchip = {
347 .name = "ws16c48",
348 .irq_ack = ws16c48_irq_ack,
349 .irq_mask = ws16c48_irq_mask,
350 .irq_unmask = ws16c48_irq_unmask,
351 .irq_set_type = ws16c48_irq_set_type
352};
353
354static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
355{
356 struct ws16c48_gpio *const ws16c48gpio = dev_id;
357 struct gpio_chip *const chip = &ws16c48gpio->chip;
358 unsigned long int_pending;
359 unsigned long port;
360 unsigned long int_id;
361 unsigned long gpio;
362
363 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
364 if (!int_pending)
365 return IRQ_NONE;
366
367 /* loop until all pending interrupts are handled */
368 do {
369 for_each_set_bit(port, &int_pending, 3) {
370 int_id = inb(ws16c48gpio->base + 8 + port);
371 for_each_set_bit(gpio, &int_id, 8)
372 generic_handle_irq(irq_find_mapping(
373 chip->irq.domain, gpio + 8*port));
374 }
375
376 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
377 } while (int_pending);
378
379 return IRQ_HANDLED;
380}
381
382#define WS16C48_NGPIO 48
383static const char *ws16c48_names[WS16C48_NGPIO] = {
384 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
385 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
386 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
387 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
388 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
389 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
390 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
391 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
392 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
393 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
394 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
395 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
396};
397
398static int ws16c48_probe(struct device *dev, unsigned int id)
399{
400 struct ws16c48_gpio *ws16c48gpio;
401 const char *const name = dev_name(dev);
402 int err;
403
404 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
405 if (!ws16c48gpio)
406 return -ENOMEM;
407
408 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
409 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
410 base[id], base[id] + WS16C48_EXTENT);
411 return -EBUSY;
412 }
413
414 ws16c48gpio->chip.label = name;
415 ws16c48gpio->chip.parent = dev;
416 ws16c48gpio->chip.owner = THIS_MODULE;
417 ws16c48gpio->chip.base = -1;
418 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
419 ws16c48gpio->chip.names = ws16c48_names;
420 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
421 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
422 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
423 ws16c48gpio->chip.get = ws16c48_gpio_get;
424 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
425 ws16c48gpio->chip.set = ws16c48_gpio_set;
426 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
427 ws16c48gpio->base = base[id];
428
429 raw_spin_lock_init(&ws16c48gpio->lock);
430
431 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
432 if (err) {
433 dev_err(dev, "GPIO registering failed (%d)\n", err);
434 return err;
435 }
436
437 /* Disable IRQ by default */
438 outb(0x80, base[id] + 7);
439 outb(0, base[id] + 8);
440 outb(0, base[id] + 9);
441 outb(0, base[id] + 10);
442 outb(0xC0, base[id] + 7);
443
444 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
445 handle_edge_irq, IRQ_TYPE_NONE);
446 if (err) {
447 dev_err(dev, "Could not add irqchip (%d)\n", err);
448 return err;
449 }
450
451 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
452 name, ws16c48gpio);
453 if (err) {
454 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
455 return err;
456 }
457
458 return 0;
459}
460
461static struct isa_driver ws16c48_driver = {
462 .probe = ws16c48_probe,
463 .driver = {
464 .name = "ws16c48"
465 },
466};
467
468module_isa_driver(ws16c48_driver, num_ws16c48);
469
470MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
471MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
472MODULE_LICENSE("GPL v2");