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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Merrifield SoC GPIO driver
4 *
5 * Copyright (c) 2016 Intel Corporation.
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/string_helpers.h>
18
19#define GCCR 0x000 /* controller configuration */
20#define GPLR 0x004 /* pin level r/o */
21#define GPDR 0x01c /* pin direction */
22#define GPSR 0x034 /* pin set w/o */
23#define GPCR 0x04c /* pin clear w/o */
24#define GRER 0x064 /* rising edge detect */
25#define GFER 0x07c /* falling edge detect */
26#define GFBR 0x094 /* glitch filter bypass */
27#define GIMR 0x0ac /* interrupt mask */
28#define GISR 0x0c4 /* interrupt source */
29#define GITR 0x300 /* input type */
30#define GLPR 0x318 /* level input polarity */
31#define GWMR 0x400 /* wake mask */
32#define GWSR 0x418 /* wake source */
33#define GSIR 0xc00 /* secure input */
34
35/* Intel Merrifield has 192 GPIO pins */
36#define MRFLD_NGPIO 192
37
38struct mrfld_gpio_pinrange {
39 unsigned int gpio_base;
40 unsigned int pin_base;
41 unsigned int npins;
42};
43
44#define GPIO_PINRANGE(gstart, gend, pstart) \
45 { \
46 .gpio_base = (gstart), \
47 .pin_base = (pstart), \
48 .npins = (gend) - (gstart) + 1, \
49 }
50
51struct mrfld_gpio {
52 struct gpio_chip chip;
53 void __iomem *reg_base;
54 raw_spinlock_t lock;
55 struct device *dev;
56};
57
58static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
59 GPIO_PINRANGE(0, 11, 146),
60 GPIO_PINRANGE(12, 13, 144),
61 GPIO_PINRANGE(14, 15, 35),
62 GPIO_PINRANGE(16, 16, 164),
63 GPIO_PINRANGE(17, 18, 105),
64 GPIO_PINRANGE(19, 22, 101),
65 GPIO_PINRANGE(23, 30, 107),
66 GPIO_PINRANGE(32, 43, 67),
67 GPIO_PINRANGE(44, 63, 195),
68 GPIO_PINRANGE(64, 67, 140),
69 GPIO_PINRANGE(68, 69, 165),
70 GPIO_PINRANGE(70, 71, 65),
71 GPIO_PINRANGE(72, 76, 228),
72 GPIO_PINRANGE(77, 86, 37),
73 GPIO_PINRANGE(87, 87, 48),
74 GPIO_PINRANGE(88, 88, 47),
75 GPIO_PINRANGE(89, 96, 49),
76 GPIO_PINRANGE(97, 97, 34),
77 GPIO_PINRANGE(102, 119, 83),
78 GPIO_PINRANGE(120, 123, 79),
79 GPIO_PINRANGE(124, 135, 115),
80 GPIO_PINRANGE(137, 142, 158),
81 GPIO_PINRANGE(154, 163, 24),
82 GPIO_PINRANGE(164, 176, 215),
83 GPIO_PINRANGE(177, 189, 127),
84 GPIO_PINRANGE(190, 191, 178),
85};
86
87static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
88 unsigned int reg_type_offset)
89{
90 struct mrfld_gpio *priv = gpiochip_get_data(chip);
91 u8 reg = offset / 32;
92
93 return priv->reg_base + reg_type_offset + reg * 4;
94}
95
96static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
97{
98 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
99
100 return !!(readl(gplr) & BIT(offset % 32));
101}
102
103static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
104 int value)
105{
106 struct mrfld_gpio *priv = gpiochip_get_data(chip);
107 void __iomem *gpsr, *gpcr;
108 unsigned long flags;
109
110 raw_spin_lock_irqsave(&priv->lock, flags);
111
112 if (value) {
113 gpsr = gpio_reg(chip, offset, GPSR);
114 writel(BIT(offset % 32), gpsr);
115 } else {
116 gpcr = gpio_reg(chip, offset, GPCR);
117 writel(BIT(offset % 32), gpcr);
118 }
119
120 raw_spin_unlock_irqrestore(&priv->lock, flags);
121}
122
123static int mrfld_gpio_direction_input(struct gpio_chip *chip,
124 unsigned int offset)
125{
126 struct mrfld_gpio *priv = gpiochip_get_data(chip);
127 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
128 unsigned long flags;
129 u32 value;
130
131 raw_spin_lock_irqsave(&priv->lock, flags);
132
133 value = readl(gpdr);
134 value &= ~BIT(offset % 32);
135 writel(value, gpdr);
136
137 raw_spin_unlock_irqrestore(&priv->lock, flags);
138
139 return 0;
140}
141
142static int mrfld_gpio_direction_output(struct gpio_chip *chip,
143 unsigned int offset, int value)
144{
145 struct mrfld_gpio *priv = gpiochip_get_data(chip);
146 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
147 unsigned long flags;
148
149 mrfld_gpio_set(chip, offset, value);
150
151 raw_spin_lock_irqsave(&priv->lock, flags);
152
153 value = readl(gpdr);
154 value |= BIT(offset % 32);
155 writel(value, gpdr);
156
157 raw_spin_unlock_irqrestore(&priv->lock, flags);
158
159 return 0;
160}
161
162static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
163{
164 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
165
166 if (readl(gpdr) & BIT(offset % 32))
167 return GPIO_LINE_DIRECTION_OUT;
168
169 return GPIO_LINE_DIRECTION_IN;
170}
171
172static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
173 unsigned int debounce)
174{
175 struct mrfld_gpio *priv = gpiochip_get_data(chip);
176 void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
177 unsigned long flags;
178 u32 value;
179
180 raw_spin_lock_irqsave(&priv->lock, flags);
181
182 if (debounce)
183 value = readl(gfbr) & ~BIT(offset % 32);
184 else
185 value = readl(gfbr) | BIT(offset % 32);
186 writel(value, gfbr);
187
188 raw_spin_unlock_irqrestore(&priv->lock, flags);
189
190 return 0;
191}
192
193static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
194 unsigned long config)
195{
196 u32 debounce;
197
198 if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) ||
199 (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) ||
200 (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN))
201 return gpiochip_generic_config(chip, offset, config);
202
203 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
204 return -ENOTSUPP;
205
206 debounce = pinconf_to_config_argument(config);
207 return mrfld_gpio_set_debounce(chip, offset, debounce);
208}
209
210static void mrfld_irq_ack(struct irq_data *d)
211{
212 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
213 u32 gpio = irqd_to_hwirq(d);
214 void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
215 unsigned long flags;
216
217 raw_spin_lock_irqsave(&priv->lock, flags);
218
219 writel(BIT(gpio % 32), gisr);
220
221 raw_spin_unlock_irqrestore(&priv->lock, flags);
222}
223
224static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask)
225{
226 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
227 unsigned long flags;
228 u32 value;
229
230 raw_spin_lock_irqsave(&priv->lock, flags);
231
232 if (unmask)
233 value = readl(gimr) | BIT(gpio % 32);
234 else
235 value = readl(gimr) & ~BIT(gpio % 32);
236 writel(value, gimr);
237
238 raw_spin_unlock_irqrestore(&priv->lock, flags);
239}
240
241static void mrfld_irq_mask(struct irq_data *d)
242{
243 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
244 u32 gpio = irqd_to_hwirq(d);
245
246 mrfld_irq_unmask_mask(priv, gpio, false);
247 gpiochip_disable_irq(&priv->chip, gpio);
248}
249
250static void mrfld_irq_unmask(struct irq_data *d)
251{
252 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
253 u32 gpio = irqd_to_hwirq(d);
254
255 gpiochip_enable_irq(&priv->chip, gpio);
256 mrfld_irq_unmask_mask(priv, gpio, true);
257}
258
259static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
260{
261 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
262 struct mrfld_gpio *priv = gpiochip_get_data(gc);
263 u32 gpio = irqd_to_hwirq(d);
264 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
265 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
266 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
267 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
268 unsigned long flags;
269 u32 value;
270
271 raw_spin_lock_irqsave(&priv->lock, flags);
272
273 if (type & IRQ_TYPE_EDGE_RISING)
274 value = readl(grer) | BIT(gpio % 32);
275 else
276 value = readl(grer) & ~BIT(gpio % 32);
277 writel(value, grer);
278
279 if (type & IRQ_TYPE_EDGE_FALLING)
280 value = readl(gfer) | BIT(gpio % 32);
281 else
282 value = readl(gfer) & ~BIT(gpio % 32);
283 writel(value, gfer);
284
285 /*
286 * To prevent glitches from triggering an unintended level interrupt,
287 * configure GLPR register first and then configure GITR.
288 */
289 if (type & IRQ_TYPE_LEVEL_LOW)
290 value = readl(glpr) | BIT(gpio % 32);
291 else
292 value = readl(glpr) & ~BIT(gpio % 32);
293 writel(value, glpr);
294
295 if (type & IRQ_TYPE_LEVEL_MASK) {
296 value = readl(gitr) | BIT(gpio % 32);
297 writel(value, gitr);
298
299 irq_set_handler_locked(d, handle_level_irq);
300 } else if (type & IRQ_TYPE_EDGE_BOTH) {
301 value = readl(gitr) & ~BIT(gpio % 32);
302 writel(value, gitr);
303
304 irq_set_handler_locked(d, handle_edge_irq);
305 }
306
307 raw_spin_unlock_irqrestore(&priv->lock, flags);
308
309 return 0;
310}
311
312static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
313{
314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 struct mrfld_gpio *priv = gpiochip_get_data(gc);
316 u32 gpio = irqd_to_hwirq(d);
317 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
318 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
319 unsigned long flags;
320 u32 value;
321
322 raw_spin_lock_irqsave(&priv->lock, flags);
323
324 /* Clear the existing wake status */
325 writel(BIT(gpio % 32), gwsr);
326
327 if (on)
328 value = readl(gwmr) | BIT(gpio % 32);
329 else
330 value = readl(gwmr) & ~BIT(gpio % 32);
331 writel(value, gwmr);
332
333 raw_spin_unlock_irqrestore(&priv->lock, flags);
334
335 dev_dbg(priv->dev, "%s wake for gpio %u\n", str_enable_disable(on), gpio);
336 return 0;
337}
338
339static const struct irq_chip mrfld_irqchip = {
340 .name = "gpio-merrifield",
341 .irq_ack = mrfld_irq_ack,
342 .irq_mask = mrfld_irq_mask,
343 .irq_unmask = mrfld_irq_unmask,
344 .irq_set_type = mrfld_irq_set_type,
345 .irq_set_wake = mrfld_irq_set_wake,
346 .flags = IRQCHIP_IMMUTABLE,
347 GPIOCHIP_IRQ_RESOURCE_HELPERS,
348};
349
350static void mrfld_irq_handler(struct irq_desc *desc)
351{
352 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
353 struct mrfld_gpio *priv = gpiochip_get_data(gc);
354 struct irq_chip *irqchip = irq_desc_get_chip(desc);
355 unsigned long base, gpio;
356
357 chained_irq_enter(irqchip, desc);
358
359 /* Check GPIO controller to check which pin triggered the interrupt */
360 for (base = 0; base < priv->chip.ngpio; base += 32) {
361 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
362 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
363 unsigned long pending, enabled;
364
365 pending = readl(gisr);
366 enabled = readl(gimr);
367
368 /* Only interrupts that are enabled */
369 pending &= enabled;
370
371 for_each_set_bit(gpio, &pending, 32)
372 generic_handle_domain_irq(gc->irq.domain, base + gpio);
373 }
374
375 chained_irq_exit(irqchip, desc);
376}
377
378static int mrfld_irq_init_hw(struct gpio_chip *chip)
379{
380 struct mrfld_gpio *priv = gpiochip_get_data(chip);
381 void __iomem *reg;
382 unsigned int base;
383
384 for (base = 0; base < priv->chip.ngpio; base += 32) {
385 /* Clear the rising-edge detect register */
386 reg = gpio_reg(&priv->chip, base, GRER);
387 writel(0, reg);
388 /* Clear the falling-edge detect register */
389 reg = gpio_reg(&priv->chip, base, GFER);
390 writel(0, reg);
391 }
392
393 return 0;
394}
395
396static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
397{
398 struct acpi_device *adev;
399 const char *name;
400
401 adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
402 if (adev) {
403 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
404 acpi_dev_put(adev);
405 } else {
406 name = "pinctrl-merrifield";
407 }
408
409 return name;
410}
411
412static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
413{
414 struct mrfld_gpio *priv = gpiochip_get_data(chip);
415 const struct mrfld_gpio_pinrange *range;
416 const char *pinctrl_dev_name;
417 unsigned int i;
418 int retval;
419
420 pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
421 if (!pinctrl_dev_name)
422 return -ENOMEM;
423
424 for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
425 range = &mrfld_gpio_ranges[i];
426 retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
427 range->gpio_base,
428 range->pin_base,
429 range->npins);
430 if (retval) {
431 dev_err(priv->dev, "failed to add GPIO pin range\n");
432 return retval;
433 }
434 }
435
436 return 0;
437}
438
439static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
440{
441 struct gpio_irq_chip *girq;
442 struct mrfld_gpio *priv;
443 u32 gpio_base, irq_base;
444 void __iomem *base;
445 int retval;
446
447 retval = pcim_enable_device(pdev);
448 if (retval)
449 return retval;
450
451 retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
452 if (retval) {
453 dev_err(&pdev->dev, "I/O memory mapping error\n");
454 return retval;
455 }
456
457 base = pcim_iomap_table(pdev)[1];
458
459 irq_base = readl(base + 0 * sizeof(u32));
460 gpio_base = readl(base + 1 * sizeof(u32));
461
462 /* Release the IO mapping, since we already get the info from BAR1 */
463 pcim_iounmap_regions(pdev, BIT(1));
464
465 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
466 if (!priv)
467 return -ENOMEM;
468
469 priv->dev = &pdev->dev;
470 priv->reg_base = pcim_iomap_table(pdev)[0];
471
472 priv->chip.label = dev_name(&pdev->dev);
473 priv->chip.parent = &pdev->dev;
474 priv->chip.request = gpiochip_generic_request;
475 priv->chip.free = gpiochip_generic_free;
476 priv->chip.direction_input = mrfld_gpio_direction_input;
477 priv->chip.direction_output = mrfld_gpio_direction_output;
478 priv->chip.get = mrfld_gpio_get;
479 priv->chip.set = mrfld_gpio_set;
480 priv->chip.get_direction = mrfld_gpio_get_direction;
481 priv->chip.set_config = mrfld_gpio_set_config;
482 priv->chip.base = gpio_base;
483 priv->chip.ngpio = MRFLD_NGPIO;
484 priv->chip.can_sleep = false;
485 priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
486
487 raw_spin_lock_init(&priv->lock);
488
489 retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
490 if (retval < 0)
491 return retval;
492
493 girq = &priv->chip.irq;
494 gpio_irq_chip_set_chip(girq, &mrfld_irqchip);
495 girq->init_hw = mrfld_irq_init_hw;
496 girq->parent_handler = mrfld_irq_handler;
497 girq->num_parents = 1;
498 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
499 sizeof(*girq->parents), GFP_KERNEL);
500 if (!girq->parents)
501 return -ENOMEM;
502 girq->parents[0] = pci_irq_vector(pdev, 0);
503 girq->first = irq_base;
504 girq->default_type = IRQ_TYPE_NONE;
505 girq->handler = handle_bad_irq;
506
507 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
508 if (retval) {
509 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
510 return retval;
511 }
512
513 pci_set_drvdata(pdev, priv);
514 return 0;
515}
516
517static const struct pci_device_id mrfld_gpio_ids[] = {
518 { PCI_VDEVICE(INTEL, 0x1199) },
519 { }
520};
521MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
522
523static struct pci_driver mrfld_gpio_driver = {
524 .name = "gpio-merrifield",
525 .id_table = mrfld_gpio_ids,
526 .probe = mrfld_gpio_probe,
527};
528
529module_pci_driver(mrfld_gpio_driver);
530
531MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
532MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
533MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Merrifield SoC GPIO driver
4 *
5 * Copyright (c) 2016 Intel Corporation.
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/pinctrl/consumer.h>
17
18#define GCCR 0x000 /* controller configuration */
19#define GPLR 0x004 /* pin level r/o */
20#define GPDR 0x01c /* pin direction */
21#define GPSR 0x034 /* pin set w/o */
22#define GPCR 0x04c /* pin clear w/o */
23#define GRER 0x064 /* rising edge detect */
24#define GFER 0x07c /* falling edge detect */
25#define GFBR 0x094 /* glitch filter bypass */
26#define GIMR 0x0ac /* interrupt mask */
27#define GISR 0x0c4 /* interrupt source */
28#define GITR 0x300 /* input type */
29#define GLPR 0x318 /* level input polarity */
30#define GWMR 0x400 /* wake mask */
31#define GWSR 0x418 /* wake source */
32#define GSIR 0xc00 /* secure input */
33
34/* Intel Merrifield has 192 GPIO pins */
35#define MRFLD_NGPIO 192
36
37struct mrfld_gpio_pinrange {
38 unsigned int gpio_base;
39 unsigned int pin_base;
40 unsigned int npins;
41};
42
43#define GPIO_PINRANGE(gstart, gend, pstart) \
44 { \
45 .gpio_base = (gstart), \
46 .pin_base = (pstart), \
47 .npins = (gend) - (gstart) + 1, \
48 }
49
50struct mrfld_gpio {
51 struct gpio_chip chip;
52 void __iomem *reg_base;
53 raw_spinlock_t lock;
54 struct device *dev;
55};
56
57static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
58 GPIO_PINRANGE(0, 11, 146),
59 GPIO_PINRANGE(12, 13, 144),
60 GPIO_PINRANGE(14, 15, 35),
61 GPIO_PINRANGE(16, 16, 164),
62 GPIO_PINRANGE(17, 18, 105),
63 GPIO_PINRANGE(19, 22, 101),
64 GPIO_PINRANGE(23, 30, 107),
65 GPIO_PINRANGE(32, 43, 67),
66 GPIO_PINRANGE(44, 63, 195),
67 GPIO_PINRANGE(64, 67, 140),
68 GPIO_PINRANGE(68, 69, 165),
69 GPIO_PINRANGE(70, 71, 65),
70 GPIO_PINRANGE(72, 76, 228),
71 GPIO_PINRANGE(77, 86, 37),
72 GPIO_PINRANGE(87, 87, 48),
73 GPIO_PINRANGE(88, 88, 47),
74 GPIO_PINRANGE(89, 96, 49),
75 GPIO_PINRANGE(97, 97, 34),
76 GPIO_PINRANGE(102, 119, 83),
77 GPIO_PINRANGE(120, 123, 79),
78 GPIO_PINRANGE(124, 135, 115),
79 GPIO_PINRANGE(137, 142, 158),
80 GPIO_PINRANGE(154, 163, 24),
81 GPIO_PINRANGE(164, 176, 215),
82 GPIO_PINRANGE(177, 189, 127),
83 GPIO_PINRANGE(190, 191, 178),
84};
85
86static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
87 unsigned int reg_type_offset)
88{
89 struct mrfld_gpio *priv = gpiochip_get_data(chip);
90 u8 reg = offset / 32;
91
92 return priv->reg_base + reg_type_offset + reg * 4;
93}
94
95static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
96{
97 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
98
99 return !!(readl(gplr) & BIT(offset % 32));
100}
101
102static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
103 int value)
104{
105 struct mrfld_gpio *priv = gpiochip_get_data(chip);
106 void __iomem *gpsr, *gpcr;
107 unsigned long flags;
108
109 raw_spin_lock_irqsave(&priv->lock, flags);
110
111 if (value) {
112 gpsr = gpio_reg(chip, offset, GPSR);
113 writel(BIT(offset % 32), gpsr);
114 } else {
115 gpcr = gpio_reg(chip, offset, GPCR);
116 writel(BIT(offset % 32), gpcr);
117 }
118
119 raw_spin_unlock_irqrestore(&priv->lock, flags);
120}
121
122static int mrfld_gpio_direction_input(struct gpio_chip *chip,
123 unsigned int offset)
124{
125 struct mrfld_gpio *priv = gpiochip_get_data(chip);
126 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
127 unsigned long flags;
128 u32 value;
129
130 raw_spin_lock_irqsave(&priv->lock, flags);
131
132 value = readl(gpdr);
133 value &= ~BIT(offset % 32);
134 writel(value, gpdr);
135
136 raw_spin_unlock_irqrestore(&priv->lock, flags);
137
138 return 0;
139}
140
141static int mrfld_gpio_direction_output(struct gpio_chip *chip,
142 unsigned int offset, int value)
143{
144 struct mrfld_gpio *priv = gpiochip_get_data(chip);
145 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
146 unsigned long flags;
147
148 mrfld_gpio_set(chip, offset, value);
149
150 raw_spin_lock_irqsave(&priv->lock, flags);
151
152 value = readl(gpdr);
153 value |= BIT(offset % 32);
154 writel(value, gpdr);
155
156 raw_spin_unlock_irqrestore(&priv->lock, flags);
157
158 return 0;
159}
160
161static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
162{
163 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
164
165 return !(readl(gpdr) & BIT(offset % 32));
166}
167
168static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
169 unsigned int debounce)
170{
171 struct mrfld_gpio *priv = gpiochip_get_data(chip);
172 void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
173 unsigned long flags;
174 u32 value;
175
176 raw_spin_lock_irqsave(&priv->lock, flags);
177
178 if (debounce)
179 value = readl(gfbr) & ~BIT(offset % 32);
180 else
181 value = readl(gfbr) | BIT(offset % 32);
182 writel(value, gfbr);
183
184 raw_spin_unlock_irqrestore(&priv->lock, flags);
185
186 return 0;
187}
188
189static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
190 unsigned long config)
191{
192 u32 debounce;
193
194 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
195 return -ENOTSUPP;
196
197 debounce = pinconf_to_config_argument(config);
198 return mrfld_gpio_set_debounce(chip, offset, debounce);
199}
200
201static void mrfld_irq_ack(struct irq_data *d)
202{
203 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
204 u32 gpio = irqd_to_hwirq(d);
205 void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
206 unsigned long flags;
207
208 raw_spin_lock_irqsave(&priv->lock, flags);
209
210 writel(BIT(gpio % 32), gisr);
211
212 raw_spin_unlock_irqrestore(&priv->lock, flags);
213}
214
215static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
216{
217 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
218 u32 gpio = irqd_to_hwirq(d);
219 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
220 unsigned long flags;
221 u32 value;
222
223 raw_spin_lock_irqsave(&priv->lock, flags);
224
225 if (unmask)
226 value = readl(gimr) | BIT(gpio % 32);
227 else
228 value = readl(gimr) & ~BIT(gpio % 32);
229 writel(value, gimr);
230
231 raw_spin_unlock_irqrestore(&priv->lock, flags);
232}
233
234static void mrfld_irq_mask(struct irq_data *d)
235{
236 mrfld_irq_unmask_mask(d, false);
237}
238
239static void mrfld_irq_unmask(struct irq_data *d)
240{
241 mrfld_irq_unmask_mask(d, true);
242}
243
244static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
245{
246 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
247 struct mrfld_gpio *priv = gpiochip_get_data(gc);
248 u32 gpio = irqd_to_hwirq(d);
249 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
250 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
251 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
252 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
253 unsigned long flags;
254 u32 value;
255
256 raw_spin_lock_irqsave(&priv->lock, flags);
257
258 if (type & IRQ_TYPE_EDGE_RISING)
259 value = readl(grer) | BIT(gpio % 32);
260 else
261 value = readl(grer) & ~BIT(gpio % 32);
262 writel(value, grer);
263
264 if (type & IRQ_TYPE_EDGE_FALLING)
265 value = readl(gfer) | BIT(gpio % 32);
266 else
267 value = readl(gfer) & ~BIT(gpio % 32);
268 writel(value, gfer);
269
270 /*
271 * To prevent glitches from triggering an unintended level interrupt,
272 * configure GLPR register first and then configure GITR.
273 */
274 if (type & IRQ_TYPE_LEVEL_LOW)
275 value = readl(glpr) | BIT(gpio % 32);
276 else
277 value = readl(glpr) & ~BIT(gpio % 32);
278 writel(value, glpr);
279
280 if (type & IRQ_TYPE_LEVEL_MASK) {
281 value = readl(gitr) | BIT(gpio % 32);
282 writel(value, gitr);
283
284 irq_set_handler_locked(d, handle_level_irq);
285 } else if (type & IRQ_TYPE_EDGE_BOTH) {
286 value = readl(gitr) & ~BIT(gpio % 32);
287 writel(value, gitr);
288
289 irq_set_handler_locked(d, handle_edge_irq);
290 }
291
292 raw_spin_unlock_irqrestore(&priv->lock, flags);
293
294 return 0;
295}
296
297static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
298{
299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
300 struct mrfld_gpio *priv = gpiochip_get_data(gc);
301 u32 gpio = irqd_to_hwirq(d);
302 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
303 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
304 unsigned long flags;
305 u32 value;
306
307 raw_spin_lock_irqsave(&priv->lock, flags);
308
309 /* Clear the existing wake status */
310 writel(BIT(gpio % 32), gwsr);
311
312 if (on)
313 value = readl(gwmr) | BIT(gpio % 32);
314 else
315 value = readl(gwmr) & ~BIT(gpio % 32);
316 writel(value, gwmr);
317
318 raw_spin_unlock_irqrestore(&priv->lock, flags);
319
320 dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
321 return 0;
322}
323
324static struct irq_chip mrfld_irqchip = {
325 .name = "gpio-merrifield",
326 .irq_ack = mrfld_irq_ack,
327 .irq_mask = mrfld_irq_mask,
328 .irq_unmask = mrfld_irq_unmask,
329 .irq_set_type = mrfld_irq_set_type,
330 .irq_set_wake = mrfld_irq_set_wake,
331};
332
333static void mrfld_irq_handler(struct irq_desc *desc)
334{
335 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
336 struct mrfld_gpio *priv = gpiochip_get_data(gc);
337 struct irq_chip *irqchip = irq_desc_get_chip(desc);
338 unsigned long base, gpio;
339
340 chained_irq_enter(irqchip, desc);
341
342 /* Check GPIO controller to check which pin triggered the interrupt */
343 for (base = 0; base < priv->chip.ngpio; base += 32) {
344 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
345 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
346 unsigned long pending, enabled;
347
348 pending = readl(gisr);
349 enabled = readl(gimr);
350
351 /* Only interrupts that are enabled */
352 pending &= enabled;
353
354 for_each_set_bit(gpio, &pending, 32) {
355 unsigned int irq;
356
357 irq = irq_find_mapping(gc->irq.domain, base + gpio);
358 generic_handle_irq(irq);
359 }
360 }
361
362 chained_irq_exit(irqchip, desc);
363}
364
365static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
366{
367 void __iomem *reg;
368 unsigned int base;
369
370 for (base = 0; base < priv->chip.ngpio; base += 32) {
371 /* Clear the rising-edge detect register */
372 reg = gpio_reg(&priv->chip, base, GRER);
373 writel(0, reg);
374 /* Clear the falling-edge detect register */
375 reg = gpio_reg(&priv->chip, base, GFER);
376 writel(0, reg);
377 }
378}
379
380static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
381{
382 struct acpi_device *adev;
383 const char *name;
384
385 adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
386 if (adev) {
387 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
388 acpi_dev_put(adev);
389 } else {
390 name = "pinctrl-merrifield";
391 }
392
393 return name;
394}
395
396static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
397{
398 const struct mrfld_gpio_pinrange *range;
399 const char *pinctrl_dev_name;
400 struct mrfld_gpio *priv;
401 u32 gpio_base, irq_base;
402 void __iomem *base;
403 unsigned int i;
404 int retval;
405
406 retval = pcim_enable_device(pdev);
407 if (retval)
408 return retval;
409
410 retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
411 if (retval) {
412 dev_err(&pdev->dev, "I/O memory mapping error\n");
413 return retval;
414 }
415
416 base = pcim_iomap_table(pdev)[1];
417
418 irq_base = readl(base);
419 gpio_base = readl(sizeof(u32) + base);
420
421 /* Release the IO mapping, since we already get the info from BAR1 */
422 pcim_iounmap_regions(pdev, BIT(1));
423
424 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
425 if (!priv)
426 return -ENOMEM;
427
428 priv->dev = &pdev->dev;
429 priv->reg_base = pcim_iomap_table(pdev)[0];
430
431 priv->chip.label = dev_name(&pdev->dev);
432 priv->chip.parent = &pdev->dev;
433 priv->chip.request = gpiochip_generic_request;
434 priv->chip.free = gpiochip_generic_free;
435 priv->chip.direction_input = mrfld_gpio_direction_input;
436 priv->chip.direction_output = mrfld_gpio_direction_output;
437 priv->chip.get = mrfld_gpio_get;
438 priv->chip.set = mrfld_gpio_set;
439 priv->chip.get_direction = mrfld_gpio_get_direction;
440 priv->chip.set_config = mrfld_gpio_set_config;
441 priv->chip.base = gpio_base;
442 priv->chip.ngpio = MRFLD_NGPIO;
443 priv->chip.can_sleep = false;
444
445 raw_spin_lock_init(&priv->lock);
446
447 pci_set_drvdata(pdev, priv);
448 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
449 if (retval) {
450 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
451 return retval;
452 }
453
454 pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
455 for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
456 range = &mrfld_gpio_ranges[i];
457 retval = gpiochip_add_pin_range(&priv->chip,
458 pinctrl_dev_name,
459 range->gpio_base,
460 range->pin_base,
461 range->npins);
462 if (retval) {
463 dev_err(&pdev->dev, "failed to add GPIO pin range\n");
464 return retval;
465 }
466 }
467
468 retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
469 handle_bad_irq, IRQ_TYPE_NONE);
470 if (retval) {
471 dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
472 return retval;
473 }
474
475 mrfld_irq_init_hw(priv);
476
477 gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
478 mrfld_irq_handler);
479
480 return 0;
481}
482
483static const struct pci_device_id mrfld_gpio_ids[] = {
484 { PCI_VDEVICE(INTEL, 0x1199) },
485 { }
486};
487MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
488
489static struct pci_driver mrfld_gpio_driver = {
490 .name = "gpio-merrifield",
491 .id_table = mrfld_gpio_ids,
492 .probe = mrfld_gpio_probe,
493};
494
495module_pci_driver(mrfld_gpio_driver);
496
497MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
498MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
499MODULE_LICENSE("GPL v2");