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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/clk.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/of_dma.h>
20#include <linux/dma-mapping.h>
21
22#include "fsl-edma-common.h"
23
24static void fsl_edma_synchronize(struct dma_chan *chan)
25{
26 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
27
28 vchan_synchronize(&fsl_chan->vchan);
29}
30
31static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
32{
33 struct fsl_edma_engine *fsl_edma = dev_id;
34 unsigned int intr, ch;
35 struct edma_regs *regs = &fsl_edma->regs;
36 struct fsl_edma_chan *fsl_chan;
37
38 intr = edma_readl(fsl_edma, regs->intl);
39 if (!intr)
40 return IRQ_NONE;
41
42 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
43 if (intr & (0x1 << ch)) {
44 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
45
46 fsl_chan = &fsl_edma->chans[ch];
47
48 spin_lock(&fsl_chan->vchan.lock);
49
50 if (!fsl_chan->edesc) {
51 /* terminate_all called before */
52 spin_unlock(&fsl_chan->vchan.lock);
53 continue;
54 }
55
56 if (!fsl_chan->edesc->iscyclic) {
57 list_del(&fsl_chan->edesc->vdesc.node);
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
59 fsl_chan->edesc = NULL;
60 fsl_chan->status = DMA_COMPLETE;
61 fsl_chan->idle = true;
62 } else {
63 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
64 }
65
66 if (!fsl_chan->edesc)
67 fsl_edma_xfer_desc(fsl_chan);
68
69 spin_unlock(&fsl_chan->vchan.lock);
70 }
71 }
72 return IRQ_HANDLED;
73}
74
75static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
76{
77 struct fsl_edma_engine *fsl_edma = dev_id;
78 unsigned int err, ch;
79 struct edma_regs *regs = &fsl_edma->regs;
80
81 err = edma_readl(fsl_edma, regs->errl);
82 if (!err)
83 return IRQ_NONE;
84
85 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
86 if (err & (0x1 << ch)) {
87 fsl_edma_disable_request(&fsl_edma->chans[ch]);
88 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
89 fsl_edma->chans[ch].status = DMA_ERROR;
90 fsl_edma->chans[ch].idle = true;
91 }
92 }
93 return IRQ_HANDLED;
94}
95
96static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
97{
98 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
99 return IRQ_HANDLED;
100
101 return fsl_edma_err_handler(irq, dev_id);
102}
103
104static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
105 struct of_dma *ofdma)
106{
107 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
108 struct dma_chan *chan, *_chan;
109 struct fsl_edma_chan *fsl_chan;
110 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
111 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
112
113 if (dma_spec->args_count != 2)
114 return NULL;
115
116 mutex_lock(&fsl_edma->fsl_edma_mutex);
117 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
118 if (chan->client_count)
119 continue;
120 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
121 chan = dma_get_slave_channel(chan);
122 if (chan) {
123 chan->device->privatecnt++;
124 fsl_chan = to_fsl_edma_chan(chan);
125 fsl_chan->slave_id = dma_spec->args[1];
126 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
127 true);
128 mutex_unlock(&fsl_edma->fsl_edma_mutex);
129 return chan;
130 }
131 }
132 }
133 mutex_unlock(&fsl_edma->fsl_edma_mutex);
134 return NULL;
135}
136
137static int
138fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
139{
140 int ret;
141
142 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
143 if (fsl_edma->txirq < 0)
144 return fsl_edma->txirq;
145
146 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
147 if (fsl_edma->errirq < 0)
148 return fsl_edma->errirq;
149
150 if (fsl_edma->txirq == fsl_edma->errirq) {
151 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
152 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
153 if (ret) {
154 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
155 return ret;
156 }
157 } else {
158 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
159 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
160 if (ret) {
161 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
162 return ret;
163 }
164
165 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
166 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
167 if (ret) {
168 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
169 return ret;
170 }
171 }
172
173 return 0;
174}
175
176static int
177fsl_edma2_irq_init(struct platform_device *pdev,
178 struct fsl_edma_engine *fsl_edma)
179{
180 int i, ret, irq;
181 int count;
182
183 count = platform_irq_count(pdev);
184 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
185 if (count <= 2) {
186 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
187 return -EINVAL;
188 }
189 /*
190 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
191 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
192 * For now, just simply request irq without IRQF_SHARED flag, since 16
193 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
194 */
195 for (i = 0; i < count; i++) {
196 irq = platform_get_irq(pdev, i);
197 if (irq < 0)
198 return -ENXIO;
199
200 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
201
202 /* The last IRQ is for eDMA err */
203 if (i == count - 1)
204 ret = devm_request_irq(&pdev->dev, irq,
205 fsl_edma_err_handler,
206 0, "eDMA2-ERR", fsl_edma);
207 else
208 ret = devm_request_irq(&pdev->dev, irq,
209 fsl_edma_tx_handler, 0,
210 fsl_edma->chans[i].chan_name,
211 fsl_edma);
212 if (ret)
213 return ret;
214 }
215
216 return 0;
217}
218
219static void fsl_edma_irq_exit(
220 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
221{
222 if (fsl_edma->txirq == fsl_edma->errirq) {
223 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
224 } else {
225 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
226 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
227 }
228}
229
230static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
231{
232 int i;
233
234 for (i = 0; i < nr_clocks; i++)
235 clk_disable_unprepare(fsl_edma->muxclk[i]);
236}
237
238static struct fsl_edma_drvdata vf610_data = {
239 .version = v1,
240 .dmamuxs = DMAMUX_NR,
241 .setup_irq = fsl_edma_irq_init,
242};
243
244static struct fsl_edma_drvdata ls1028a_data = {
245 .version = v1,
246 .dmamuxs = DMAMUX_NR,
247 .mux_swap = true,
248 .setup_irq = fsl_edma_irq_init,
249};
250
251static struct fsl_edma_drvdata imx7ulp_data = {
252 .version = v3,
253 .dmamuxs = 1,
254 .has_dmaclk = true,
255 .setup_irq = fsl_edma2_irq_init,
256};
257
258static const struct of_device_id fsl_edma_dt_ids[] = {
259 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
260 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
261 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
262 { /* sentinel */ }
263};
264MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
265
266static int fsl_edma_probe(struct platform_device *pdev)
267{
268 const struct of_device_id *of_id =
269 of_match_device(fsl_edma_dt_ids, &pdev->dev);
270 struct device_node *np = pdev->dev.of_node;
271 struct fsl_edma_engine *fsl_edma;
272 const struct fsl_edma_drvdata *drvdata = NULL;
273 struct fsl_edma_chan *fsl_chan;
274 struct edma_regs *regs;
275 struct resource *res;
276 int len, chans;
277 int ret, i;
278
279 if (of_id)
280 drvdata = of_id->data;
281 if (!drvdata) {
282 dev_err(&pdev->dev, "unable to find driver data\n");
283 return -EINVAL;
284 }
285
286 ret = of_property_read_u32(np, "dma-channels", &chans);
287 if (ret) {
288 dev_err(&pdev->dev, "Can't get dma-channels.\n");
289 return ret;
290 }
291
292 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
293 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
294 if (!fsl_edma)
295 return -ENOMEM;
296
297 fsl_edma->drvdata = drvdata;
298 fsl_edma->n_chans = chans;
299 mutex_init(&fsl_edma->fsl_edma_mutex);
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
303 if (IS_ERR(fsl_edma->membase))
304 return PTR_ERR(fsl_edma->membase);
305
306 fsl_edma_setup_regs(fsl_edma);
307 regs = &fsl_edma->regs;
308
309 if (drvdata->has_dmaclk) {
310 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
311 if (IS_ERR(fsl_edma->dmaclk)) {
312 dev_err(&pdev->dev, "Missing DMA block clock.\n");
313 return PTR_ERR(fsl_edma->dmaclk);
314 }
315
316 ret = clk_prepare_enable(fsl_edma->dmaclk);
317 if (ret) {
318 dev_err(&pdev->dev, "DMA clk block failed.\n");
319 return ret;
320 }
321 }
322
323 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
324 char clkname[32];
325
326 res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
327 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
328 if (IS_ERR(fsl_edma->muxbase[i])) {
329 /* on error: disable all previously enabled clks */
330 fsl_disable_clocks(fsl_edma, i);
331 return PTR_ERR(fsl_edma->muxbase[i]);
332 }
333
334 sprintf(clkname, "dmamux%d", i);
335 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
336 if (IS_ERR(fsl_edma->muxclk[i])) {
337 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
338 /* on error: disable all previously enabled clks */
339 fsl_disable_clocks(fsl_edma, i);
340 return PTR_ERR(fsl_edma->muxclk[i]);
341 }
342
343 ret = clk_prepare_enable(fsl_edma->muxclk[i]);
344 if (ret)
345 /* on error: disable all previously enabled clks */
346 fsl_disable_clocks(fsl_edma, i);
347
348 }
349
350 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
351
352 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
353 for (i = 0; i < fsl_edma->n_chans; i++) {
354 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
355
356 fsl_chan->edma = fsl_edma;
357 fsl_chan->pm_state = RUNNING;
358 fsl_chan->slave_id = 0;
359 fsl_chan->idle = true;
360 fsl_chan->dma_dir = DMA_NONE;
361 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
362 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
363
364 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
365 fsl_edma_chan_mux(fsl_chan, 0, false);
366 }
367
368 edma_writel(fsl_edma, ~0, regs->intl);
369 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
370 if (ret)
371 return ret;
372
373 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
374 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
375 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
376 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
377
378 fsl_edma->dma_dev.dev = &pdev->dev;
379 fsl_edma->dma_dev.device_alloc_chan_resources
380 = fsl_edma_alloc_chan_resources;
381 fsl_edma->dma_dev.device_free_chan_resources
382 = fsl_edma_free_chan_resources;
383 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
384 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
385 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
386 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
387 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
388 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
389 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
390 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
391 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
392 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
393
394 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
395 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
396 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
397
398 fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
399 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
400 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
401
402 platform_set_drvdata(pdev, fsl_edma);
403
404 ret = dma_async_device_register(&fsl_edma->dma_dev);
405 if (ret) {
406 dev_err(&pdev->dev,
407 "Can't register Freescale eDMA engine. (%d)\n", ret);
408 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
409 return ret;
410 }
411
412 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
413 if (ret) {
414 dev_err(&pdev->dev,
415 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
416 dma_async_device_unregister(&fsl_edma->dma_dev);
417 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
418 return ret;
419 }
420
421 /* enable round robin arbitration */
422 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
423
424 return 0;
425}
426
427static int fsl_edma_remove(struct platform_device *pdev)
428{
429 struct device_node *np = pdev->dev.of_node;
430 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
431
432 fsl_edma_irq_exit(pdev, fsl_edma);
433 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
434 of_dma_controller_free(np);
435 dma_async_device_unregister(&fsl_edma->dma_dev);
436 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
437
438 return 0;
439}
440
441static int fsl_edma_suspend_late(struct device *dev)
442{
443 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
444 struct fsl_edma_chan *fsl_chan;
445 unsigned long flags;
446 int i;
447
448 for (i = 0; i < fsl_edma->n_chans; i++) {
449 fsl_chan = &fsl_edma->chans[i];
450 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
451 /* Make sure chan is idle or will force disable. */
452 if (unlikely(!fsl_chan->idle)) {
453 dev_warn(dev, "WARN: There is non-idle channel.");
454 fsl_edma_disable_request(fsl_chan);
455 fsl_edma_chan_mux(fsl_chan, 0, false);
456 }
457
458 fsl_chan->pm_state = SUSPENDED;
459 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
460 }
461
462 return 0;
463}
464
465static int fsl_edma_resume_early(struct device *dev)
466{
467 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
468 struct fsl_edma_chan *fsl_chan;
469 struct edma_regs *regs = &fsl_edma->regs;
470 int i;
471
472 for (i = 0; i < fsl_edma->n_chans; i++) {
473 fsl_chan = &fsl_edma->chans[i];
474 fsl_chan->pm_state = RUNNING;
475 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
476 if (fsl_chan->slave_id != 0)
477 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
478 }
479
480 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
481
482 return 0;
483}
484
485/*
486 * eDMA provides the service to others, so it should be suspend late
487 * and resume early. When eDMA suspend, all of the clients should stop
488 * the DMA data transmission and let the channel idle.
489 */
490static const struct dev_pm_ops fsl_edma_pm_ops = {
491 .suspend_late = fsl_edma_suspend_late,
492 .resume_early = fsl_edma_resume_early,
493};
494
495static struct platform_driver fsl_edma_driver = {
496 .driver = {
497 .name = "fsl-edma",
498 .of_match_table = fsl_edma_dt_ids,
499 .pm = &fsl_edma_pm_ops,
500 },
501 .probe = fsl_edma_probe,
502 .remove = fsl_edma_remove,
503};
504
505static int __init fsl_edma_init(void)
506{
507 return platform_driver_register(&fsl_edma_driver);
508}
509subsys_initcall(fsl_edma_init);
510
511static void __exit fsl_edma_exit(void)
512{
513 platform_driver_unregister(&fsl_edma_driver);
514}
515module_exit(fsl_edma_exit);
516
517MODULE_ALIAS("platform:fsl-edma");
518MODULE_DESCRIPTION("Freescale eDMA engine driver");
519MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/clk.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/of_dma.h>
20
21#include "fsl-edma-common.h"
22
23static void fsl_edma_synchronize(struct dma_chan *chan)
24{
25 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
26
27 vchan_synchronize(&fsl_chan->vchan);
28}
29
30static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
31{
32 struct fsl_edma_engine *fsl_edma = dev_id;
33 unsigned int intr, ch;
34 struct edma_regs *regs = &fsl_edma->regs;
35 struct fsl_edma_chan *fsl_chan;
36
37 intr = edma_readl(fsl_edma, regs->intl);
38 if (!intr)
39 return IRQ_NONE;
40
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
42 if (intr & (0x1 << ch)) {
43 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
44
45 fsl_chan = &fsl_edma->chans[ch];
46
47 spin_lock(&fsl_chan->vchan.lock);
48 if (!fsl_chan->edesc->iscyclic) {
49 list_del(&fsl_chan->edesc->vdesc.node);
50 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
51 fsl_chan->edesc = NULL;
52 fsl_chan->status = DMA_COMPLETE;
53 fsl_chan->idle = true;
54 } else {
55 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
56 }
57
58 if (!fsl_chan->edesc)
59 fsl_edma_xfer_desc(fsl_chan);
60
61 spin_unlock(&fsl_chan->vchan.lock);
62 }
63 }
64 return IRQ_HANDLED;
65}
66
67static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
68{
69 struct fsl_edma_engine *fsl_edma = dev_id;
70 unsigned int err, ch;
71 struct edma_regs *regs = &fsl_edma->regs;
72
73 err = edma_readl(fsl_edma, regs->errl);
74 if (!err)
75 return IRQ_NONE;
76
77 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
78 if (err & (0x1 << ch)) {
79 fsl_edma_disable_request(&fsl_edma->chans[ch]);
80 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
81 fsl_edma->chans[ch].status = DMA_ERROR;
82 fsl_edma->chans[ch].idle = true;
83 }
84 }
85 return IRQ_HANDLED;
86}
87
88static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
89{
90 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
91 return IRQ_HANDLED;
92
93 return fsl_edma_err_handler(irq, dev_id);
94}
95
96static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
97 struct of_dma *ofdma)
98{
99 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
100 struct dma_chan *chan, *_chan;
101 struct fsl_edma_chan *fsl_chan;
102 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
103 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
104
105 if (dma_spec->args_count != 2)
106 return NULL;
107
108 mutex_lock(&fsl_edma->fsl_edma_mutex);
109 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
110 if (chan->client_count)
111 continue;
112 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
113 chan = dma_get_slave_channel(chan);
114 if (chan) {
115 chan->device->privatecnt++;
116 fsl_chan = to_fsl_edma_chan(chan);
117 fsl_chan->slave_id = dma_spec->args[1];
118 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
119 true);
120 mutex_unlock(&fsl_edma->fsl_edma_mutex);
121 return chan;
122 }
123 }
124 }
125 mutex_unlock(&fsl_edma->fsl_edma_mutex);
126 return NULL;
127}
128
129static int
130fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
131{
132 int ret;
133
134 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
135 if (fsl_edma->txirq < 0)
136 return fsl_edma->txirq;
137
138 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
139 if (fsl_edma->errirq < 0)
140 return fsl_edma->errirq;
141
142 if (fsl_edma->txirq == fsl_edma->errirq) {
143 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
144 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
145 if (ret) {
146 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
147 return ret;
148 }
149 } else {
150 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
151 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
152 if (ret) {
153 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
154 return ret;
155 }
156
157 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
158 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
159 if (ret) {
160 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
161 return ret;
162 }
163 }
164
165 return 0;
166}
167
168static int
169fsl_edma2_irq_init(struct platform_device *pdev,
170 struct fsl_edma_engine *fsl_edma)
171{
172 int i, ret, irq;
173 int count;
174
175 count = platform_irq_count(pdev);
176 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
177 if (count <= 2) {
178 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
179 return -EINVAL;
180 }
181 /*
182 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
183 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
184 * For now, just simply request irq without IRQF_SHARED flag, since 16
185 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
186 */
187 for (i = 0; i < count; i++) {
188 irq = platform_get_irq(pdev, i);
189 if (irq < 0)
190 return -ENXIO;
191
192 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
193
194 /* The last IRQ is for eDMA err */
195 if (i == count - 1)
196 ret = devm_request_irq(&pdev->dev, irq,
197 fsl_edma_err_handler,
198 0, "eDMA2-ERR", fsl_edma);
199 else
200 ret = devm_request_irq(&pdev->dev, irq,
201 fsl_edma_tx_handler, 0,
202 fsl_edma->chans[i].chan_name,
203 fsl_edma);
204 if (ret)
205 return ret;
206 }
207
208 return 0;
209}
210
211static void fsl_edma_irq_exit(
212 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
213{
214 if (fsl_edma->txirq == fsl_edma->errirq) {
215 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
216 } else {
217 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
218 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
219 }
220}
221
222static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
223{
224 int i;
225
226 for (i = 0; i < nr_clocks; i++)
227 clk_disable_unprepare(fsl_edma->muxclk[i]);
228}
229
230static struct fsl_edma_drvdata vf610_data = {
231 .version = v1,
232 .dmamuxs = DMAMUX_NR,
233 .setup_irq = fsl_edma_irq_init,
234};
235
236static struct fsl_edma_drvdata imx7ulp_data = {
237 .version = v3,
238 .dmamuxs = 1,
239 .has_dmaclk = true,
240 .setup_irq = fsl_edma2_irq_init,
241};
242
243static const struct of_device_id fsl_edma_dt_ids[] = {
244 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
245 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
246 { /* sentinel */ }
247};
248MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
249
250static int fsl_edma_probe(struct platform_device *pdev)
251{
252 const struct of_device_id *of_id =
253 of_match_device(fsl_edma_dt_ids, &pdev->dev);
254 struct device_node *np = pdev->dev.of_node;
255 struct fsl_edma_engine *fsl_edma;
256 const struct fsl_edma_drvdata *drvdata = NULL;
257 struct fsl_edma_chan *fsl_chan;
258 struct edma_regs *regs;
259 struct resource *res;
260 int len, chans;
261 int ret, i;
262
263 if (of_id)
264 drvdata = of_id->data;
265 if (!drvdata) {
266 dev_err(&pdev->dev, "unable to find driver data\n");
267 return -EINVAL;
268 }
269
270 ret = of_property_read_u32(np, "dma-channels", &chans);
271 if (ret) {
272 dev_err(&pdev->dev, "Can't get dma-channels.\n");
273 return ret;
274 }
275
276 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
277 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
278 if (!fsl_edma)
279 return -ENOMEM;
280
281 fsl_edma->drvdata = drvdata;
282 fsl_edma->n_chans = chans;
283 mutex_init(&fsl_edma->fsl_edma_mutex);
284
285 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
286 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
287 if (IS_ERR(fsl_edma->membase))
288 return PTR_ERR(fsl_edma->membase);
289
290 fsl_edma_setup_regs(fsl_edma);
291 regs = &fsl_edma->regs;
292
293 if (drvdata->has_dmaclk) {
294 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
295 if (IS_ERR(fsl_edma->dmaclk)) {
296 dev_err(&pdev->dev, "Missing DMA block clock.\n");
297 return PTR_ERR(fsl_edma->dmaclk);
298 }
299
300 ret = clk_prepare_enable(fsl_edma->dmaclk);
301 if (ret) {
302 dev_err(&pdev->dev, "DMA clk block failed.\n");
303 return ret;
304 }
305 }
306
307 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
308 char clkname[32];
309
310 res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
311 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
312 if (IS_ERR(fsl_edma->muxbase[i])) {
313 /* on error: disable all previously enabled clks */
314 fsl_disable_clocks(fsl_edma, i);
315 return PTR_ERR(fsl_edma->muxbase[i]);
316 }
317
318 sprintf(clkname, "dmamux%d", i);
319 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
320 if (IS_ERR(fsl_edma->muxclk[i])) {
321 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
322 /* on error: disable all previously enabled clks */
323 fsl_disable_clocks(fsl_edma, i);
324 return PTR_ERR(fsl_edma->muxclk[i]);
325 }
326
327 ret = clk_prepare_enable(fsl_edma->muxclk[i]);
328 if (ret)
329 /* on error: disable all previously enabled clks */
330 fsl_disable_clocks(fsl_edma, i);
331
332 }
333
334 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
335
336 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
337 for (i = 0; i < fsl_edma->n_chans; i++) {
338 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
339
340 fsl_chan->edma = fsl_edma;
341 fsl_chan->pm_state = RUNNING;
342 fsl_chan->slave_id = 0;
343 fsl_chan->idle = true;
344 fsl_chan->dma_dir = DMA_NONE;
345 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
346 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
347
348 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
349 fsl_edma_chan_mux(fsl_chan, 0, false);
350 }
351
352 edma_writel(fsl_edma, ~0, regs->intl);
353 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
354 if (ret)
355 return ret;
356
357 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
358 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
359 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
360
361 fsl_edma->dma_dev.dev = &pdev->dev;
362 fsl_edma->dma_dev.device_alloc_chan_resources
363 = fsl_edma_alloc_chan_resources;
364 fsl_edma->dma_dev.device_free_chan_resources
365 = fsl_edma_free_chan_resources;
366 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
367 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
368 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
369 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
370 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
371 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
372 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
373 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
374 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
375
376 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
377 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
378 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
379
380 platform_set_drvdata(pdev, fsl_edma);
381
382 ret = dma_async_device_register(&fsl_edma->dma_dev);
383 if (ret) {
384 dev_err(&pdev->dev,
385 "Can't register Freescale eDMA engine. (%d)\n", ret);
386 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
387 return ret;
388 }
389
390 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
391 if (ret) {
392 dev_err(&pdev->dev,
393 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
394 dma_async_device_unregister(&fsl_edma->dma_dev);
395 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
396 return ret;
397 }
398
399 /* enable round robin arbitration */
400 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
401
402 return 0;
403}
404
405static int fsl_edma_remove(struct platform_device *pdev)
406{
407 struct device_node *np = pdev->dev.of_node;
408 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
409
410 fsl_edma_irq_exit(pdev, fsl_edma);
411 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
412 of_dma_controller_free(np);
413 dma_async_device_unregister(&fsl_edma->dma_dev);
414 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
415
416 return 0;
417}
418
419static int fsl_edma_suspend_late(struct device *dev)
420{
421 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
422 struct fsl_edma_chan *fsl_chan;
423 unsigned long flags;
424 int i;
425
426 for (i = 0; i < fsl_edma->n_chans; i++) {
427 fsl_chan = &fsl_edma->chans[i];
428 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
429 /* Make sure chan is idle or will force disable. */
430 if (unlikely(!fsl_chan->idle)) {
431 dev_warn(dev, "WARN: There is non-idle channel.");
432 fsl_edma_disable_request(fsl_chan);
433 fsl_edma_chan_mux(fsl_chan, 0, false);
434 }
435
436 fsl_chan->pm_state = SUSPENDED;
437 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
438 }
439
440 return 0;
441}
442
443static int fsl_edma_resume_early(struct device *dev)
444{
445 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
446 struct fsl_edma_chan *fsl_chan;
447 struct edma_regs *regs = &fsl_edma->regs;
448 int i;
449
450 for (i = 0; i < fsl_edma->n_chans; i++) {
451 fsl_chan = &fsl_edma->chans[i];
452 fsl_chan->pm_state = RUNNING;
453 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
454 if (fsl_chan->slave_id != 0)
455 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
456 }
457
458 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
459
460 return 0;
461}
462
463/*
464 * eDMA provides the service to others, so it should be suspend late
465 * and resume early. When eDMA suspend, all of the clients should stop
466 * the DMA data transmission and let the channel idle.
467 */
468static const struct dev_pm_ops fsl_edma_pm_ops = {
469 .suspend_late = fsl_edma_suspend_late,
470 .resume_early = fsl_edma_resume_early,
471};
472
473static struct platform_driver fsl_edma_driver = {
474 .driver = {
475 .name = "fsl-edma",
476 .of_match_table = fsl_edma_dt_ids,
477 .pm = &fsl_edma_pm_ops,
478 },
479 .probe = fsl_edma_probe,
480 .remove = fsl_edma_remove,
481};
482
483static int __init fsl_edma_init(void)
484{
485 return platform_driver_register(&fsl_edma_driver);
486}
487subsys_initcall(fsl_edma_init);
488
489static void __exit fsl_edma_exit(void)
490{
491 platform_driver_unregister(&fsl_edma_driver);
492}
493module_exit(fsl_edma_exit);
494
495MODULE_ALIAS("platform:fsl-edma");
496MODULE_DESCRIPTION("Freescale eDMA engine driver");
497MODULE_LICENSE("GPL v2");