1# SPDX-License-Identifier: GPL-2.0-only
  2menuconfig PM_DEVFREQ
  3	bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
  4	select SRCU
  5	select PM_OPP
  6	help
  7	  A device may have a list of frequencies and voltages available.
  8	  devfreq, a generic DVFS framework can be registered for a device
  9	  in order to let the governor provided to devfreq choose an
 10	  operating frequency based on the device driver's policy.
 11
 12	  Each device may have its own governor and policy. Devfreq can
 13	  reevaluate the device state periodically and/or based on the
 14	  notification to "nb", a notifier block, of devfreq.
 15
 16	  Like some CPUs with CPUfreq, a device may have multiple clocks.
 17	  However, because the clock frequencies of a single device are
 18	  determined by the single device's state, an instance of devfreq
 19	  is attached to a single device and returns a "representative"
 20	  clock frequency of the device, which is also attached
 21	  to a device by 1-to-1. The device registering devfreq takes the
 22	  responsibility to "interpret" the representative frequency and
 23	  to set its every clock accordingly with the "target" callback
 24	  given to devfreq.
 25
 26	  When OPP is used with the devfreq device, it is recommended to
 27	  register devfreq's nb to the OPP's notifier head.  If OPP is
 28	  used with the devfreq device, you may use OPP helper
 29	  functions defined in devfreq.h.
 30
 31if PM_DEVFREQ
 32
 33comment "DEVFREQ Governors"
 34
 35config DEVFREQ_GOV_SIMPLE_ONDEMAND
 36	tristate "Simple Ondemand"
 37	help
 38	  Chooses frequency based on the recent load on the device. Works
 39	  similar as ONDEMAND governor of CPUFREQ does. A device with
 40	  Simple-Ondemand should be able to provide busy/total counter
 41	  values that imply the usage rate. A device may provide tuned
 42	  values to the governor with data field at devfreq_add_device().
 43
 44config DEVFREQ_GOV_PERFORMANCE
 45	tristate "Performance"
 46	help
 47	  Sets the frequency at the maximum available frequency.
 48	  This governor always returns UINT_MAX as frequency so that
 49	  the DEVFREQ framework returns the highest frequency available
 50	  at any time.
 51
 52config DEVFREQ_GOV_POWERSAVE
 53	tristate "Powersave"
 54	help
 55	  Sets the frequency at the minimum available frequency.
 56	  This governor always returns 0 as frequency so that
 57	  the DEVFREQ framework returns the lowest frequency available
 58	  at any time.
 59
 60config DEVFREQ_GOV_USERSPACE
 61	tristate "Userspace"
 62	help
 63	  Sets the frequency at the user specified one.
 64	  This governor returns the user configured frequency if there
 65	  has been an input to /sys/devices/.../userspace/set_freq.
 66	  Otherwise, the governor does not change the frequency
 67	  given at the initialization.
 68
 69config DEVFREQ_GOV_PASSIVE
 70	tristate "Passive"
 71	help
 72	  Sets the frequency based on the frequency of its parent devfreq
 73	  device. This governor does not change the frequency by itself
 74	  through sysfs entries. The passive governor recommends that
 75	  devfreq device uses the OPP table to get the frequency/voltage.
 76
 77comment "DEVFREQ Drivers"
 78
 79config ARM_EXYNOS_BUS_DEVFREQ
 80	tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
 81	depends on ARCH_EXYNOS || COMPILE_TEST
 82	select DEVFREQ_GOV_SIMPLE_ONDEMAND
 83	select DEVFREQ_GOV_PASSIVE
 84	select DEVFREQ_EVENT_EXYNOS_PPMU
 85	select PM_DEVFREQ_EVENT
 
 86	help
 87	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
 88	  Memory bus has one more group of memory bus (e.g, MIF and INT block).
 89	  Each memory bus group could contain many memoby bus block. It reads
 90	  PPMU counters of memory controllers by using DEVFREQ-event device
 91	  and adjusts the operating frequencies and voltages with OPP support.
 92	  This does not yet operate with optimal voltages.
 93
 94config ARM_IMX_BUS_DEVFREQ
 95	tristate "i.MX Generic Bus DEVFREQ Driver"
 96	depends on ARCH_MXC || COMPILE_TEST
 97	select DEVFREQ_GOV_USERSPACE
 98	help
 99	  This adds the generic DEVFREQ driver for i.MX interconnects. It
100	  allows adjusting NIC/NOC frequency.
101
102config ARM_IMX8M_DDRC_DEVFREQ
103	tristate "i.MX8M DDRC DEVFREQ Driver"
104	depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
105		(COMPILE_TEST && HAVE_ARM_SMCCC)
106	select DEVFREQ_GOV_USERSPACE
107	help
108	  This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
109	  adjusting DRAM frequency.
110
111config ARM_TEGRA_DEVFREQ
112	tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
113	depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
114		ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
115		ARCH_TEGRA_210_SOC || \
116		COMPILE_TEST
117	depends on COMMON_CLK
118	help
119	  This adds the DEVFREQ driver for the Tegra family of SoCs.
120	  It reads ACTMON counters of memory controllers and adjusts the
121	  operating frequencies and voltages with OPP support.
122
123config ARM_MEDIATEK_CCI_DEVFREQ
124	tristate "MEDIATEK CCI DEVFREQ Driver"
125	depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
126	select DEVFREQ_GOV_PASSIVE
 
 
127	help
128	  This adds a devfreq driver for MediaTek Cache Coherent Interconnect
129	  which is shared the same regulators with the cpu cluster. It can track
130	  buck voltages and update a proper CCI frequency. Use the notification
131	  to get the regulator status.
132
133config ARM_RK3399_DMC_DEVFREQ
134	tristate "ARM RK3399 DMC DEVFREQ Driver"
135	depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
136		(COMPILE_TEST && HAVE_ARM_SMCCC)
137	select DEVFREQ_EVENT_ROCKCHIP_DFI
138	select DEVFREQ_GOV_SIMPLE_ONDEMAND
139	select PM_DEVFREQ_EVENT
 
140	help
141	  This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
142	  It sets the frequency for the memory controller and reads the usage counts
143	  from hardware.
144
145config ARM_SUN8I_A33_MBUS_DEVFREQ
146	tristate "sun8i/sun50i MBUS DEVFREQ Driver"
147	depends on ARCH_SUNXI || COMPILE_TEST
148	depends on COMMON_CLK
149	select DEVFREQ_GOV_SIMPLE_ONDEMAND
150	help
151	  This adds the DEVFREQ driver for the MBUS controller in some
152	  Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
153
154source "drivers/devfreq/event/Kconfig"
155
156endif # PM_DEVFREQ

  1# SPDX-License-Identifier: GPL-2.0-only
  2menuconfig PM_DEVFREQ
  3	bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
  4	select SRCU
  5	select PM_OPP
  6	help
  7	  A device may have a list of frequencies and voltages available.
  8	  devfreq, a generic DVFS framework can be registered for a device
  9	  in order to let the governor provided to devfreq choose an
 10	  operating frequency based on the device driver's policy.
 11
 12	  Each device may have its own governor and policy. Devfreq can
 13	  reevaluate the device state periodically and/or based on the
 14	  notification to "nb", a notifier block, of devfreq.
 15
 16	  Like some CPUs with CPUfreq, a device may have multiple clocks.
 17	  However, because the clock frequencies of a single device are
 18	  determined by the single device's state, an instance of devfreq
 19	  is attached to a single device and returns a "representative"
 20	  clock frequency of the device, which is also attached
 21	  to a device by 1-to-1. The device registering devfreq takes the
 22	  responsibility to "interpret" the representative frequency and
 23	  to set its every clock accordingly with the "target" callback
 24	  given to devfreq.
 25
 26	  When OPP is used with the devfreq device, it is recommended to
 27	  register devfreq's nb to the OPP's notifier head.  If OPP is
 28	  used with the devfreq device, you may use OPP helper
 29	  functions defined in devfreq.h.
 30
 31if PM_DEVFREQ
 32
 33comment "DEVFREQ Governors"
 34
 35config DEVFREQ_GOV_SIMPLE_ONDEMAND
 36	tristate "Simple Ondemand"
 37	help
 38	  Chooses frequency based on the recent load on the device. Works
 39	  similar as ONDEMAND governor of CPUFREQ does. A device with
 40	  Simple-Ondemand should be able to provide busy/total counter
 41	  values that imply the usage rate. A device may provide tuned
 42	  values to the governor with data field at devfreq_add_device().
 43
 44config DEVFREQ_GOV_PERFORMANCE
 45	tristate "Performance"
 46	help
 47	  Sets the frequency at the maximum available frequency.
 48	  This governor always returns UINT_MAX as frequency so that
 49	  the DEVFREQ framework returns the highest frequency available
 50	  at any time.
 51
 52config DEVFREQ_GOV_POWERSAVE
 53	tristate "Powersave"
 54	help
 55	  Sets the frequency at the minimum available frequency.
 56	  This governor always returns 0 as frequency so that
 57	  the DEVFREQ framework returns the lowest frequency available
 58	  at any time.
 59
 60config DEVFREQ_GOV_USERSPACE
 61	tristate "Userspace"
 62	help
 63	  Sets the frequency at the user specified one.
 64	  This governor returns the user configured frequency if there
 65	  has been an input to /sys/devices/.../power/devfreq_set_freq.
 66	  Otherwise, the governor does not change the frequency
 67	  given at the initialization.
 68
 69config DEVFREQ_GOV_PASSIVE
 70	tristate "Passive"
 71	help
 72	  Sets the frequency based on the frequency of its parent devfreq
 73	  device. This governor does not change the frequency by itself
 74	  through sysfs entries. The passive governor recommends that
 75	  devfreq device uses the OPP table to get the frequency/voltage.
 76
 77comment "DEVFREQ Drivers"
 78
 79config ARM_EXYNOS_BUS_DEVFREQ
 80	tristate "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
 81	depends on ARCH_EXYNOS || COMPILE_TEST
 82	select DEVFREQ_GOV_SIMPLE_ONDEMAND
 83	select DEVFREQ_GOV_PASSIVE
 84	select DEVFREQ_EVENT_EXYNOS_PPMU
 85	select PM_DEVFREQ_EVENT
 86	select PM_OPP
 87	help
 88	  This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
 89	  Memory bus has one more group of memory bus (e.g, MIF and INT block).
 90	  Each memory bus group could contain many memoby bus block. It reads
 91	  PPMU counters of memory controllers by using DEVFREQ-event device
 92	  and adjusts the operating frequencies and voltages with OPP support.
 93	  This does not yet operate with optimal voltages.
 94
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 95config ARM_TEGRA_DEVFREQ
 96	tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
 97	depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
 98		ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
 99		ARCH_TEGRA_210_SOC || \
100		COMPILE_TEST
101	select PM_OPP
102	help
103	  This adds the DEVFREQ driver for the Tegra family of SoCs.
104	  It reads ACTMON counters of memory controllers and adjusts the
105	  operating frequencies and voltages with OPP support.
106
107config ARM_TEGRA20_DEVFREQ
108	tristate "NVIDIA Tegra20 DEVFREQ Driver"
109	depends on (TEGRA_MC && TEGRA20_EMC) || COMPILE_TEST
110	depends on COMMON_CLK
111	select DEVFREQ_GOV_SIMPLE_ONDEMAND
112	select PM_OPP
113	help
114	  This adds the DEVFREQ driver for the Tegra20 family of SoCs.
115	  It reads Memory Controller counters and adjusts the operating
116	  frequencies and voltages with OPP support.
 
117
118config ARM_RK3399_DMC_DEVFREQ
119	tristate "ARM RK3399 DMC DEVFREQ Driver"
120	depends on ARCH_ROCKCHIP
 
121	select DEVFREQ_EVENT_ROCKCHIP_DFI
122	select DEVFREQ_GOV_SIMPLE_ONDEMAND
123	select PM_DEVFREQ_EVENT
124	select PM_OPP
125	help
126          This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
127          It sets the frequency for the memory controller and reads the usage counts
128          from hardware.
 
 
 
 
 
 
 
 
 
129
130source "drivers/devfreq/event/Kconfig"
131
132endif # PM_DEVFREQ