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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21/*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34/* Header files */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/skbuff.h>
39#include <linux/atmdev.h>
40#include <linux/atm.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/types.h>
44#include <linux/string.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/timer.h>
49#include <linux/interrupt.h>
50#include <linux/bitops.h>
51#include <linux/slab.h>
52#include <linux/idr.h>
53#include <asm/io.h>
54#include <linux/uaccess.h>
55#include <linux/atomic.h>
56#include <linux/etherdevice.h>
57#include "nicstar.h"
58#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59#include "suni.h"
60#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62#include "idt77105.h"
63#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65/* Additional code */
66
67#include "nicstarmac.c"
68
69/* Configurable parameters */
70
71#undef PHY_LOOPBACK
72#undef TX_DEBUG
73#undef RX_DEBUG
74#undef GENERAL_DEBUG
75#undef EXTRA_DEBUG
76
77/* Do not touch these */
78
79#ifdef TX_DEBUG
80#define TXPRINTK(args...) printk(args)
81#else
82#define TXPRINTK(args...)
83#endif /* TX_DEBUG */
84
85#ifdef RX_DEBUG
86#define RXPRINTK(args...) printk(args)
87#else
88#define RXPRINTK(args...)
89#endif /* RX_DEBUG */
90
91#ifdef GENERAL_DEBUG
92#define PRINTK(args...) printk(args)
93#else
94#define PRINTK(args...) do {} while (0)
95#endif /* GENERAL_DEBUG */
96
97#ifdef EXTRA_DEBUG
98#define XPRINTK(args...) printk(args)
99#else
100#define XPRINTK(args...)
101#endif /* EXTRA_DEBUG */
102
103/* Macros */
104
105#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107#define NS_DELAY mdelay(1)
108
109#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111#ifndef ATM_SKB
112#define ATM_SKB(s) (&(s)->atm)
113#endif
114
115#define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118/* Function declarations */
119
120static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123static int ns_init_card(int i, struct pci_dev *pcidev);
124static void ns_init_card_error(ns_dev * card, int error);
125static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127static void push_rxbufs(ns_dev *, struct sk_buff *);
128static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129static int ns_open(struct atm_vcc *vcc);
130static void ns_close(struct atm_vcc *vcc);
131static void fill_tst(ns_dev * card, int n, vc_map * vc);
132static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
134static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 struct sk_buff *skb, bool may_sleep);
136static void process_tsq(ns_dev * card);
137static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138static void process_rsq(ns_dev * card);
139static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
145static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
146static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
147#ifdef EXTRA_DEBUG
148static void which_list(ns_dev * card, struct sk_buff *skb);
149#endif
150static void ns_poll(struct timer_list *unused);
151static void ns_phy_put(struct atm_dev *dev, unsigned char value,
152 unsigned long addr);
153static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
154
155/* Global variables */
156
157static struct ns_dev *cards[NS_MAX_CARDS];
158static unsigned num_cards;
159static const struct atmdev_ops atm_ops = {
160 .open = ns_open,
161 .close = ns_close,
162 .ioctl = ns_ioctl,
163 .send = ns_send,
164 .send_bh = ns_send_bh,
165 .phy_put = ns_phy_put,
166 .phy_get = ns_phy_get,
167 .proc_read = ns_proc_read,
168 .owner = THIS_MODULE,
169};
170
171static struct timer_list ns_timer;
172static char *mac[NS_MAX_CARDS];
173module_param_array(mac, charp, NULL, 0);
174MODULE_LICENSE("GPL");
175
176/* Functions */
177
178static int nicstar_init_one(struct pci_dev *pcidev,
179 const struct pci_device_id *ent)
180{
181 static int index = -1;
182 unsigned int error;
183
184 index++;
185 cards[index] = NULL;
186
187 error = ns_init_card(index, pcidev);
188 if (error) {
189 cards[index--] = NULL; /* don't increment index */
190 goto err_out;
191 }
192
193 return 0;
194err_out:
195 return -ENODEV;
196}
197
198static void nicstar_remove_one(struct pci_dev *pcidev)
199{
200 int i, j;
201 ns_dev *card = pci_get_drvdata(pcidev);
202 struct sk_buff *hb;
203 struct sk_buff *iovb;
204 struct sk_buff *lb;
205 struct sk_buff *sb;
206
207 i = card->index;
208
209 if (cards[i] == NULL)
210 return;
211
212 if (card->atmdev->phy && card->atmdev->phy->stop)
213 card->atmdev->phy->stop(card->atmdev);
214
215 /* Stop everything */
216 writel(0x00000000, card->membase + CFG);
217
218 /* De-register device */
219 atm_dev_deregister(card->atmdev);
220
221 /* Disable PCI device */
222 pci_disable_device(pcidev);
223
224 /* Free up resources */
225 j = 0;
226 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
228 dev_kfree_skb_any(hb);
229 j++;
230 }
231 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
232 j = 0;
233 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
234 card->iovpool.count);
235 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
236 dev_kfree_skb_any(iovb);
237 j++;
238 }
239 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
240 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
241 dev_kfree_skb_any(lb);
242 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
243 dev_kfree_skb_any(sb);
244 free_scq(card, card->scq0, NULL);
245 for (j = 0; j < NS_FRSCD_NUM; j++) {
246 if (card->scd2vc[j] != NULL)
247 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
248 }
249 idr_destroy(&card->idr);
250 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251 card->rsq.org, card->rsq.dma);
252 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253 card->tsq.org, card->tsq.dma);
254 free_irq(card->pcidev->irq, card);
255 iounmap(card->membase);
256 kfree(card);
257}
258
259static const struct pci_device_id nicstar_pci_tbl[] = {
260 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
261 {0,} /* terminate list */
262};
263
264MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
265
266static struct pci_driver nicstar_driver = {
267 .name = "nicstar",
268 .id_table = nicstar_pci_tbl,
269 .probe = nicstar_init_one,
270 .remove = nicstar_remove_one,
271};
272
273static int __init nicstar_init(void)
274{
275 unsigned error = 0; /* Initialized to remove compile warning */
276
277 XPRINTK("nicstar: nicstar_init() called.\n");
278
279 error = pci_register_driver(&nicstar_driver);
280
281 TXPRINTK("nicstar: TX debug enabled.\n");
282 RXPRINTK("nicstar: RX debug enabled.\n");
283 PRINTK("nicstar: General debug enabled.\n");
284#ifdef PHY_LOOPBACK
285 printk("nicstar: using PHY loopback.\n");
286#endif /* PHY_LOOPBACK */
287 XPRINTK("nicstar: nicstar_init() returned.\n");
288
289 if (!error) {
290 timer_setup(&ns_timer, ns_poll, 0);
291 ns_timer.expires = jiffies + NS_POLL_PERIOD;
292 add_timer(&ns_timer);
293 }
294
295 return error;
296}
297
298static void __exit nicstar_cleanup(void)
299{
300 XPRINTK("nicstar: nicstar_cleanup() called.\n");
301
302 del_timer_sync(&ns_timer);
303
304 pci_unregister_driver(&nicstar_driver);
305
306 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
307}
308
309static u32 ns_read_sram(ns_dev * card, u32 sram_address)
310{
311 unsigned long flags;
312 u32 data;
313 sram_address <<= 2;
314 sram_address &= 0x0007FFFC; /* address must be dword aligned */
315 sram_address |= 0x50000000; /* SRAM read command */
316 spin_lock_irqsave(&card->res_lock, flags);
317 while (CMD_BUSY(card)) ;
318 writel(sram_address, card->membase + CMD);
319 while (CMD_BUSY(card)) ;
320 data = readl(card->membase + DR0);
321 spin_unlock_irqrestore(&card->res_lock, flags);
322 return data;
323}
324
325static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
326 int count)
327{
328 unsigned long flags;
329 int i, c;
330 count--; /* count range now is 0..3 instead of 1..4 */
331 c = count;
332 c <<= 2; /* to use increments of 4 */
333 spin_lock_irqsave(&card->res_lock, flags);
334 while (CMD_BUSY(card)) ;
335 for (i = 0; i <= c; i += 4)
336 writel(*(value++), card->membase + i);
337 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
338 so card->membase + DR0 == card->membase */
339 sram_address <<= 2;
340 sram_address &= 0x0007FFFC;
341 sram_address |= (0x40000000 | count);
342 writel(sram_address, card->membase + CMD);
343 spin_unlock_irqrestore(&card->res_lock, flags);
344}
345
346static int ns_init_card(int i, struct pci_dev *pcidev)
347{
348 int j;
349 struct ns_dev *card = NULL;
350 unsigned char pci_latency;
351 unsigned error;
352 u32 data;
353 u32 u32d[4];
354 u32 ns_cfg_rctsize;
355 int bcount;
356 unsigned long membase;
357
358 error = 0;
359
360 if (pci_enable_device(pcidev)) {
361 printk("nicstar%d: can't enable PCI device\n", i);
362 error = 2;
363 ns_init_card_error(card, error);
364 return error;
365 }
366 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
367 printk(KERN_WARNING
368 "nicstar%d: No suitable DMA available.\n", i);
369 error = 2;
370 ns_init_card_error(card, error);
371 return error;
372 }
373
374 card = kmalloc(sizeof(*card), GFP_KERNEL);
375 if (!card) {
376 printk
377 ("nicstar%d: can't allocate memory for device structure.\n",
378 i);
379 error = 2;
380 ns_init_card_error(card, error);
381 return error;
382 }
383 cards[i] = card;
384 spin_lock_init(&card->int_lock);
385 spin_lock_init(&card->res_lock);
386
387 pci_set_drvdata(pcidev, card);
388
389 card->index = i;
390 card->atmdev = NULL;
391 card->pcidev = pcidev;
392 membase = pci_resource_start(pcidev, 1);
393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
394 if (!card->membase) {
395 printk("nicstar%d: can't ioremap() membase.\n", i);
396 error = 3;
397 ns_init_card_error(card, error);
398 return error;
399 }
400 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
401
402 pci_set_master(pcidev);
403
404 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
405 printk("nicstar%d: can't read PCI latency timer.\n", i);
406 error = 6;
407 ns_init_card_error(card, error);
408 return error;
409 }
410#ifdef NS_PCI_LATENCY
411 if (pci_latency < NS_PCI_LATENCY) {
412 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
413 NS_PCI_LATENCY);
414 for (j = 1; j < 4; j++) {
415 if (pci_write_config_byte
416 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
417 break;
418 }
419 if (j == 4) {
420 printk
421 ("nicstar%d: can't set PCI latency timer to %d.\n",
422 i, NS_PCI_LATENCY);
423 error = 7;
424 ns_init_card_error(card, error);
425 return error;
426 }
427 }
428#endif /* NS_PCI_LATENCY */
429
430 /* Clear timer overflow */
431 data = readl(card->membase + STAT);
432 if (data & NS_STAT_TMROF)
433 writel(NS_STAT_TMROF, card->membase + STAT);
434
435 /* Software reset */
436 writel(NS_CFG_SWRST, card->membase + CFG);
437 NS_DELAY;
438 writel(0x00000000, card->membase + CFG);
439
440 /* PHY reset */
441 writel(0x00000008, card->membase + GP);
442 NS_DELAY;
443 writel(0x00000001, card->membase + GP);
444 NS_DELAY;
445 while (CMD_BUSY(card)) ;
446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
447 NS_DELAY;
448
449 /* Detect PHY type */
450 while (CMD_BUSY(card)) ;
451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
452 while (CMD_BUSY(card)) ;
453 data = readl(card->membase + DR0);
454 switch (data) {
455 case 0x00000009:
456 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
457 card->max_pcr = ATM_25_PCR;
458 while (CMD_BUSY(card)) ;
459 writel(0x00000008, card->membase + DR0);
460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
461 /* Clear an eventual pending interrupt */
462 writel(NS_STAT_SFBQF, card->membase + STAT);
463#ifdef PHY_LOOPBACK
464 while (CMD_BUSY(card)) ;
465 writel(0x00000022, card->membase + DR0);
466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
467#endif /* PHY_LOOPBACK */
468 break;
469 case 0x00000030:
470 case 0x00000031:
471 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
472 card->max_pcr = ATM_OC3_PCR;
473#ifdef PHY_LOOPBACK
474 while (CMD_BUSY(card)) ;
475 writel(0x00000002, card->membase + DR0);
476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
477#endif /* PHY_LOOPBACK */
478 break;
479 default:
480 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
481 error = 8;
482 ns_init_card_error(card, error);
483 return error;
484 }
485 writel(0x00000000, card->membase + GP);
486
487 /* Determine SRAM size */
488 data = 0x76543210;
489 ns_write_sram(card, 0x1C003, &data, 1);
490 data = 0x89ABCDEF;
491 ns_write_sram(card, 0x14003, &data, 1);
492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
493 ns_read_sram(card, 0x1C003) == 0x76543210)
494 card->sram_size = 128;
495 else
496 card->sram_size = 32;
497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
498
499 card->rct_size = NS_MAX_RCTSIZE;
500
501#if (NS_MAX_RCTSIZE == 4096)
502 if (card->sram_size == 128)
503 printk
504 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505 i);
506#elif (NS_MAX_RCTSIZE == 16384)
507 if (card->sram_size == 32) {
508 printk
509 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
510 i);
511 card->rct_size = 4096;
512 }
513#else
514#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
515#endif
516
517 card->vpibits = NS_VPIBITS;
518 if (card->rct_size == 4096)
519 card->vcibits = 12 - NS_VPIBITS;
520 else /* card->rct_size == 16384 */
521 card->vcibits = 14 - NS_VPIBITS;
522
523 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
524 if (mac[i] == NULL)
525 nicstar_init_eprom(card->membase);
526
527 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
528 writel(0x00000000, card->membase + VPM);
529
530 card->intcnt = 0;
531 if (request_irq
532 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
533 pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
534 error = 9;
535 ns_init_card_error(card, error);
536 return error;
537 }
538
539 /* Initialize TSQ */
540 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
541 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
542 &card->tsq.dma, GFP_KERNEL);
543 if (card->tsq.org == NULL) {
544 printk("nicstar%d: can't allocate TSQ.\n", i);
545 error = 10;
546 ns_init_card_error(card, error);
547 return error;
548 }
549 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
550 card->tsq.next = card->tsq.base;
551 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
552 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
553 ns_tsi_init(card->tsq.base + j);
554 writel(0x00000000, card->membase + TSQH);
555 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
556 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
557
558 /* Initialize RSQ */
559 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
560 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
561 &card->rsq.dma, GFP_KERNEL);
562 if (card->rsq.org == NULL) {
563 printk("nicstar%d: can't allocate RSQ.\n", i);
564 error = 11;
565 ns_init_card_error(card, error);
566 return error;
567 }
568 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
569 card->rsq.next = card->rsq.base;
570 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
571 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
572 ns_rsqe_init(card->rsq.base + j);
573 writel(0x00000000, card->membase + RSQH);
574 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
575 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
576
577 /* Initialize SCQ0, the only VBR SCQ used */
578 card->scq1 = NULL;
579 card->scq2 = NULL;
580 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
581 if (card->scq0 == NULL) {
582 printk("nicstar%d: can't get SCQ0.\n", i);
583 error = 12;
584 ns_init_card_error(card, error);
585 return error;
586 }
587 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
588 u32d[1] = (u32) 0x00000000;
589 u32d[2] = (u32) 0xffffffff;
590 u32d[3] = (u32) 0x00000000;
591 ns_write_sram(card, NS_VRSCD0, u32d, 4);
592 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
593 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
594 card->scq0->scd = NS_VRSCD0;
595 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
596
597 /* Initialize TSTs */
598 card->tst_addr = NS_TST0;
599 card->tst_free_entries = NS_TST_NUM_ENTRIES;
600 data = NS_TST_OPCODE_VARIABLE;
601 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
602 ns_write_sram(card, NS_TST0 + j, &data, 1);
603 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
604 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
605 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
606 ns_write_sram(card, NS_TST1 + j, &data, 1);
607 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
608 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
609 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
610 card->tste2vc[j] = NULL;
611 writel(NS_TST0 << 2, card->membase + TSTB);
612
613 /* Initialize RCT. AAL type is set on opening the VC. */
614#ifdef RCQ_SUPPORT
615 u32d[0] = NS_RCTE_RAWCELLINTEN;
616#else
617 u32d[0] = 0x00000000;
618#endif /* RCQ_SUPPORT */
619 u32d[1] = 0x00000000;
620 u32d[2] = 0x00000000;
621 u32d[3] = 0xFFFFFFFF;
622 for (j = 0; j < card->rct_size; j++)
623 ns_write_sram(card, j * 4, u32d, 4);
624
625 memset(card->vcmap, 0, sizeof(card->vcmap));
626
627 for (j = 0; j < NS_FRSCD_NUM; j++)
628 card->scd2vc[j] = NULL;
629
630 /* Initialize buffer levels */
631 card->sbnr.min = MIN_SB;
632 card->sbnr.init = NUM_SB;
633 card->sbnr.max = MAX_SB;
634 card->lbnr.min = MIN_LB;
635 card->lbnr.init = NUM_LB;
636 card->lbnr.max = MAX_LB;
637 card->iovnr.min = MIN_IOVB;
638 card->iovnr.init = NUM_IOVB;
639 card->iovnr.max = MAX_IOVB;
640 card->hbnr.min = MIN_HB;
641 card->hbnr.init = NUM_HB;
642 card->hbnr.max = MAX_HB;
643
644 card->sm_handle = NULL;
645 card->sm_addr = 0x00000000;
646 card->lg_handle = NULL;
647 card->lg_addr = 0x00000000;
648
649 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
650
651 idr_init(&card->idr);
652
653 /* Pre-allocate some huge buffers */
654 skb_queue_head_init(&card->hbpool.queue);
655 card->hbpool.count = 0;
656 for (j = 0; j < NUM_HB; j++) {
657 struct sk_buff *hb;
658 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
659 if (hb == NULL) {
660 printk
661 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
662 i, j, NUM_HB);
663 error = 13;
664 ns_init_card_error(card, error);
665 return error;
666 }
667 NS_PRV_BUFTYPE(hb) = BUF_NONE;
668 skb_queue_tail(&card->hbpool.queue, hb);
669 card->hbpool.count++;
670 }
671
672 /* Allocate large buffers */
673 skb_queue_head_init(&card->lbpool.queue);
674 card->lbpool.count = 0; /* Not used */
675 for (j = 0; j < NUM_LB; j++) {
676 struct sk_buff *lb;
677 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
678 if (lb == NULL) {
679 printk
680 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
681 i, j, NUM_LB);
682 error = 14;
683 ns_init_card_error(card, error);
684 return error;
685 }
686 NS_PRV_BUFTYPE(lb) = BUF_LG;
687 skb_queue_tail(&card->lbpool.queue, lb);
688 skb_reserve(lb, NS_SMBUFSIZE);
689 push_rxbufs(card, lb);
690 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
691 if (j == 1) {
692 card->rcbuf = lb;
693 card->rawcell = (struct ns_rcqe *) lb->data;
694 card->rawch = NS_PRV_DMA(lb);
695 }
696 }
697 /* Test for strange behaviour which leads to crashes */
698 if ((bcount =
699 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
700 printk
701 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
702 i, j, bcount);
703 error = 14;
704 ns_init_card_error(card, error);
705 return error;
706 }
707
708 /* Allocate small buffers */
709 skb_queue_head_init(&card->sbpool.queue);
710 card->sbpool.count = 0; /* Not used */
711 for (j = 0; j < NUM_SB; j++) {
712 struct sk_buff *sb;
713 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
714 if (sb == NULL) {
715 printk
716 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
717 i, j, NUM_SB);
718 error = 15;
719 ns_init_card_error(card, error);
720 return error;
721 }
722 NS_PRV_BUFTYPE(sb) = BUF_SM;
723 skb_queue_tail(&card->sbpool.queue, sb);
724 skb_reserve(sb, NS_AAL0_HEADER);
725 push_rxbufs(card, sb);
726 }
727 /* Test for strange behaviour which leads to crashes */
728 if ((bcount =
729 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
730 printk
731 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
732 i, j, bcount);
733 error = 15;
734 ns_init_card_error(card, error);
735 return error;
736 }
737
738 /* Allocate iovec buffers */
739 skb_queue_head_init(&card->iovpool.queue);
740 card->iovpool.count = 0;
741 for (j = 0; j < NUM_IOVB; j++) {
742 struct sk_buff *iovb;
743 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
744 if (iovb == NULL) {
745 printk
746 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
747 i, j, NUM_IOVB);
748 error = 16;
749 ns_init_card_error(card, error);
750 return error;
751 }
752 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
753 skb_queue_tail(&card->iovpool.queue, iovb);
754 card->iovpool.count++;
755 }
756
757 /* Configure NICStAR */
758 if (card->rct_size == 4096)
759 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
760 else /* (card->rct_size == 16384) */
761 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
762
763 card->efbie = 1;
764
765 /* Register device */
766 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
767 -1, NULL);
768 if (card->atmdev == NULL) {
769 printk("nicstar%d: can't register device.\n", i);
770 error = 17;
771 ns_init_card_error(card, error);
772 return error;
773 }
774
775 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
776 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777 card->atmdev->esi, 6);
778 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
779 nicstar_read_eprom(card->membase,
780 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
781 card->atmdev->esi, 6);
782 }
783 }
784
785 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
786
787 card->atmdev->dev_data = card;
788 card->atmdev->ci_range.vpi_bits = card->vpibits;
789 card->atmdev->ci_range.vci_bits = card->vcibits;
790 card->atmdev->link_rate = card->max_pcr;
791 card->atmdev->phy = NULL;
792
793#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
794 if (card->max_pcr == ATM_OC3_PCR)
795 suni_init(card->atmdev);
796#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
797
798#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
799 if (card->max_pcr == ATM_25_PCR)
800 idt77105_init(card->atmdev);
801#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
802
803 if (card->atmdev->phy && card->atmdev->phy->start)
804 card->atmdev->phy->start(card->atmdev);
805
806 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
807 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
808 NS_CFG_PHYIE, card->membase + CFG);
809
810 num_cards++;
811
812 return error;
813}
814
815static void ns_init_card_error(ns_dev *card, int error)
816{
817 if (error >= 17) {
818 writel(0x00000000, card->membase + CFG);
819 }
820 if (error >= 16) {
821 struct sk_buff *iovb;
822 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
823 dev_kfree_skb_any(iovb);
824 }
825 if (error >= 15) {
826 struct sk_buff *sb;
827 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
828 dev_kfree_skb_any(sb);
829 free_scq(card, card->scq0, NULL);
830 }
831 if (error >= 14) {
832 struct sk_buff *lb;
833 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
834 dev_kfree_skb_any(lb);
835 }
836 if (error >= 13) {
837 struct sk_buff *hb;
838 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
839 dev_kfree_skb_any(hb);
840 }
841 if (error >= 12) {
842 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
843 card->rsq.org, card->rsq.dma);
844 }
845 if (error >= 11) {
846 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
847 card->tsq.org, card->tsq.dma);
848 }
849 if (error >= 10) {
850 free_irq(card->pcidev->irq, card);
851 }
852 if (error >= 4) {
853 iounmap(card->membase);
854 }
855 if (error >= 3) {
856 pci_disable_device(card->pcidev);
857 kfree(card);
858 }
859}
860
861static scq_info *get_scq(ns_dev *card, int size, u32 scd)
862{
863 scq_info *scq;
864
865 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
866 return NULL;
867
868 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
869 if (!scq)
870 return NULL;
871 scq->org = dma_alloc_coherent(&card->pcidev->dev,
872 2 * size, &scq->dma, GFP_KERNEL);
873 if (!scq->org) {
874 kfree(scq);
875 return NULL;
876 }
877 scq->skb = kcalloc(size / NS_SCQE_SIZE, sizeof(*scq->skb),
878 GFP_KERNEL);
879 if (!scq->skb) {
880 dma_free_coherent(&card->pcidev->dev,
881 2 * size, scq->org, scq->dma);
882 kfree(scq);
883 return NULL;
884 }
885 scq->num_entries = size / NS_SCQE_SIZE;
886 scq->base = PTR_ALIGN(scq->org, size);
887 scq->next = scq->base;
888 scq->last = scq->base + (scq->num_entries - 1);
889 scq->tail = scq->last;
890 scq->scd = scd;
891 scq->tbd_count = 0;
892 init_waitqueue_head(&scq->scqfull_waitq);
893 scq->full = 0;
894 spin_lock_init(&scq->lock);
895
896 return scq;
897}
898
899/* For variable rate SCQ vcc must be NULL */
900static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
901{
902 int i;
903
904 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
905 for (i = 0; i < scq->num_entries; i++) {
906 if (scq->skb[i] != NULL) {
907 vcc = ATM_SKB(scq->skb[i])->vcc;
908 if (vcc->pop != NULL)
909 vcc->pop(vcc, scq->skb[i]);
910 else
911 dev_kfree_skb_any(scq->skb[i]);
912 }
913 } else { /* vcc must be != NULL */
914
915 if (vcc == NULL) {
916 printk
917 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
918 for (i = 0; i < scq->num_entries; i++)
919 dev_kfree_skb_any(scq->skb[i]);
920 } else
921 for (i = 0; i < scq->num_entries; i++) {
922 if (scq->skb[i] != NULL) {
923 if (vcc->pop != NULL)
924 vcc->pop(vcc, scq->skb[i]);
925 else
926 dev_kfree_skb_any(scq->skb[i]);
927 }
928 }
929 }
930 kfree(scq->skb);
931 dma_free_coherent(&card->pcidev->dev,
932 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
933 VBR_SCQSIZE : CBR_SCQSIZE),
934 scq->org, scq->dma);
935 kfree(scq);
936}
937
938/* The handles passed must be pointers to the sk_buff containing the small
939 or large buffer(s) cast to u32. */
940static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
941{
942 struct sk_buff *handle1, *handle2;
943 int id1, id2;
944 u32 addr1, addr2;
945 u32 stat;
946 unsigned long flags;
947
948 /* *BARF* */
949 handle2 = NULL;
950 addr2 = 0;
951 handle1 = skb;
952 addr1 = dma_map_single(&card->pcidev->dev,
953 skb->data,
954 (NS_PRV_BUFTYPE(skb) == BUF_SM
955 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
956 DMA_TO_DEVICE);
957 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
958
959#ifdef GENERAL_DEBUG
960 if (!addr1)
961 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
962 card->index);
963#endif /* GENERAL_DEBUG */
964
965 stat = readl(card->membase + STAT);
966 card->sbfqc = ns_stat_sfbqc_get(stat);
967 card->lbfqc = ns_stat_lfbqc_get(stat);
968 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
969 if (!addr2) {
970 if (card->sm_addr) {
971 addr2 = card->sm_addr;
972 handle2 = card->sm_handle;
973 card->sm_addr = 0x00000000;
974 card->sm_handle = NULL;
975 } else { /* (!sm_addr) */
976
977 card->sm_addr = addr1;
978 card->sm_handle = handle1;
979 }
980 }
981 } else { /* buf_type == BUF_LG */
982
983 if (!addr2) {
984 if (card->lg_addr) {
985 addr2 = card->lg_addr;
986 handle2 = card->lg_handle;
987 card->lg_addr = 0x00000000;
988 card->lg_handle = NULL;
989 } else { /* (!lg_addr) */
990
991 card->lg_addr = addr1;
992 card->lg_handle = handle1;
993 }
994 }
995 }
996
997 if (addr2) {
998 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
999 if (card->sbfqc >= card->sbnr.max) {
1000 skb_unlink(handle1, &card->sbpool.queue);
1001 dev_kfree_skb_any(handle1);
1002 skb_unlink(handle2, &card->sbpool.queue);
1003 dev_kfree_skb_any(handle2);
1004 return;
1005 } else
1006 card->sbfqc += 2;
1007 } else { /* (buf_type == BUF_LG) */
1008
1009 if (card->lbfqc >= card->lbnr.max) {
1010 skb_unlink(handle1, &card->lbpool.queue);
1011 dev_kfree_skb_any(handle1);
1012 skb_unlink(handle2, &card->lbpool.queue);
1013 dev_kfree_skb_any(handle2);
1014 return;
1015 } else
1016 card->lbfqc += 2;
1017 }
1018
1019 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1020 if (id1 < 0)
1021 goto out;
1022
1023 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1024 if (id2 < 0)
1025 goto out;
1026
1027 spin_lock_irqsave(&card->res_lock, flags);
1028 while (CMD_BUSY(card)) ;
1029 writel(addr2, card->membase + DR3);
1030 writel(id2, card->membase + DR2);
1031 writel(addr1, card->membase + DR1);
1032 writel(id1, card->membase + DR0);
1033 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1034 card->membase + CMD);
1035 spin_unlock_irqrestore(&card->res_lock, flags);
1036
1037 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1038 card->index,
1039 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1040 addr1, addr2);
1041 }
1042
1043 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1044 card->lbfqc >= card->lbnr.min) {
1045 card->efbie = 1;
1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1047 card->membase + CFG);
1048 }
1049
1050out:
1051 return;
1052}
1053
1054static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1055{
1056 u32 stat_r;
1057 ns_dev *card;
1058 struct atm_dev *dev;
1059 unsigned long flags;
1060
1061 card = (ns_dev *) dev_id;
1062 dev = card->atmdev;
1063 card->intcnt++;
1064
1065 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1066
1067 spin_lock_irqsave(&card->int_lock, flags);
1068
1069 stat_r = readl(card->membase + STAT);
1070
1071 /* Transmit Status Indicator has been written to T. S. Queue */
1072 if (stat_r & NS_STAT_TSIF) {
1073 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1074 process_tsq(card);
1075 writel(NS_STAT_TSIF, card->membase + STAT);
1076 }
1077
1078 /* Incomplete CS-PDU has been transmitted */
1079 if (stat_r & NS_STAT_TXICP) {
1080 writel(NS_STAT_TXICP, card->membase + STAT);
1081 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1082 card->index);
1083 }
1084
1085 /* Transmit Status Queue 7/8 full */
1086 if (stat_r & NS_STAT_TSQF) {
1087 writel(NS_STAT_TSQF, card->membase + STAT);
1088 PRINTK("nicstar%d: TSQ full.\n", card->index);
1089 process_tsq(card);
1090 }
1091
1092 /* Timer overflow */
1093 if (stat_r & NS_STAT_TMROF) {
1094 writel(NS_STAT_TMROF, card->membase + STAT);
1095 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1096 }
1097
1098 /* PHY device interrupt signal active */
1099 if (stat_r & NS_STAT_PHYI) {
1100 writel(NS_STAT_PHYI, card->membase + STAT);
1101 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1102 if (dev->phy && dev->phy->interrupt) {
1103 dev->phy->interrupt(dev);
1104 }
1105 }
1106
1107 /* Small Buffer Queue is full */
1108 if (stat_r & NS_STAT_SFBQF) {
1109 writel(NS_STAT_SFBQF, card->membase + STAT);
1110 printk("nicstar%d: Small free buffer queue is full.\n",
1111 card->index);
1112 }
1113
1114 /* Large Buffer Queue is full */
1115 if (stat_r & NS_STAT_LFBQF) {
1116 writel(NS_STAT_LFBQF, card->membase + STAT);
1117 printk("nicstar%d: Large free buffer queue is full.\n",
1118 card->index);
1119 }
1120
1121 /* Receive Status Queue is full */
1122 if (stat_r & NS_STAT_RSQF) {
1123 writel(NS_STAT_RSQF, card->membase + STAT);
1124 printk("nicstar%d: RSQ full.\n", card->index);
1125 process_rsq(card);
1126 }
1127
1128 /* Complete CS-PDU received */
1129 if (stat_r & NS_STAT_EOPDU) {
1130 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1131 process_rsq(card);
1132 writel(NS_STAT_EOPDU, card->membase + STAT);
1133 }
1134
1135 /* Raw cell received */
1136 if (stat_r & NS_STAT_RAWCF) {
1137 writel(NS_STAT_RAWCF, card->membase + STAT);
1138#ifndef RCQ_SUPPORT
1139 printk("nicstar%d: Raw cell received and no support yet...\n",
1140 card->index);
1141#endif /* RCQ_SUPPORT */
1142 /* NOTE: the following procedure may keep a raw cell pending until the
1143 next interrupt. As this preliminary support is only meant to
1144 avoid buffer leakage, this is not an issue. */
1145 while (readl(card->membase + RAWCT) != card->rawch) {
1146
1147 if (ns_rcqe_islast(card->rawcell)) {
1148 struct sk_buff *oldbuf;
1149
1150 oldbuf = card->rcbuf;
1151 card->rcbuf = idr_find(&card->idr,
1152 ns_rcqe_nextbufhandle(card->rawcell));
1153 card->rawch = NS_PRV_DMA(card->rcbuf);
1154 card->rawcell = (struct ns_rcqe *)
1155 card->rcbuf->data;
1156 recycle_rx_buf(card, oldbuf);
1157 } else {
1158 card->rawch += NS_RCQE_SIZE;
1159 card->rawcell++;
1160 }
1161 }
1162 }
1163
1164 /* Small buffer queue is empty */
1165 if (stat_r & NS_STAT_SFBQE) {
1166 int i;
1167 struct sk_buff *sb;
1168
1169 writel(NS_STAT_SFBQE, card->membase + STAT);
1170 printk("nicstar%d: Small free buffer queue empty.\n",
1171 card->index);
1172 for (i = 0; i < card->sbnr.min; i++) {
1173 sb = dev_alloc_skb(NS_SMSKBSIZE);
1174 if (sb == NULL) {
1175 writel(readl(card->membase + CFG) &
1176 ~NS_CFG_EFBIE, card->membase + CFG);
1177 card->efbie = 0;
1178 break;
1179 }
1180 NS_PRV_BUFTYPE(sb) = BUF_SM;
1181 skb_queue_tail(&card->sbpool.queue, sb);
1182 skb_reserve(sb, NS_AAL0_HEADER);
1183 push_rxbufs(card, sb);
1184 }
1185 card->sbfqc = i;
1186 process_rsq(card);
1187 }
1188
1189 /* Large buffer queue empty */
1190 if (stat_r & NS_STAT_LFBQE) {
1191 int i;
1192 struct sk_buff *lb;
1193
1194 writel(NS_STAT_LFBQE, card->membase + STAT);
1195 printk("nicstar%d: Large free buffer queue empty.\n",
1196 card->index);
1197 for (i = 0; i < card->lbnr.min; i++) {
1198 lb = dev_alloc_skb(NS_LGSKBSIZE);
1199 if (lb == NULL) {
1200 writel(readl(card->membase + CFG) &
1201 ~NS_CFG_EFBIE, card->membase + CFG);
1202 card->efbie = 0;
1203 break;
1204 }
1205 NS_PRV_BUFTYPE(lb) = BUF_LG;
1206 skb_queue_tail(&card->lbpool.queue, lb);
1207 skb_reserve(lb, NS_SMBUFSIZE);
1208 push_rxbufs(card, lb);
1209 }
1210 card->lbfqc = i;
1211 process_rsq(card);
1212 }
1213
1214 /* Receive Status Queue is 7/8 full */
1215 if (stat_r & NS_STAT_RSQAF) {
1216 writel(NS_STAT_RSQAF, card->membase + STAT);
1217 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1218 process_rsq(card);
1219 }
1220
1221 spin_unlock_irqrestore(&card->int_lock, flags);
1222 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1223 return IRQ_HANDLED;
1224}
1225
1226static int ns_open(struct atm_vcc *vcc)
1227{
1228 ns_dev *card;
1229 vc_map *vc;
1230 unsigned long tmpl, modl;
1231 int tcr, tcra; /* target cell rate, and absolute value */
1232 int n = 0; /* Number of entries in the TST. Initialized to remove
1233 the compiler warning. */
1234 u32 u32d[4];
1235 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1236 warning. How I wish compilers were clever enough to
1237 tell which variables can truly be used
1238 uninitialized... */
1239 int inuse; /* tx or rx vc already in use by another vcc */
1240 short vpi = vcc->vpi;
1241 int vci = vcc->vci;
1242
1243 card = (ns_dev *) vcc->dev->dev_data;
1244 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1245 vci);
1246 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1247 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1248 return -EINVAL;
1249 }
1250
1251 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1252 vcc->dev_data = vc;
1253
1254 inuse = 0;
1255 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1256 inuse = 1;
1257 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1258 inuse += 2;
1259 if (inuse) {
1260 printk("nicstar%d: %s vci already in use.\n", card->index,
1261 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1262 return -EINVAL;
1263 }
1264
1265 set_bit(ATM_VF_ADDR, &vcc->flags);
1266
1267 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1268 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1269 needed to do that. */
1270 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1271 scq_info *scq;
1272
1273 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1274 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1275 /* Check requested cell rate and availability of SCD */
1276 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1277 && vcc->qos.txtp.min_pcr == 0) {
1278 PRINTK
1279 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1280 card->index);
1281 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1282 clear_bit(ATM_VF_ADDR, &vcc->flags);
1283 return -EINVAL;
1284 }
1285
1286 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1287 tcra = tcr >= 0 ? tcr : -tcr;
1288
1289 PRINTK("nicstar%d: target cell rate = %d.\n",
1290 card->index, vcc->qos.txtp.max_pcr);
1291
1292 tmpl =
1293 (unsigned long)tcra *(unsigned long)
1294 NS_TST_NUM_ENTRIES;
1295 modl = tmpl % card->max_pcr;
1296
1297 n = (int)(tmpl / card->max_pcr);
1298 if (tcr > 0) {
1299 if (modl > 0)
1300 n++;
1301 } else if (tcr == 0) {
1302 if ((n =
1303 (card->tst_free_entries -
1304 NS_TST_RESERVED)) <= 0) {
1305 PRINTK
1306 ("nicstar%d: no CBR bandwidth free.\n",
1307 card->index);
1308 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1309 clear_bit(ATM_VF_ADDR, &vcc->flags);
1310 return -EINVAL;
1311 }
1312 }
1313
1314 if (n == 0) {
1315 printk
1316 ("nicstar%d: selected bandwidth < granularity.\n",
1317 card->index);
1318 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1319 clear_bit(ATM_VF_ADDR, &vcc->flags);
1320 return -EINVAL;
1321 }
1322
1323 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1324 PRINTK
1325 ("nicstar%d: not enough free CBR bandwidth.\n",
1326 card->index);
1327 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1328 clear_bit(ATM_VF_ADDR, &vcc->flags);
1329 return -EINVAL;
1330 } else
1331 card->tst_free_entries -= n;
1332
1333 XPRINTK("nicstar%d: writing %d tst entries.\n",
1334 card->index, n);
1335 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1336 if (card->scd2vc[frscdi] == NULL) {
1337 card->scd2vc[frscdi] = vc;
1338 break;
1339 }
1340 }
1341 if (frscdi == NS_FRSCD_NUM) {
1342 PRINTK
1343 ("nicstar%d: no SCD available for CBR channel.\n",
1344 card->index);
1345 card->tst_free_entries += n;
1346 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1347 clear_bit(ATM_VF_ADDR, &vcc->flags);
1348 return -EBUSY;
1349 }
1350
1351 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1352
1353 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1354 if (scq == NULL) {
1355 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1356 card->index);
1357 card->scd2vc[frscdi] = NULL;
1358 card->tst_free_entries += n;
1359 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1360 clear_bit(ATM_VF_ADDR, &vcc->flags);
1361 return -ENOMEM;
1362 }
1363 vc->scq = scq;
1364 u32d[0] = scq_virt_to_bus(scq, scq->base);
1365 u32d[1] = (u32) 0x00000000;
1366 u32d[2] = (u32) 0xffffffff;
1367 u32d[3] = (u32) 0x00000000;
1368 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1369
1370 fill_tst(card, n, vc);
1371 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1372 vc->cbr_scd = 0x00000000;
1373 vc->scq = card->scq0;
1374 }
1375
1376 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1377 vc->tx = 1;
1378 vc->tx_vcc = vcc;
1379 vc->tbd_count = 0;
1380 }
1381 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1382 u32 status;
1383
1384 vc->rx = 1;
1385 vc->rx_vcc = vcc;
1386 vc->rx_iov = NULL;
1387
1388 /* Open the connection in hardware */
1389 if (vcc->qos.aal == ATM_AAL5)
1390 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1391 else /* vcc->qos.aal == ATM_AAL0 */
1392 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1393#ifdef RCQ_SUPPORT
1394 status |= NS_RCTE_RAWCELLINTEN;
1395#endif /* RCQ_SUPPORT */
1396 ns_write_sram(card,
1397 NS_RCT +
1398 (vpi << card->vcibits | vci) *
1399 NS_RCT_ENTRY_SIZE, &status, 1);
1400 }
1401
1402 }
1403
1404 set_bit(ATM_VF_READY, &vcc->flags);
1405 return 0;
1406}
1407
1408static void ns_close(struct atm_vcc *vcc)
1409{
1410 vc_map *vc;
1411 ns_dev *card;
1412 u32 data;
1413 int i;
1414
1415 vc = vcc->dev_data;
1416 card = vcc->dev->dev_data;
1417 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1418 (int)vcc->vpi, vcc->vci);
1419
1420 clear_bit(ATM_VF_READY, &vcc->flags);
1421
1422 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1423 u32 addr;
1424 unsigned long flags;
1425
1426 addr =
1427 NS_RCT +
1428 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1429 spin_lock_irqsave(&card->res_lock, flags);
1430 while (CMD_BUSY(card)) ;
1431 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1432 card->membase + CMD);
1433 spin_unlock_irqrestore(&card->res_lock, flags);
1434
1435 vc->rx = 0;
1436 if (vc->rx_iov != NULL) {
1437 struct sk_buff *iovb;
1438 u32 stat;
1439
1440 stat = readl(card->membase + STAT);
1441 card->sbfqc = ns_stat_sfbqc_get(stat);
1442 card->lbfqc = ns_stat_lfbqc_get(stat);
1443
1444 PRINTK
1445 ("nicstar%d: closing a VC with pending rx buffers.\n",
1446 card->index);
1447 iovb = vc->rx_iov;
1448 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1449 NS_PRV_IOVCNT(iovb));
1450 NS_PRV_IOVCNT(iovb) = 0;
1451 spin_lock_irqsave(&card->int_lock, flags);
1452 recycle_iov_buf(card, iovb);
1453 spin_unlock_irqrestore(&card->int_lock, flags);
1454 vc->rx_iov = NULL;
1455 }
1456 }
1457
1458 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1459 vc->tx = 0;
1460 }
1461
1462 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1463 unsigned long flags;
1464 ns_scqe *scqep;
1465 scq_info *scq;
1466
1467 scq = vc->scq;
1468
1469 for (;;) {
1470 spin_lock_irqsave(&scq->lock, flags);
1471 scqep = scq->next;
1472 if (scqep == scq->base)
1473 scqep = scq->last;
1474 else
1475 scqep--;
1476 if (scqep == scq->tail) {
1477 spin_unlock_irqrestore(&scq->lock, flags);
1478 break;
1479 }
1480 /* If the last entry is not a TSR, place one in the SCQ in order to
1481 be able to completely drain it and then close. */
1482 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1483 ns_scqe tsr;
1484 u32 scdi, scqi;
1485 u32 data;
1486 int index;
1487
1488 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1489 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1490 scqi = scq->next - scq->base;
1491 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1492 tsr.word_3 = 0x00000000;
1493 tsr.word_4 = 0x00000000;
1494 *scq->next = tsr;
1495 index = (int)scqi;
1496 scq->skb[index] = NULL;
1497 if (scq->next == scq->last)
1498 scq->next = scq->base;
1499 else
1500 scq->next++;
1501 data = scq_virt_to_bus(scq, scq->next);
1502 ns_write_sram(card, scq->scd, &data, 1);
1503 }
1504 spin_unlock_irqrestore(&scq->lock, flags);
1505 schedule();
1506 }
1507
1508 /* Free all TST entries */
1509 data = NS_TST_OPCODE_VARIABLE;
1510 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1511 if (card->tste2vc[i] == vc) {
1512 ns_write_sram(card, card->tst_addr + i, &data,
1513 1);
1514 card->tste2vc[i] = NULL;
1515 card->tst_free_entries++;
1516 }
1517 }
1518
1519 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1520 free_scq(card, vc->scq, vcc);
1521 }
1522
1523 /* remove all references to vcc before deleting it */
1524 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1525 unsigned long flags;
1526 scq_info *scq = card->scq0;
1527
1528 spin_lock_irqsave(&scq->lock, flags);
1529
1530 for (i = 0; i < scq->num_entries; i++) {
1531 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1532 ATM_SKB(scq->skb[i])->vcc = NULL;
1533 atm_return(vcc, scq->skb[i]->truesize);
1534 PRINTK
1535 ("nicstar: deleted pending vcc mapping\n");
1536 }
1537 }
1538
1539 spin_unlock_irqrestore(&scq->lock, flags);
1540 }
1541
1542 vcc->dev_data = NULL;
1543 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1544 clear_bit(ATM_VF_ADDR, &vcc->flags);
1545
1546#ifdef RX_DEBUG
1547 {
1548 u32 stat, cfg;
1549 stat = readl(card->membase + STAT);
1550 cfg = readl(card->membase + CFG);
1551 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1552 printk
1553 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1554 card->tsq.base, card->tsq.next,
1555 card->tsq.last, readl(card->membase + TSQT));
1556 printk
1557 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1558 card->rsq.base, card->rsq.next,
1559 card->rsq.last, readl(card->membase + RSQT));
1560 printk("Empty free buffer queue interrupt %s \n",
1561 card->efbie ? "enabled" : "disabled");
1562 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1563 ns_stat_sfbqc_get(stat), card->sbpool.count,
1564 ns_stat_lfbqc_get(stat), card->lbpool.count);
1565 printk("hbpool.count = %d iovpool.count = %d \n",
1566 card->hbpool.count, card->iovpool.count);
1567 }
1568#endif /* RX_DEBUG */
1569}
1570
1571static void fill_tst(ns_dev * card, int n, vc_map * vc)
1572{
1573 u32 new_tst;
1574 unsigned long cl;
1575 int e, r;
1576 u32 data;
1577
1578 /* It would be very complicated to keep the two TSTs synchronized while
1579 assuring that writes are only made to the inactive TST. So, for now I
1580 will use only one TST. If problems occur, I will change this again */
1581
1582 new_tst = card->tst_addr;
1583
1584 /* Fill procedure */
1585
1586 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1587 if (card->tste2vc[e] == NULL)
1588 break;
1589 }
1590 if (e == NS_TST_NUM_ENTRIES) {
1591 printk("nicstar%d: No free TST entries found. \n", card->index);
1592 return;
1593 }
1594
1595 r = n;
1596 cl = NS_TST_NUM_ENTRIES;
1597 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1598
1599 while (r > 0) {
1600 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1601 card->tste2vc[e] = vc;
1602 ns_write_sram(card, new_tst + e, &data, 1);
1603 cl -= NS_TST_NUM_ENTRIES;
1604 r--;
1605 }
1606
1607 if (++e == NS_TST_NUM_ENTRIES) {
1608 e = 0;
1609 }
1610 cl += n;
1611 }
1612
1613 /* End of fill procedure */
1614
1615 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1616 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1617 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1618 card->tst_addr = new_tst;
1619}
1620
1621static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
1622{
1623 ns_dev *card;
1624 vc_map *vc;
1625 scq_info *scq;
1626 unsigned long buflen;
1627 ns_scqe scqe;
1628 u32 flags; /* TBD flags, not CPU flags */
1629
1630 card = vcc->dev->dev_data;
1631 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1632 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1633 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1634 card->index);
1635 atomic_inc(&vcc->stats->tx_err);
1636 dev_kfree_skb_any(skb);
1637 return -EINVAL;
1638 }
1639
1640 if (!vc->tx) {
1641 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1642 card->index);
1643 atomic_inc(&vcc->stats->tx_err);
1644 dev_kfree_skb_any(skb);
1645 return -EINVAL;
1646 }
1647
1648 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1649 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1650 card->index);
1651 atomic_inc(&vcc->stats->tx_err);
1652 dev_kfree_skb_any(skb);
1653 return -EINVAL;
1654 }
1655
1656 if (skb_shinfo(skb)->nr_frags != 0) {
1657 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1658 atomic_inc(&vcc->stats->tx_err);
1659 dev_kfree_skb_any(skb);
1660 return -EINVAL;
1661 }
1662
1663 ATM_SKB(skb)->vcc = vcc;
1664
1665 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1666 skb->len, DMA_TO_DEVICE);
1667
1668 if (vcc->qos.aal == ATM_AAL5) {
1669 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1670 flags = NS_TBD_AAL5;
1671 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1672 scqe.word_3 = cpu_to_le32(skb->len);
1673 scqe.word_4 =
1674 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1675 ATM_SKB(skb)->
1676 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1677 flags |= NS_TBD_EOPDU;
1678 } else { /* (vcc->qos.aal == ATM_AAL0) */
1679
1680 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1681 flags = NS_TBD_AAL0;
1682 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1683 scqe.word_3 = cpu_to_le32(0x00000000);
1684 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1685 flags |= NS_TBD_EOPDU;
1686 scqe.word_4 =
1687 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1688 /* Force the VPI/VCI to be the same as in VCC struct */
1689 scqe.word_4 |=
1690 cpu_to_le32((((u32) vcc->
1691 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1692 vci) <<
1693 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1694 }
1695
1696 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1697 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1698 scq = ((vc_map *) vcc->dev_data)->scq;
1699 } else {
1700 scqe.word_1 =
1701 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1702 scq = card->scq0;
1703 }
1704
1705 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
1706 atomic_inc(&vcc->stats->tx_err);
1707 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1708 DMA_TO_DEVICE);
1709 dev_kfree_skb_any(skb);
1710 return -EIO;
1711 }
1712 atomic_inc(&vcc->stats->tx);
1713
1714 return 0;
1715}
1716
1717static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1718{
1719 return _ns_send(vcc, skb, true);
1720}
1721
1722static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
1723{
1724 return _ns_send(vcc, skb, false);
1725}
1726
1727static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1728 struct sk_buff *skb, bool may_sleep)
1729{
1730 unsigned long flags;
1731 ns_scqe tsr;
1732 u32 scdi, scqi;
1733 int scq_is_vbr;
1734 u32 data;
1735 int index;
1736
1737 spin_lock_irqsave(&scq->lock, flags);
1738 while (scq->tail == scq->next) {
1739 if (!may_sleep) {
1740 spin_unlock_irqrestore(&scq->lock, flags);
1741 printk("nicstar%d: Error pushing TBD.\n", card->index);
1742 return 1;
1743 }
1744
1745 scq->full = 1;
1746 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1747 scq->tail != scq->next,
1748 scq->lock,
1749 SCQFULL_TIMEOUT);
1750
1751 if (scq->full) {
1752 spin_unlock_irqrestore(&scq->lock, flags);
1753 printk("nicstar%d: Timeout pushing TBD.\n",
1754 card->index);
1755 return 1;
1756 }
1757 }
1758 *scq->next = *tbd;
1759 index = (int)(scq->next - scq->base);
1760 scq->skb[index] = skb;
1761 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1762 card->index, skb, index);
1763 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1764 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1765 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1766 scq->next);
1767 if (scq->next == scq->last)
1768 scq->next = scq->base;
1769 else
1770 scq->next++;
1771
1772 vc->tbd_count++;
1773 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1774 scq->tbd_count++;
1775 scq_is_vbr = 1;
1776 } else
1777 scq_is_vbr = 0;
1778
1779 if (vc->tbd_count >= MAX_TBD_PER_VC
1780 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1781 int has_run = 0;
1782
1783 while (scq->tail == scq->next) {
1784 if (!may_sleep) {
1785 data = scq_virt_to_bus(scq, scq->next);
1786 ns_write_sram(card, scq->scd, &data, 1);
1787 spin_unlock_irqrestore(&scq->lock, flags);
1788 printk("nicstar%d: Error pushing TSR.\n",
1789 card->index);
1790 return 0;
1791 }
1792
1793 scq->full = 1;
1794 if (has_run++)
1795 break;
1796 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1797 scq->tail != scq->next,
1798 scq->lock,
1799 SCQFULL_TIMEOUT);
1800 }
1801
1802 if (!scq->full) {
1803 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1804 if (scq_is_vbr)
1805 scdi = NS_TSR_SCDISVBR;
1806 else
1807 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1808 scqi = scq->next - scq->base;
1809 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1810 tsr.word_3 = 0x00000000;
1811 tsr.word_4 = 0x00000000;
1812
1813 *scq->next = tsr;
1814 index = (int)scqi;
1815 scq->skb[index] = NULL;
1816 XPRINTK
1817 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1818 card->index, le32_to_cpu(tsr.word_1),
1819 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1820 le32_to_cpu(tsr.word_4), scq->next);
1821 if (scq->next == scq->last)
1822 scq->next = scq->base;
1823 else
1824 scq->next++;
1825 vc->tbd_count = 0;
1826 scq->tbd_count = 0;
1827 } else
1828 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1829 card->index);
1830 }
1831 data = scq_virt_to_bus(scq, scq->next);
1832 ns_write_sram(card, scq->scd, &data, 1);
1833
1834 spin_unlock_irqrestore(&scq->lock, flags);
1835
1836 return 0;
1837}
1838
1839static void process_tsq(ns_dev * card)
1840{
1841 u32 scdi;
1842 scq_info *scq;
1843 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1844 int serviced_entries; /* flag indicating at least on entry was serviced */
1845
1846 serviced_entries = 0;
1847
1848 if (card->tsq.next == card->tsq.last)
1849 one_ahead = card->tsq.base;
1850 else
1851 one_ahead = card->tsq.next + 1;
1852
1853 if (one_ahead == card->tsq.last)
1854 two_ahead = card->tsq.base;
1855 else
1856 two_ahead = one_ahead + 1;
1857
1858 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1859 !ns_tsi_isempty(two_ahead))
1860 /* At most two empty, as stated in the 77201 errata */
1861 {
1862 serviced_entries = 1;
1863
1864 /* Skip the one or two possible empty entries */
1865 while (ns_tsi_isempty(card->tsq.next)) {
1866 if (card->tsq.next == card->tsq.last)
1867 card->tsq.next = card->tsq.base;
1868 else
1869 card->tsq.next++;
1870 }
1871
1872 if (!ns_tsi_tmrof(card->tsq.next)) {
1873 scdi = ns_tsi_getscdindex(card->tsq.next);
1874 if (scdi == NS_TSI_SCDISVBR)
1875 scq = card->scq0;
1876 else {
1877 if (card->scd2vc[scdi] == NULL) {
1878 printk
1879 ("nicstar%d: could not find VC from SCD index.\n",
1880 card->index);
1881 ns_tsi_init(card->tsq.next);
1882 return;
1883 }
1884 scq = card->scd2vc[scdi]->scq;
1885 }
1886 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1887 scq->full = 0;
1888 wake_up_interruptible(&(scq->scqfull_waitq));
1889 }
1890
1891 ns_tsi_init(card->tsq.next);
1892 previous = card->tsq.next;
1893 if (card->tsq.next == card->tsq.last)
1894 card->tsq.next = card->tsq.base;
1895 else
1896 card->tsq.next++;
1897
1898 if (card->tsq.next == card->tsq.last)
1899 one_ahead = card->tsq.base;
1900 else
1901 one_ahead = card->tsq.next + 1;
1902
1903 if (one_ahead == card->tsq.last)
1904 two_ahead = card->tsq.base;
1905 else
1906 two_ahead = one_ahead + 1;
1907 }
1908
1909 if (serviced_entries)
1910 writel(PTR_DIFF(previous, card->tsq.base),
1911 card->membase + TSQH);
1912}
1913
1914static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1915{
1916 struct atm_vcc *vcc;
1917 struct sk_buff *skb;
1918 int i;
1919 unsigned long flags;
1920
1921 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1922 card->index, scq, pos);
1923 if (pos >= scq->num_entries) {
1924 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1925 return;
1926 }
1927
1928 spin_lock_irqsave(&scq->lock, flags);
1929 i = (int)(scq->tail - scq->base);
1930 if (++i == scq->num_entries)
1931 i = 0;
1932 while (i != pos) {
1933 skb = scq->skb[i];
1934 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1935 card->index, skb, i);
1936 if (skb != NULL) {
1937 dma_unmap_single(&card->pcidev->dev,
1938 NS_PRV_DMA(skb),
1939 skb->len,
1940 DMA_TO_DEVICE);
1941 vcc = ATM_SKB(skb)->vcc;
1942 if (vcc && vcc->pop != NULL) {
1943 vcc->pop(vcc, skb);
1944 } else {
1945 dev_kfree_skb_irq(skb);
1946 }
1947 scq->skb[i] = NULL;
1948 }
1949 if (++i == scq->num_entries)
1950 i = 0;
1951 }
1952 scq->tail = scq->base + pos;
1953 spin_unlock_irqrestore(&scq->lock, flags);
1954}
1955
1956static void process_rsq(ns_dev * card)
1957{
1958 ns_rsqe *previous;
1959
1960 if (!ns_rsqe_valid(card->rsq.next))
1961 return;
1962 do {
1963 dequeue_rx(card, card->rsq.next);
1964 ns_rsqe_init(card->rsq.next);
1965 previous = card->rsq.next;
1966 if (card->rsq.next == card->rsq.last)
1967 card->rsq.next = card->rsq.base;
1968 else
1969 card->rsq.next++;
1970 } while (ns_rsqe_valid(card->rsq.next));
1971 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1972}
1973
1974static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1975{
1976 u32 vpi, vci;
1977 vc_map *vc;
1978 struct sk_buff *iovb;
1979 struct iovec *iov;
1980 struct atm_vcc *vcc;
1981 struct sk_buff *skb;
1982 unsigned short aal5_len;
1983 int len;
1984 u32 stat;
1985 u32 id;
1986
1987 stat = readl(card->membase + STAT);
1988 card->sbfqc = ns_stat_sfbqc_get(stat);
1989 card->lbfqc = ns_stat_lfbqc_get(stat);
1990
1991 id = le32_to_cpu(rsqe->buffer_handle);
1992 skb = idr_remove(&card->idr, id);
1993 if (!skb) {
1994 RXPRINTK(KERN_ERR
1995 "nicstar%d: skb not found!\n", card->index);
1996 return;
1997 }
1998 dma_sync_single_for_cpu(&card->pcidev->dev,
1999 NS_PRV_DMA(skb),
2000 (NS_PRV_BUFTYPE(skb) == BUF_SM
2001 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2002 DMA_FROM_DEVICE);
2003 dma_unmap_single(&card->pcidev->dev,
2004 NS_PRV_DMA(skb),
2005 (NS_PRV_BUFTYPE(skb) == BUF_SM
2006 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2007 DMA_FROM_DEVICE);
2008 vpi = ns_rsqe_vpi(rsqe);
2009 vci = ns_rsqe_vci(rsqe);
2010 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2011 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2012 card->index, vpi, vci);
2013 recycle_rx_buf(card, skb);
2014 return;
2015 }
2016
2017 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2018 if (!vc->rx) {
2019 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2020 card->index, vpi, vci);
2021 recycle_rx_buf(card, skb);
2022 return;
2023 }
2024
2025 vcc = vc->rx_vcc;
2026
2027 if (vcc->qos.aal == ATM_AAL0) {
2028 struct sk_buff *sb;
2029 unsigned char *cell;
2030 int i;
2031
2032 cell = skb->data;
2033 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2034 sb = dev_alloc_skb(NS_SMSKBSIZE);
2035 if (!sb) {
2036 printk
2037 ("nicstar%d: Can't allocate buffers for aal0.\n",
2038 card->index);
2039 atomic_add(i, &vcc->stats->rx_drop);
2040 break;
2041 }
2042 if (!atm_charge(vcc, sb->truesize)) {
2043 RXPRINTK
2044 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2045 card->index);
2046 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2047 dev_kfree_skb_any(sb);
2048 break;
2049 }
2050 /* Rebuild the header */
2051 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2052 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2053 if (i == 1 && ns_rsqe_eopdu(rsqe))
2054 *((u32 *) sb->data) |= 0x00000002;
2055 skb_put(sb, NS_AAL0_HEADER);
2056 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2057 skb_put(sb, ATM_CELL_PAYLOAD);
2058 ATM_SKB(sb)->vcc = vcc;
2059 __net_timestamp(sb);
2060 vcc->push(vcc, sb);
2061 atomic_inc(&vcc->stats->rx);
2062 cell += ATM_CELL_PAYLOAD;
2063 }
2064
2065 recycle_rx_buf(card, skb);
2066 return;
2067 }
2068
2069 /* To reach this point, the AAL layer can only be AAL5 */
2070
2071 if ((iovb = vc->rx_iov) == NULL) {
2072 iovb = skb_dequeue(&(card->iovpool.queue));
2073 if (iovb == NULL) { /* No buffers in the queue */
2074 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2075 if (iovb == NULL) {
2076 printk("nicstar%d: Out of iovec buffers.\n",
2077 card->index);
2078 atomic_inc(&vcc->stats->rx_drop);
2079 recycle_rx_buf(card, skb);
2080 return;
2081 }
2082 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2083 } else if (--card->iovpool.count < card->iovnr.min) {
2084 struct sk_buff *new_iovb;
2085 if ((new_iovb =
2086 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2087 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2088 skb_queue_tail(&card->iovpool.queue, new_iovb);
2089 card->iovpool.count++;
2090 }
2091 }
2092 vc->rx_iov = iovb;
2093 NS_PRV_IOVCNT(iovb) = 0;
2094 iovb->len = 0;
2095 iovb->data = iovb->head;
2096 skb_reset_tail_pointer(iovb);
2097 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2098 buffer is stored as iovec base, NOT a pointer to the
2099 small or large buffer itself. */
2100 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2101 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2102 atomic_inc(&vcc->stats->rx_err);
2103 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2104 NS_MAX_IOVECS);
2105 NS_PRV_IOVCNT(iovb) = 0;
2106 iovb->len = 0;
2107 iovb->data = iovb->head;
2108 skb_reset_tail_pointer(iovb);
2109 }
2110 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2111 iov->iov_base = (void *)skb;
2112 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2113 iovb->len += iov->iov_len;
2114
2115#ifdef EXTRA_DEBUG
2116 if (NS_PRV_IOVCNT(iovb) == 1) {
2117 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2118 printk
2119 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2120 card->index);
2121 which_list(card, skb);
2122 atomic_inc(&vcc->stats->rx_err);
2123 recycle_rx_buf(card, skb);
2124 vc->rx_iov = NULL;
2125 recycle_iov_buf(card, iovb);
2126 return;
2127 }
2128 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2129
2130 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2131 printk
2132 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2133 card->index);
2134 which_list(card, skb);
2135 atomic_inc(&vcc->stats->rx_err);
2136 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2137 NS_PRV_IOVCNT(iovb));
2138 vc->rx_iov = NULL;
2139 recycle_iov_buf(card, iovb);
2140 return;
2141 }
2142 }
2143#endif /* EXTRA_DEBUG */
2144
2145 if (ns_rsqe_eopdu(rsqe)) {
2146 /* This works correctly regardless of the endianness of the host */
2147 unsigned char *L1L2 = (unsigned char *)
2148 (skb->data + iov->iov_len - 6);
2149 aal5_len = L1L2[0] << 8 | L1L2[1];
2150 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2151 if (ns_rsqe_crcerr(rsqe) ||
2152 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2153 printk("nicstar%d: AAL5 CRC error", card->index);
2154 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2155 printk(" - PDU size mismatch.\n");
2156 else
2157 printk(".\n");
2158 atomic_inc(&vcc->stats->rx_err);
2159 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2160 NS_PRV_IOVCNT(iovb));
2161 vc->rx_iov = NULL;
2162 recycle_iov_buf(card, iovb);
2163 return;
2164 }
2165
2166 /* By this point we (hopefully) have a complete SDU without errors. */
2167
2168 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2169 /* skb points to a small buffer */
2170 if (!atm_charge(vcc, skb->truesize)) {
2171 push_rxbufs(card, skb);
2172 atomic_inc(&vcc->stats->rx_drop);
2173 } else {
2174 skb_put(skb, len);
2175 dequeue_sm_buf(card, skb);
2176 ATM_SKB(skb)->vcc = vcc;
2177 __net_timestamp(skb);
2178 vcc->push(vcc, skb);
2179 atomic_inc(&vcc->stats->rx);
2180 }
2181 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2182 struct sk_buff *sb;
2183
2184 sb = (struct sk_buff *)(iov - 1)->iov_base;
2185 /* skb points to a large buffer */
2186
2187 if (len <= NS_SMBUFSIZE) {
2188 if (!atm_charge(vcc, sb->truesize)) {
2189 push_rxbufs(card, sb);
2190 atomic_inc(&vcc->stats->rx_drop);
2191 } else {
2192 skb_put(sb, len);
2193 dequeue_sm_buf(card, sb);
2194 ATM_SKB(sb)->vcc = vcc;
2195 __net_timestamp(sb);
2196 vcc->push(vcc, sb);
2197 atomic_inc(&vcc->stats->rx);
2198 }
2199
2200 push_rxbufs(card, skb);
2201
2202 } else { /* len > NS_SMBUFSIZE, the usual case */
2203
2204 if (!atm_charge(vcc, skb->truesize)) {
2205 push_rxbufs(card, skb);
2206 atomic_inc(&vcc->stats->rx_drop);
2207 } else {
2208 dequeue_lg_buf(card, skb);
2209 skb_push(skb, NS_SMBUFSIZE);
2210 skb_copy_from_linear_data(sb, skb->data,
2211 NS_SMBUFSIZE);
2212 skb_put(skb, len - NS_SMBUFSIZE);
2213 ATM_SKB(skb)->vcc = vcc;
2214 __net_timestamp(skb);
2215 vcc->push(vcc, skb);
2216 atomic_inc(&vcc->stats->rx);
2217 }
2218
2219 push_rxbufs(card, sb);
2220
2221 }
2222
2223 } else { /* Must push a huge buffer */
2224
2225 struct sk_buff *hb, *sb, *lb;
2226 int remaining, tocopy;
2227 int j;
2228
2229 hb = skb_dequeue(&(card->hbpool.queue));
2230 if (hb == NULL) { /* No buffers in the queue */
2231
2232 hb = dev_alloc_skb(NS_HBUFSIZE);
2233 if (hb == NULL) {
2234 printk
2235 ("nicstar%d: Out of huge buffers.\n",
2236 card->index);
2237 atomic_inc(&vcc->stats->rx_drop);
2238 recycle_iovec_rx_bufs(card,
2239 (struct iovec *)
2240 iovb->data,
2241 NS_PRV_IOVCNT(iovb));
2242 vc->rx_iov = NULL;
2243 recycle_iov_buf(card, iovb);
2244 return;
2245 } else if (card->hbpool.count < card->hbnr.min) {
2246 struct sk_buff *new_hb;
2247 if ((new_hb =
2248 dev_alloc_skb(NS_HBUFSIZE)) !=
2249 NULL) {
2250 skb_queue_tail(&card->hbpool.
2251 queue, new_hb);
2252 card->hbpool.count++;
2253 }
2254 }
2255 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2256 } else if (--card->hbpool.count < card->hbnr.min) {
2257 struct sk_buff *new_hb;
2258 if ((new_hb =
2259 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2260 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2261 skb_queue_tail(&card->hbpool.queue,
2262 new_hb);
2263 card->hbpool.count++;
2264 }
2265 if (card->hbpool.count < card->hbnr.min) {
2266 if ((new_hb =
2267 dev_alloc_skb(NS_HBUFSIZE)) !=
2268 NULL) {
2269 NS_PRV_BUFTYPE(new_hb) =
2270 BUF_NONE;
2271 skb_queue_tail(&card->hbpool.
2272 queue, new_hb);
2273 card->hbpool.count++;
2274 }
2275 }
2276 }
2277
2278 iov = (struct iovec *)iovb->data;
2279
2280 if (!atm_charge(vcc, hb->truesize)) {
2281 recycle_iovec_rx_bufs(card, iov,
2282 NS_PRV_IOVCNT(iovb));
2283 if (card->hbpool.count < card->hbnr.max) {
2284 skb_queue_tail(&card->hbpool.queue, hb);
2285 card->hbpool.count++;
2286 } else
2287 dev_kfree_skb_any(hb);
2288 atomic_inc(&vcc->stats->rx_drop);
2289 } else {
2290 /* Copy the small buffer to the huge buffer */
2291 sb = (struct sk_buff *)iov->iov_base;
2292 skb_copy_from_linear_data(sb, hb->data,
2293 iov->iov_len);
2294 skb_put(hb, iov->iov_len);
2295 remaining = len - iov->iov_len;
2296 iov++;
2297 /* Free the small buffer */
2298 push_rxbufs(card, sb);
2299
2300 /* Copy all large buffers to the huge buffer and free them */
2301 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2302 lb = (struct sk_buff *)iov->iov_base;
2303 tocopy =
2304 min_t(int, remaining, iov->iov_len);
2305 skb_copy_from_linear_data(lb,
2306 skb_tail_pointer
2307 (hb), tocopy);
2308 skb_put(hb, tocopy);
2309 iov++;
2310 remaining -= tocopy;
2311 push_rxbufs(card, lb);
2312 }
2313#ifdef EXTRA_DEBUG
2314 if (remaining != 0 || hb->len != len)
2315 printk
2316 ("nicstar%d: Huge buffer len mismatch.\n",
2317 card->index);
2318#endif /* EXTRA_DEBUG */
2319 ATM_SKB(hb)->vcc = vcc;
2320 __net_timestamp(hb);
2321 vcc->push(vcc, hb);
2322 atomic_inc(&vcc->stats->rx);
2323 }
2324 }
2325
2326 vc->rx_iov = NULL;
2327 recycle_iov_buf(card, iovb);
2328 }
2329
2330}
2331
2332static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2333{
2334 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2335 printk("nicstar%d: What kind of rx buffer is this?\n",
2336 card->index);
2337 dev_kfree_skb_any(skb);
2338 } else
2339 push_rxbufs(card, skb);
2340}
2341
2342static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2343{
2344 while (count-- > 0)
2345 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2346}
2347
2348static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2349{
2350 if (card->iovpool.count < card->iovnr.max) {
2351 skb_queue_tail(&card->iovpool.queue, iovb);
2352 card->iovpool.count++;
2353 } else
2354 dev_kfree_skb_any(iovb);
2355}
2356
2357static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2358{
2359 skb_unlink(sb, &card->sbpool.queue);
2360 if (card->sbfqc < card->sbnr.init) {
2361 struct sk_buff *new_sb;
2362 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2363 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2364 skb_queue_tail(&card->sbpool.queue, new_sb);
2365 skb_reserve(new_sb, NS_AAL0_HEADER);
2366 push_rxbufs(card, new_sb);
2367 }
2368 }
2369 if (card->sbfqc < card->sbnr.init)
2370 {
2371 struct sk_buff *new_sb;
2372 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2373 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2374 skb_queue_tail(&card->sbpool.queue, new_sb);
2375 skb_reserve(new_sb, NS_AAL0_HEADER);
2376 push_rxbufs(card, new_sb);
2377 }
2378 }
2379}
2380
2381static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2382{
2383 skb_unlink(lb, &card->lbpool.queue);
2384 if (card->lbfqc < card->lbnr.init) {
2385 struct sk_buff *new_lb;
2386 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2387 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2388 skb_queue_tail(&card->lbpool.queue, new_lb);
2389 skb_reserve(new_lb, NS_SMBUFSIZE);
2390 push_rxbufs(card, new_lb);
2391 }
2392 }
2393 if (card->lbfqc < card->lbnr.init)
2394 {
2395 struct sk_buff *new_lb;
2396 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2397 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2398 skb_queue_tail(&card->lbpool.queue, new_lb);
2399 skb_reserve(new_lb, NS_SMBUFSIZE);
2400 push_rxbufs(card, new_lb);
2401 }
2402 }
2403}
2404
2405static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2406{
2407 u32 stat;
2408 ns_dev *card;
2409 int left;
2410
2411 left = (int)*pos;
2412 card = (ns_dev *) dev->dev_data;
2413 stat = readl(card->membase + STAT);
2414 if (!left--)
2415 return sprintf(page, "Pool count min init max \n");
2416 if (!left--)
2417 return sprintf(page, "Small %5d %5d %5d %5d \n",
2418 ns_stat_sfbqc_get(stat), card->sbnr.min,
2419 card->sbnr.init, card->sbnr.max);
2420 if (!left--)
2421 return sprintf(page, "Large %5d %5d %5d %5d \n",
2422 ns_stat_lfbqc_get(stat), card->lbnr.min,
2423 card->lbnr.init, card->lbnr.max);
2424 if (!left--)
2425 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2426 card->hbpool.count, card->hbnr.min,
2427 card->hbnr.init, card->hbnr.max);
2428 if (!left--)
2429 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2430 card->iovpool.count, card->iovnr.min,
2431 card->iovnr.init, card->iovnr.max);
2432 if (!left--) {
2433 int retval;
2434 retval =
2435 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2436 card->intcnt = 0;
2437 return retval;
2438 }
2439#if 0
2440 /* Dump 25.6 Mbps PHY registers */
2441 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2442 here just in case it's needed for debugging. */
2443 if (card->max_pcr == ATM_25_PCR && !left--) {
2444 u32 phy_regs[4];
2445 u32 i;
2446
2447 for (i = 0; i < 4; i++) {
2448 while (CMD_BUSY(card)) ;
2449 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2450 card->membase + CMD);
2451 while (CMD_BUSY(card)) ;
2452 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2453 }
2454
2455 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2456 phy_regs[0], phy_regs[1], phy_regs[2],
2457 phy_regs[3]);
2458 }
2459#endif /* 0 - Dump 25.6 Mbps PHY registers */
2460#if 0
2461 /* Dump TST */
2462 if (left-- < NS_TST_NUM_ENTRIES) {
2463 if (card->tste2vc[left + 1] == NULL)
2464 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2465 else
2466 return sprintf(page, "%5d - %d %d \n", left + 1,
2467 card->tste2vc[left + 1]->tx_vcc->vpi,
2468 card->tste2vc[left + 1]->tx_vcc->vci);
2469 }
2470#endif /* 0 */
2471 return 0;
2472}
2473
2474static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2475{
2476 ns_dev *card;
2477 pool_levels pl;
2478 long btype;
2479 unsigned long flags;
2480
2481 card = dev->dev_data;
2482 switch (cmd) {
2483 case NS_GETPSTAT:
2484 if (get_user
2485 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2486 return -EFAULT;
2487 switch (pl.buftype) {
2488 case NS_BUFTYPE_SMALL:
2489 pl.count =
2490 ns_stat_sfbqc_get(readl(card->membase + STAT));
2491 pl.level.min = card->sbnr.min;
2492 pl.level.init = card->sbnr.init;
2493 pl.level.max = card->sbnr.max;
2494 break;
2495
2496 case NS_BUFTYPE_LARGE:
2497 pl.count =
2498 ns_stat_lfbqc_get(readl(card->membase + STAT));
2499 pl.level.min = card->lbnr.min;
2500 pl.level.init = card->lbnr.init;
2501 pl.level.max = card->lbnr.max;
2502 break;
2503
2504 case NS_BUFTYPE_HUGE:
2505 pl.count = card->hbpool.count;
2506 pl.level.min = card->hbnr.min;
2507 pl.level.init = card->hbnr.init;
2508 pl.level.max = card->hbnr.max;
2509 break;
2510
2511 case NS_BUFTYPE_IOVEC:
2512 pl.count = card->iovpool.count;
2513 pl.level.min = card->iovnr.min;
2514 pl.level.init = card->iovnr.init;
2515 pl.level.max = card->iovnr.max;
2516 break;
2517
2518 default:
2519 return -ENOIOCTLCMD;
2520
2521 }
2522 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2523 return (sizeof(pl));
2524 else
2525 return -EFAULT;
2526
2527 case NS_SETBUFLEV:
2528 if (!capable(CAP_NET_ADMIN))
2529 return -EPERM;
2530 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2531 return -EFAULT;
2532 if (pl.level.min >= pl.level.init
2533 || pl.level.init >= pl.level.max)
2534 return -EINVAL;
2535 if (pl.level.min == 0)
2536 return -EINVAL;
2537 switch (pl.buftype) {
2538 case NS_BUFTYPE_SMALL:
2539 if (pl.level.max > TOP_SB)
2540 return -EINVAL;
2541 card->sbnr.min = pl.level.min;
2542 card->sbnr.init = pl.level.init;
2543 card->sbnr.max = pl.level.max;
2544 break;
2545
2546 case NS_BUFTYPE_LARGE:
2547 if (pl.level.max > TOP_LB)
2548 return -EINVAL;
2549 card->lbnr.min = pl.level.min;
2550 card->lbnr.init = pl.level.init;
2551 card->lbnr.max = pl.level.max;
2552 break;
2553
2554 case NS_BUFTYPE_HUGE:
2555 if (pl.level.max > TOP_HB)
2556 return -EINVAL;
2557 card->hbnr.min = pl.level.min;
2558 card->hbnr.init = pl.level.init;
2559 card->hbnr.max = pl.level.max;
2560 break;
2561
2562 case NS_BUFTYPE_IOVEC:
2563 if (pl.level.max > TOP_IOVB)
2564 return -EINVAL;
2565 card->iovnr.min = pl.level.min;
2566 card->iovnr.init = pl.level.init;
2567 card->iovnr.max = pl.level.max;
2568 break;
2569
2570 default:
2571 return -EINVAL;
2572
2573 }
2574 return 0;
2575
2576 case NS_ADJBUFLEV:
2577 if (!capable(CAP_NET_ADMIN))
2578 return -EPERM;
2579 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2580 switch (btype) {
2581 case NS_BUFTYPE_SMALL:
2582 while (card->sbfqc < card->sbnr.init) {
2583 struct sk_buff *sb;
2584
2585 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2586 if (sb == NULL)
2587 return -ENOMEM;
2588 NS_PRV_BUFTYPE(sb) = BUF_SM;
2589 skb_queue_tail(&card->sbpool.queue, sb);
2590 skb_reserve(sb, NS_AAL0_HEADER);
2591 push_rxbufs(card, sb);
2592 }
2593 break;
2594
2595 case NS_BUFTYPE_LARGE:
2596 while (card->lbfqc < card->lbnr.init) {
2597 struct sk_buff *lb;
2598
2599 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2600 if (lb == NULL)
2601 return -ENOMEM;
2602 NS_PRV_BUFTYPE(lb) = BUF_LG;
2603 skb_queue_tail(&card->lbpool.queue, lb);
2604 skb_reserve(lb, NS_SMBUFSIZE);
2605 push_rxbufs(card, lb);
2606 }
2607 break;
2608
2609 case NS_BUFTYPE_HUGE:
2610 while (card->hbpool.count > card->hbnr.init) {
2611 struct sk_buff *hb;
2612
2613 spin_lock_irqsave(&card->int_lock, flags);
2614 hb = skb_dequeue(&card->hbpool.queue);
2615 card->hbpool.count--;
2616 spin_unlock_irqrestore(&card->int_lock, flags);
2617 if (hb == NULL)
2618 printk
2619 ("nicstar%d: huge buffer count inconsistent.\n",
2620 card->index);
2621 else
2622 dev_kfree_skb_any(hb);
2623
2624 }
2625 while (card->hbpool.count < card->hbnr.init) {
2626 struct sk_buff *hb;
2627
2628 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2629 if (hb == NULL)
2630 return -ENOMEM;
2631 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2632 spin_lock_irqsave(&card->int_lock, flags);
2633 skb_queue_tail(&card->hbpool.queue, hb);
2634 card->hbpool.count++;
2635 spin_unlock_irqrestore(&card->int_lock, flags);
2636 }
2637 break;
2638
2639 case NS_BUFTYPE_IOVEC:
2640 while (card->iovpool.count > card->iovnr.init) {
2641 struct sk_buff *iovb;
2642
2643 spin_lock_irqsave(&card->int_lock, flags);
2644 iovb = skb_dequeue(&card->iovpool.queue);
2645 card->iovpool.count--;
2646 spin_unlock_irqrestore(&card->int_lock, flags);
2647 if (iovb == NULL)
2648 printk
2649 ("nicstar%d: iovec buffer count inconsistent.\n",
2650 card->index);
2651 else
2652 dev_kfree_skb_any(iovb);
2653
2654 }
2655 while (card->iovpool.count < card->iovnr.init) {
2656 struct sk_buff *iovb;
2657
2658 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2659 if (iovb == NULL)
2660 return -ENOMEM;
2661 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2662 spin_lock_irqsave(&card->int_lock, flags);
2663 skb_queue_tail(&card->iovpool.queue, iovb);
2664 card->iovpool.count++;
2665 spin_unlock_irqrestore(&card->int_lock, flags);
2666 }
2667 break;
2668
2669 default:
2670 return -EINVAL;
2671
2672 }
2673 return 0;
2674
2675 default:
2676 if (dev->phy && dev->phy->ioctl) {
2677 return dev->phy->ioctl(dev, cmd, arg);
2678 } else {
2679 printk("nicstar%d: %s == NULL \n", card->index,
2680 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2681 return -ENOIOCTLCMD;
2682 }
2683 }
2684}
2685
2686#ifdef EXTRA_DEBUG
2687static void which_list(ns_dev * card, struct sk_buff *skb)
2688{
2689 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2690}
2691#endif /* EXTRA_DEBUG */
2692
2693static void ns_poll(struct timer_list *unused)
2694{
2695 int i;
2696 ns_dev *card;
2697 unsigned long flags;
2698 u32 stat_r, stat_w;
2699
2700 PRINTK("nicstar: Entering ns_poll().\n");
2701 for (i = 0; i < num_cards; i++) {
2702 card = cards[i];
2703 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2704 /* Probably it isn't worth spinning */
2705 continue;
2706 }
2707
2708 stat_w = 0;
2709 stat_r = readl(card->membase + STAT);
2710 if (stat_r & NS_STAT_TSIF)
2711 stat_w |= NS_STAT_TSIF;
2712 if (stat_r & NS_STAT_EOPDU)
2713 stat_w |= NS_STAT_EOPDU;
2714
2715 process_tsq(card);
2716 process_rsq(card);
2717
2718 writel(stat_w, card->membase + STAT);
2719 spin_unlock_irqrestore(&card->int_lock, flags);
2720 }
2721 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2722 PRINTK("nicstar: Leaving ns_poll().\n");
2723}
2724
2725static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2726 unsigned long addr)
2727{
2728 ns_dev *card;
2729 unsigned long flags;
2730
2731 card = dev->dev_data;
2732 spin_lock_irqsave(&card->res_lock, flags);
2733 while (CMD_BUSY(card)) ;
2734 writel((u32) value, card->membase + DR0);
2735 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2736 card->membase + CMD);
2737 spin_unlock_irqrestore(&card->res_lock, flags);
2738}
2739
2740static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2741{
2742 ns_dev *card;
2743 unsigned long flags;
2744 u32 data;
2745
2746 card = dev->dev_data;
2747 spin_lock_irqsave(&card->res_lock, flags);
2748 while (CMD_BUSY(card)) ;
2749 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2750 card->membase + CMD);
2751 while (CMD_BUSY(card)) ;
2752 data = readl(card->membase + DR0) & 0x000000FF;
2753 spin_unlock_irqrestore(&card->res_lock, flags);
2754 return (unsigned char)data;
2755}
2756
2757module_init(nicstar_init);
2758module_exit(nicstar_cleanup);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21/*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34/* Header files */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/skbuff.h>
39#include <linux/atmdev.h>
40#include <linux/atm.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/types.h>
44#include <linux/string.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/timer.h>
49#include <linux/interrupt.h>
50#include <linux/bitops.h>
51#include <linux/slab.h>
52#include <linux/idr.h>
53#include <asm/io.h>
54#include <linux/uaccess.h>
55#include <linux/atomic.h>
56#include <linux/etherdevice.h>
57#include "nicstar.h"
58#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59#include "suni.h"
60#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62#include "idt77105.h"
63#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65/* Additional code */
66
67#include "nicstarmac.c"
68
69/* Configurable parameters */
70
71#undef PHY_LOOPBACK
72#undef TX_DEBUG
73#undef RX_DEBUG
74#undef GENERAL_DEBUG
75#undef EXTRA_DEBUG
76
77/* Do not touch these */
78
79#ifdef TX_DEBUG
80#define TXPRINTK(args...) printk(args)
81#else
82#define TXPRINTK(args...)
83#endif /* TX_DEBUG */
84
85#ifdef RX_DEBUG
86#define RXPRINTK(args...) printk(args)
87#else
88#define RXPRINTK(args...)
89#endif /* RX_DEBUG */
90
91#ifdef GENERAL_DEBUG
92#define PRINTK(args...) printk(args)
93#else
94#define PRINTK(args...)
95#endif /* GENERAL_DEBUG */
96
97#ifdef EXTRA_DEBUG
98#define XPRINTK(args...) printk(args)
99#else
100#define XPRINTK(args...)
101#endif /* EXTRA_DEBUG */
102
103/* Macros */
104
105#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107#define NS_DELAY mdelay(1)
108
109#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111#ifndef ATM_SKB
112#define ATM_SKB(s) (&(s)->atm)
113#endif
114
115#define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118/* Function declarations */
119
120static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123static int ns_init_card(int i, struct pci_dev *pcidev);
124static void ns_init_card_error(ns_dev * card, int error);
125static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127static void push_rxbufs(ns_dev *, struct sk_buff *);
128static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129static int ns_open(struct atm_vcc *vcc);
130static void ns_close(struct atm_vcc *vcc);
131static void fill_tst(ns_dev * card, int n, vc_map * vc);
132static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
134 struct sk_buff *skb);
135static void process_tsq(ns_dev * card);
136static void drain_scq(ns_dev * card, scq_info * scq, int pos);
137static void process_rsq(ns_dev * card);
138static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
139static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
140static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
141static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
142static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
143static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
144static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
145static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
146#ifdef EXTRA_DEBUG
147static void which_list(ns_dev * card, struct sk_buff *skb);
148#endif
149static void ns_poll(struct timer_list *unused);
150static void ns_phy_put(struct atm_dev *dev, unsigned char value,
151 unsigned long addr);
152static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
153
154/* Global variables */
155
156static struct ns_dev *cards[NS_MAX_CARDS];
157static unsigned num_cards;
158static const struct atmdev_ops atm_ops = {
159 .open = ns_open,
160 .close = ns_close,
161 .ioctl = ns_ioctl,
162 .send = ns_send,
163 .phy_put = ns_phy_put,
164 .phy_get = ns_phy_get,
165 .proc_read = ns_proc_read,
166 .owner = THIS_MODULE,
167};
168
169static struct timer_list ns_timer;
170static char *mac[NS_MAX_CARDS];
171module_param_array(mac, charp, NULL, 0);
172MODULE_LICENSE("GPL");
173
174/* Functions */
175
176static int nicstar_init_one(struct pci_dev *pcidev,
177 const struct pci_device_id *ent)
178{
179 static int index = -1;
180 unsigned int error;
181
182 index++;
183 cards[index] = NULL;
184
185 error = ns_init_card(index, pcidev);
186 if (error) {
187 cards[index--] = NULL; /* don't increment index */
188 goto err_out;
189 }
190
191 return 0;
192err_out:
193 return -ENODEV;
194}
195
196static void nicstar_remove_one(struct pci_dev *pcidev)
197{
198 int i, j;
199 ns_dev *card = pci_get_drvdata(pcidev);
200 struct sk_buff *hb;
201 struct sk_buff *iovb;
202 struct sk_buff *lb;
203 struct sk_buff *sb;
204
205 i = card->index;
206
207 if (cards[i] == NULL)
208 return;
209
210 if (card->atmdev->phy && card->atmdev->phy->stop)
211 card->atmdev->phy->stop(card->atmdev);
212
213 /* Stop everything */
214 writel(0x00000000, card->membase + CFG);
215
216 /* De-register device */
217 atm_dev_deregister(card->atmdev);
218
219 /* Disable PCI device */
220 pci_disable_device(pcidev);
221
222 /* Free up resources */
223 j = 0;
224 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
225 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
226 dev_kfree_skb_any(hb);
227 j++;
228 }
229 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
230 j = 0;
231 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
232 card->iovpool.count);
233 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
234 dev_kfree_skb_any(iovb);
235 j++;
236 }
237 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
238 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
239 dev_kfree_skb_any(lb);
240 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
241 dev_kfree_skb_any(sb);
242 free_scq(card, card->scq0, NULL);
243 for (j = 0; j < NS_FRSCD_NUM; j++) {
244 if (card->scd2vc[j] != NULL)
245 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
246 }
247 idr_destroy(&card->idr);
248 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
249 card->rsq.org, card->rsq.dma);
250 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
251 card->tsq.org, card->tsq.dma);
252 free_irq(card->pcidev->irq, card);
253 iounmap(card->membase);
254 kfree(card);
255}
256
257static const struct pci_device_id nicstar_pci_tbl[] = {
258 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
259 {0,} /* terminate list */
260};
261
262MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
263
264static struct pci_driver nicstar_driver = {
265 .name = "nicstar",
266 .id_table = nicstar_pci_tbl,
267 .probe = nicstar_init_one,
268 .remove = nicstar_remove_one,
269};
270
271static int __init nicstar_init(void)
272{
273 unsigned error = 0; /* Initialized to remove compile warning */
274
275 XPRINTK("nicstar: nicstar_init() called.\n");
276
277 error = pci_register_driver(&nicstar_driver);
278
279 TXPRINTK("nicstar: TX debug enabled.\n");
280 RXPRINTK("nicstar: RX debug enabled.\n");
281 PRINTK("nicstar: General debug enabled.\n");
282#ifdef PHY_LOOPBACK
283 printk("nicstar: using PHY loopback.\n");
284#endif /* PHY_LOOPBACK */
285 XPRINTK("nicstar: nicstar_init() returned.\n");
286
287 if (!error) {
288 timer_setup(&ns_timer, ns_poll, 0);
289 ns_timer.expires = jiffies + NS_POLL_PERIOD;
290 add_timer(&ns_timer);
291 }
292
293 return error;
294}
295
296static void __exit nicstar_cleanup(void)
297{
298 XPRINTK("nicstar: nicstar_cleanup() called.\n");
299
300 del_timer(&ns_timer);
301
302 pci_unregister_driver(&nicstar_driver);
303
304 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
305}
306
307static u32 ns_read_sram(ns_dev * card, u32 sram_address)
308{
309 unsigned long flags;
310 u32 data;
311 sram_address <<= 2;
312 sram_address &= 0x0007FFFC; /* address must be dword aligned */
313 sram_address |= 0x50000000; /* SRAM read command */
314 spin_lock_irqsave(&card->res_lock, flags);
315 while (CMD_BUSY(card)) ;
316 writel(sram_address, card->membase + CMD);
317 while (CMD_BUSY(card)) ;
318 data = readl(card->membase + DR0);
319 spin_unlock_irqrestore(&card->res_lock, flags);
320 return data;
321}
322
323static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
324 int count)
325{
326 unsigned long flags;
327 int i, c;
328 count--; /* count range now is 0..3 instead of 1..4 */
329 c = count;
330 c <<= 2; /* to use increments of 4 */
331 spin_lock_irqsave(&card->res_lock, flags);
332 while (CMD_BUSY(card)) ;
333 for (i = 0; i <= c; i += 4)
334 writel(*(value++), card->membase + i);
335 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
336 so card->membase + DR0 == card->membase */
337 sram_address <<= 2;
338 sram_address &= 0x0007FFFC;
339 sram_address |= (0x40000000 | count);
340 writel(sram_address, card->membase + CMD);
341 spin_unlock_irqrestore(&card->res_lock, flags);
342}
343
344static int ns_init_card(int i, struct pci_dev *pcidev)
345{
346 int j;
347 struct ns_dev *card = NULL;
348 unsigned char pci_latency;
349 unsigned error;
350 u32 data;
351 u32 u32d[4];
352 u32 ns_cfg_rctsize;
353 int bcount;
354 unsigned long membase;
355
356 error = 0;
357
358 if (pci_enable_device(pcidev)) {
359 printk("nicstar%d: can't enable PCI device\n", i);
360 error = 2;
361 ns_init_card_error(card, error);
362 return error;
363 }
364 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
365 printk(KERN_WARNING
366 "nicstar%d: No suitable DMA available.\n", i);
367 error = 2;
368 ns_init_card_error(card, error);
369 return error;
370 }
371
372 card = kmalloc(sizeof(*card), GFP_KERNEL);
373 if (!card) {
374 printk
375 ("nicstar%d: can't allocate memory for device structure.\n",
376 i);
377 error = 2;
378 ns_init_card_error(card, error);
379 return error;
380 }
381 cards[i] = card;
382 spin_lock_init(&card->int_lock);
383 spin_lock_init(&card->res_lock);
384
385 pci_set_drvdata(pcidev, card);
386
387 card->index = i;
388 card->atmdev = NULL;
389 card->pcidev = pcidev;
390 membase = pci_resource_start(pcidev, 1);
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
392 if (!card->membase) {
393 printk("nicstar%d: can't ioremap() membase.\n", i);
394 error = 3;
395 ns_init_card_error(card, error);
396 return error;
397 }
398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
399
400 pci_set_master(pcidev);
401
402 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
403 printk("nicstar%d: can't read PCI latency timer.\n", i);
404 error = 6;
405 ns_init_card_error(card, error);
406 return error;
407 }
408#ifdef NS_PCI_LATENCY
409 if (pci_latency < NS_PCI_LATENCY) {
410 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
411 NS_PCI_LATENCY);
412 for (j = 1; j < 4; j++) {
413 if (pci_write_config_byte
414 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
415 break;
416 }
417 if (j == 4) {
418 printk
419 ("nicstar%d: can't set PCI latency timer to %d.\n",
420 i, NS_PCI_LATENCY);
421 error = 7;
422 ns_init_card_error(card, error);
423 return error;
424 }
425 }
426#endif /* NS_PCI_LATENCY */
427
428 /* Clear timer overflow */
429 data = readl(card->membase + STAT);
430 if (data & NS_STAT_TMROF)
431 writel(NS_STAT_TMROF, card->membase + STAT);
432
433 /* Software reset */
434 writel(NS_CFG_SWRST, card->membase + CFG);
435 NS_DELAY;
436 writel(0x00000000, card->membase + CFG);
437
438 /* PHY reset */
439 writel(0x00000008, card->membase + GP);
440 NS_DELAY;
441 writel(0x00000001, card->membase + GP);
442 NS_DELAY;
443 while (CMD_BUSY(card)) ;
444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
445 NS_DELAY;
446
447 /* Detect PHY type */
448 while (CMD_BUSY(card)) ;
449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
450 while (CMD_BUSY(card)) ;
451 data = readl(card->membase + DR0);
452 switch (data) {
453 case 0x00000009:
454 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
455 card->max_pcr = ATM_25_PCR;
456 while (CMD_BUSY(card)) ;
457 writel(0x00000008, card->membase + DR0);
458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
459 /* Clear an eventual pending interrupt */
460 writel(NS_STAT_SFBQF, card->membase + STAT);
461#ifdef PHY_LOOPBACK
462 while (CMD_BUSY(card)) ;
463 writel(0x00000022, card->membase + DR0);
464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
465#endif /* PHY_LOOPBACK */
466 break;
467 case 0x00000030:
468 case 0x00000031:
469 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
470 card->max_pcr = ATM_OC3_PCR;
471#ifdef PHY_LOOPBACK
472 while (CMD_BUSY(card)) ;
473 writel(0x00000002, card->membase + DR0);
474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
475#endif /* PHY_LOOPBACK */
476 break;
477 default:
478 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
479 error = 8;
480 ns_init_card_error(card, error);
481 return error;
482 }
483 writel(0x00000000, card->membase + GP);
484
485 /* Determine SRAM size */
486 data = 0x76543210;
487 ns_write_sram(card, 0x1C003, &data, 1);
488 data = 0x89ABCDEF;
489 ns_write_sram(card, 0x14003, &data, 1);
490 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
491 ns_read_sram(card, 0x1C003) == 0x76543210)
492 card->sram_size = 128;
493 else
494 card->sram_size = 32;
495 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
496
497 card->rct_size = NS_MAX_RCTSIZE;
498
499#if (NS_MAX_RCTSIZE == 4096)
500 if (card->sram_size == 128)
501 printk
502 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
503 i);
504#elif (NS_MAX_RCTSIZE == 16384)
505 if (card->sram_size == 32) {
506 printk
507 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
508 i);
509 card->rct_size = 4096;
510 }
511#else
512#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
513#endif
514
515 card->vpibits = NS_VPIBITS;
516 if (card->rct_size == 4096)
517 card->vcibits = 12 - NS_VPIBITS;
518 else /* card->rct_size == 16384 */
519 card->vcibits = 14 - NS_VPIBITS;
520
521 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
522 if (mac[i] == NULL)
523 nicstar_init_eprom(card->membase);
524
525 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
526 writel(0x00000000, card->membase + VPM);
527
528 /* Initialize TSQ */
529 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
530 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
531 &card->tsq.dma, GFP_KERNEL);
532 if (card->tsq.org == NULL) {
533 printk("nicstar%d: can't allocate TSQ.\n", i);
534 error = 10;
535 ns_init_card_error(card, error);
536 return error;
537 }
538 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
539 card->tsq.next = card->tsq.base;
540 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
541 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
542 ns_tsi_init(card->tsq.base + j);
543 writel(0x00000000, card->membase + TSQH);
544 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
545 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
546
547 /* Initialize RSQ */
548 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
549 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
550 &card->rsq.dma, GFP_KERNEL);
551 if (card->rsq.org == NULL) {
552 printk("nicstar%d: can't allocate RSQ.\n", i);
553 error = 11;
554 ns_init_card_error(card, error);
555 return error;
556 }
557 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
558 card->rsq.next = card->rsq.base;
559 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
560 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
561 ns_rsqe_init(card->rsq.base + j);
562 writel(0x00000000, card->membase + RSQH);
563 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
564 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
565
566 /* Initialize SCQ0, the only VBR SCQ used */
567 card->scq1 = NULL;
568 card->scq2 = NULL;
569 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
570 if (card->scq0 == NULL) {
571 printk("nicstar%d: can't get SCQ0.\n", i);
572 error = 12;
573 ns_init_card_error(card, error);
574 return error;
575 }
576 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
577 u32d[1] = (u32) 0x00000000;
578 u32d[2] = (u32) 0xffffffff;
579 u32d[3] = (u32) 0x00000000;
580 ns_write_sram(card, NS_VRSCD0, u32d, 4);
581 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
582 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
583 card->scq0->scd = NS_VRSCD0;
584 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
585
586 /* Initialize TSTs */
587 card->tst_addr = NS_TST0;
588 card->tst_free_entries = NS_TST_NUM_ENTRIES;
589 data = NS_TST_OPCODE_VARIABLE;
590 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
591 ns_write_sram(card, NS_TST0 + j, &data, 1);
592 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
593 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
594 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
595 ns_write_sram(card, NS_TST1 + j, &data, 1);
596 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
597 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
598 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
599 card->tste2vc[j] = NULL;
600 writel(NS_TST0 << 2, card->membase + TSTB);
601
602 /* Initialize RCT. AAL type is set on opening the VC. */
603#ifdef RCQ_SUPPORT
604 u32d[0] = NS_RCTE_RAWCELLINTEN;
605#else
606 u32d[0] = 0x00000000;
607#endif /* RCQ_SUPPORT */
608 u32d[1] = 0x00000000;
609 u32d[2] = 0x00000000;
610 u32d[3] = 0xFFFFFFFF;
611 for (j = 0; j < card->rct_size; j++)
612 ns_write_sram(card, j * 4, u32d, 4);
613
614 memset(card->vcmap, 0, sizeof(card->vcmap));
615
616 for (j = 0; j < NS_FRSCD_NUM; j++)
617 card->scd2vc[j] = NULL;
618
619 /* Initialize buffer levels */
620 card->sbnr.min = MIN_SB;
621 card->sbnr.init = NUM_SB;
622 card->sbnr.max = MAX_SB;
623 card->lbnr.min = MIN_LB;
624 card->lbnr.init = NUM_LB;
625 card->lbnr.max = MAX_LB;
626 card->iovnr.min = MIN_IOVB;
627 card->iovnr.init = NUM_IOVB;
628 card->iovnr.max = MAX_IOVB;
629 card->hbnr.min = MIN_HB;
630 card->hbnr.init = NUM_HB;
631 card->hbnr.max = MAX_HB;
632
633 card->sm_handle = NULL;
634 card->sm_addr = 0x00000000;
635 card->lg_handle = NULL;
636 card->lg_addr = 0x00000000;
637
638 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
639
640 idr_init(&card->idr);
641
642 /* Pre-allocate some huge buffers */
643 skb_queue_head_init(&card->hbpool.queue);
644 card->hbpool.count = 0;
645 for (j = 0; j < NUM_HB; j++) {
646 struct sk_buff *hb;
647 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
648 if (hb == NULL) {
649 printk
650 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
651 i, j, NUM_HB);
652 error = 13;
653 ns_init_card_error(card, error);
654 return error;
655 }
656 NS_PRV_BUFTYPE(hb) = BUF_NONE;
657 skb_queue_tail(&card->hbpool.queue, hb);
658 card->hbpool.count++;
659 }
660
661 /* Allocate large buffers */
662 skb_queue_head_init(&card->lbpool.queue);
663 card->lbpool.count = 0; /* Not used */
664 for (j = 0; j < NUM_LB; j++) {
665 struct sk_buff *lb;
666 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
667 if (lb == NULL) {
668 printk
669 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
670 i, j, NUM_LB);
671 error = 14;
672 ns_init_card_error(card, error);
673 return error;
674 }
675 NS_PRV_BUFTYPE(lb) = BUF_LG;
676 skb_queue_tail(&card->lbpool.queue, lb);
677 skb_reserve(lb, NS_SMBUFSIZE);
678 push_rxbufs(card, lb);
679 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
680 if (j == 1) {
681 card->rcbuf = lb;
682 card->rawcell = (struct ns_rcqe *) lb->data;
683 card->rawch = NS_PRV_DMA(lb);
684 }
685 }
686 /* Test for strange behaviour which leads to crashes */
687 if ((bcount =
688 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
689 printk
690 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
691 i, j, bcount);
692 error = 14;
693 ns_init_card_error(card, error);
694 return error;
695 }
696
697 /* Allocate small buffers */
698 skb_queue_head_init(&card->sbpool.queue);
699 card->sbpool.count = 0; /* Not used */
700 for (j = 0; j < NUM_SB; j++) {
701 struct sk_buff *sb;
702 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
703 if (sb == NULL) {
704 printk
705 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
706 i, j, NUM_SB);
707 error = 15;
708 ns_init_card_error(card, error);
709 return error;
710 }
711 NS_PRV_BUFTYPE(sb) = BUF_SM;
712 skb_queue_tail(&card->sbpool.queue, sb);
713 skb_reserve(sb, NS_AAL0_HEADER);
714 push_rxbufs(card, sb);
715 }
716 /* Test for strange behaviour which leads to crashes */
717 if ((bcount =
718 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
719 printk
720 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
721 i, j, bcount);
722 error = 15;
723 ns_init_card_error(card, error);
724 return error;
725 }
726
727 /* Allocate iovec buffers */
728 skb_queue_head_init(&card->iovpool.queue);
729 card->iovpool.count = 0;
730 for (j = 0; j < NUM_IOVB; j++) {
731 struct sk_buff *iovb;
732 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
733 if (iovb == NULL) {
734 printk
735 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
736 i, j, NUM_IOVB);
737 error = 16;
738 ns_init_card_error(card, error);
739 return error;
740 }
741 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
742 skb_queue_tail(&card->iovpool.queue, iovb);
743 card->iovpool.count++;
744 }
745
746 /* Configure NICStAR */
747 if (card->rct_size == 4096)
748 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
749 else /* (card->rct_size == 16384) */
750 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
751
752 card->efbie = 1;
753
754 card->intcnt = 0;
755 if (request_irq
756 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
757 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
758 error = 9;
759 ns_init_card_error(card, error);
760 return error;
761 }
762
763 /* Register device */
764 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
765 -1, NULL);
766 if (card->atmdev == NULL) {
767 printk("nicstar%d: can't register device.\n", i);
768 error = 17;
769 ns_init_card_error(card, error);
770 return error;
771 }
772
773 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
775 card->atmdev->esi, 6);
776 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
777 nicstar_read_eprom(card->membase,
778 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
779 card->atmdev->esi, 6);
780 }
781 }
782
783 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
784
785 card->atmdev->dev_data = card;
786 card->atmdev->ci_range.vpi_bits = card->vpibits;
787 card->atmdev->ci_range.vci_bits = card->vcibits;
788 card->atmdev->link_rate = card->max_pcr;
789 card->atmdev->phy = NULL;
790
791#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
792 if (card->max_pcr == ATM_OC3_PCR)
793 suni_init(card->atmdev);
794#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
795
796#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
797 if (card->max_pcr == ATM_25_PCR)
798 idt77105_init(card->atmdev);
799#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
800
801 if (card->atmdev->phy && card->atmdev->phy->start)
802 card->atmdev->phy->start(card->atmdev);
803
804 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
805 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
806 NS_CFG_PHYIE, card->membase + CFG);
807
808 num_cards++;
809
810 return error;
811}
812
813static void ns_init_card_error(ns_dev *card, int error)
814{
815 if (error >= 17) {
816 writel(0x00000000, card->membase + CFG);
817 }
818 if (error >= 16) {
819 struct sk_buff *iovb;
820 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
821 dev_kfree_skb_any(iovb);
822 }
823 if (error >= 15) {
824 struct sk_buff *sb;
825 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
826 dev_kfree_skb_any(sb);
827 free_scq(card, card->scq0, NULL);
828 }
829 if (error >= 14) {
830 struct sk_buff *lb;
831 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
832 dev_kfree_skb_any(lb);
833 }
834 if (error >= 13) {
835 struct sk_buff *hb;
836 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
837 dev_kfree_skb_any(hb);
838 }
839 if (error >= 12) {
840 kfree(card->rsq.org);
841 }
842 if (error >= 11) {
843 kfree(card->tsq.org);
844 }
845 if (error >= 10) {
846 free_irq(card->pcidev->irq, card);
847 }
848 if (error >= 4) {
849 iounmap(card->membase);
850 }
851 if (error >= 3) {
852 pci_disable_device(card->pcidev);
853 kfree(card);
854 }
855}
856
857static scq_info *get_scq(ns_dev *card, int size, u32 scd)
858{
859 scq_info *scq;
860 int i;
861
862 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
863 return NULL;
864
865 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
866 if (!scq)
867 return NULL;
868 scq->org = dma_alloc_coherent(&card->pcidev->dev,
869 2 * size, &scq->dma, GFP_KERNEL);
870 if (!scq->org) {
871 kfree(scq);
872 return NULL;
873 }
874 scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
875 sizeof(*scq->skb),
876 GFP_KERNEL);
877 if (!scq->skb) {
878 dma_free_coherent(&card->pcidev->dev,
879 2 * size, scq->org, scq->dma);
880 kfree(scq);
881 return NULL;
882 }
883 scq->num_entries = size / NS_SCQE_SIZE;
884 scq->base = PTR_ALIGN(scq->org, size);
885 scq->next = scq->base;
886 scq->last = scq->base + (scq->num_entries - 1);
887 scq->tail = scq->last;
888 scq->scd = scd;
889 scq->num_entries = size / NS_SCQE_SIZE;
890 scq->tbd_count = 0;
891 init_waitqueue_head(&scq->scqfull_waitq);
892 scq->full = 0;
893 spin_lock_init(&scq->lock);
894
895 for (i = 0; i < scq->num_entries; i++)
896 scq->skb[i] = NULL;
897
898 return scq;
899}
900
901/* For variable rate SCQ vcc must be NULL */
902static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
903{
904 int i;
905
906 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
907 for (i = 0; i < scq->num_entries; i++) {
908 if (scq->skb[i] != NULL) {
909 vcc = ATM_SKB(scq->skb[i])->vcc;
910 if (vcc->pop != NULL)
911 vcc->pop(vcc, scq->skb[i]);
912 else
913 dev_kfree_skb_any(scq->skb[i]);
914 }
915 } else { /* vcc must be != NULL */
916
917 if (vcc == NULL) {
918 printk
919 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
920 for (i = 0; i < scq->num_entries; i++)
921 dev_kfree_skb_any(scq->skb[i]);
922 } else
923 for (i = 0; i < scq->num_entries; i++) {
924 if (scq->skb[i] != NULL) {
925 if (vcc->pop != NULL)
926 vcc->pop(vcc, scq->skb[i]);
927 else
928 dev_kfree_skb_any(scq->skb[i]);
929 }
930 }
931 }
932 kfree(scq->skb);
933 dma_free_coherent(&card->pcidev->dev,
934 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
935 VBR_SCQSIZE : CBR_SCQSIZE),
936 scq->org, scq->dma);
937 kfree(scq);
938}
939
940/* The handles passed must be pointers to the sk_buff containing the small
941 or large buffer(s) cast to u32. */
942static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
943{
944 struct sk_buff *handle1, *handle2;
945 int id1, id2;
946 u32 addr1, addr2;
947 u32 stat;
948 unsigned long flags;
949
950 /* *BARF* */
951 handle2 = NULL;
952 addr2 = 0;
953 handle1 = skb;
954 addr1 = dma_map_single(&card->pcidev->dev,
955 skb->data,
956 (NS_PRV_BUFTYPE(skb) == BUF_SM
957 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
958 DMA_TO_DEVICE);
959 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
960
961#ifdef GENERAL_DEBUG
962 if (!addr1)
963 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
964 card->index);
965#endif /* GENERAL_DEBUG */
966
967 stat = readl(card->membase + STAT);
968 card->sbfqc = ns_stat_sfbqc_get(stat);
969 card->lbfqc = ns_stat_lfbqc_get(stat);
970 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
971 if (!addr2) {
972 if (card->sm_addr) {
973 addr2 = card->sm_addr;
974 handle2 = card->sm_handle;
975 card->sm_addr = 0x00000000;
976 card->sm_handle = NULL;
977 } else { /* (!sm_addr) */
978
979 card->sm_addr = addr1;
980 card->sm_handle = handle1;
981 }
982 }
983 } else { /* buf_type == BUF_LG */
984
985 if (!addr2) {
986 if (card->lg_addr) {
987 addr2 = card->lg_addr;
988 handle2 = card->lg_handle;
989 card->lg_addr = 0x00000000;
990 card->lg_handle = NULL;
991 } else { /* (!lg_addr) */
992
993 card->lg_addr = addr1;
994 card->lg_handle = handle1;
995 }
996 }
997 }
998
999 if (addr2) {
1000 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1001 if (card->sbfqc >= card->sbnr.max) {
1002 skb_unlink(handle1, &card->sbpool.queue);
1003 dev_kfree_skb_any(handle1);
1004 skb_unlink(handle2, &card->sbpool.queue);
1005 dev_kfree_skb_any(handle2);
1006 return;
1007 } else
1008 card->sbfqc += 2;
1009 } else { /* (buf_type == BUF_LG) */
1010
1011 if (card->lbfqc >= card->lbnr.max) {
1012 skb_unlink(handle1, &card->lbpool.queue);
1013 dev_kfree_skb_any(handle1);
1014 skb_unlink(handle2, &card->lbpool.queue);
1015 dev_kfree_skb_any(handle2);
1016 return;
1017 } else
1018 card->lbfqc += 2;
1019 }
1020
1021 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1022 if (id1 < 0)
1023 goto out;
1024
1025 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1026 if (id2 < 0)
1027 goto out;
1028
1029 spin_lock_irqsave(&card->res_lock, flags);
1030 while (CMD_BUSY(card)) ;
1031 writel(addr2, card->membase + DR3);
1032 writel(id2, card->membase + DR2);
1033 writel(addr1, card->membase + DR1);
1034 writel(id1, card->membase + DR0);
1035 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1036 card->membase + CMD);
1037 spin_unlock_irqrestore(&card->res_lock, flags);
1038
1039 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1040 card->index,
1041 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1042 addr1, addr2);
1043 }
1044
1045 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1046 card->lbfqc >= card->lbnr.min) {
1047 card->efbie = 1;
1048 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1049 card->membase + CFG);
1050 }
1051
1052out:
1053 return;
1054}
1055
1056static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1057{
1058 u32 stat_r;
1059 ns_dev *card;
1060 struct atm_dev *dev;
1061 unsigned long flags;
1062
1063 card = (ns_dev *) dev_id;
1064 dev = card->atmdev;
1065 card->intcnt++;
1066
1067 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1068
1069 spin_lock_irqsave(&card->int_lock, flags);
1070
1071 stat_r = readl(card->membase + STAT);
1072
1073 /* Transmit Status Indicator has been written to T. S. Queue */
1074 if (stat_r & NS_STAT_TSIF) {
1075 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1076 process_tsq(card);
1077 writel(NS_STAT_TSIF, card->membase + STAT);
1078 }
1079
1080 /* Incomplete CS-PDU has been transmitted */
1081 if (stat_r & NS_STAT_TXICP) {
1082 writel(NS_STAT_TXICP, card->membase + STAT);
1083 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1084 card->index);
1085 }
1086
1087 /* Transmit Status Queue 7/8 full */
1088 if (stat_r & NS_STAT_TSQF) {
1089 writel(NS_STAT_TSQF, card->membase + STAT);
1090 PRINTK("nicstar%d: TSQ full.\n", card->index);
1091 process_tsq(card);
1092 }
1093
1094 /* Timer overflow */
1095 if (stat_r & NS_STAT_TMROF) {
1096 writel(NS_STAT_TMROF, card->membase + STAT);
1097 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1098 }
1099
1100 /* PHY device interrupt signal active */
1101 if (stat_r & NS_STAT_PHYI) {
1102 writel(NS_STAT_PHYI, card->membase + STAT);
1103 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1104 if (dev->phy && dev->phy->interrupt) {
1105 dev->phy->interrupt(dev);
1106 }
1107 }
1108
1109 /* Small Buffer Queue is full */
1110 if (stat_r & NS_STAT_SFBQF) {
1111 writel(NS_STAT_SFBQF, card->membase + STAT);
1112 printk("nicstar%d: Small free buffer queue is full.\n",
1113 card->index);
1114 }
1115
1116 /* Large Buffer Queue is full */
1117 if (stat_r & NS_STAT_LFBQF) {
1118 writel(NS_STAT_LFBQF, card->membase + STAT);
1119 printk("nicstar%d: Large free buffer queue is full.\n",
1120 card->index);
1121 }
1122
1123 /* Receive Status Queue is full */
1124 if (stat_r & NS_STAT_RSQF) {
1125 writel(NS_STAT_RSQF, card->membase + STAT);
1126 printk("nicstar%d: RSQ full.\n", card->index);
1127 process_rsq(card);
1128 }
1129
1130 /* Complete CS-PDU received */
1131 if (stat_r & NS_STAT_EOPDU) {
1132 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1133 process_rsq(card);
1134 writel(NS_STAT_EOPDU, card->membase + STAT);
1135 }
1136
1137 /* Raw cell received */
1138 if (stat_r & NS_STAT_RAWCF) {
1139 writel(NS_STAT_RAWCF, card->membase + STAT);
1140#ifndef RCQ_SUPPORT
1141 printk("nicstar%d: Raw cell received and no support yet...\n",
1142 card->index);
1143#endif /* RCQ_SUPPORT */
1144 /* NOTE: the following procedure may keep a raw cell pending until the
1145 next interrupt. As this preliminary support is only meant to
1146 avoid buffer leakage, this is not an issue. */
1147 while (readl(card->membase + RAWCT) != card->rawch) {
1148
1149 if (ns_rcqe_islast(card->rawcell)) {
1150 struct sk_buff *oldbuf;
1151
1152 oldbuf = card->rcbuf;
1153 card->rcbuf = idr_find(&card->idr,
1154 ns_rcqe_nextbufhandle(card->rawcell));
1155 card->rawch = NS_PRV_DMA(card->rcbuf);
1156 card->rawcell = (struct ns_rcqe *)
1157 card->rcbuf->data;
1158 recycle_rx_buf(card, oldbuf);
1159 } else {
1160 card->rawch += NS_RCQE_SIZE;
1161 card->rawcell++;
1162 }
1163 }
1164 }
1165
1166 /* Small buffer queue is empty */
1167 if (stat_r & NS_STAT_SFBQE) {
1168 int i;
1169 struct sk_buff *sb;
1170
1171 writel(NS_STAT_SFBQE, card->membase + STAT);
1172 printk("nicstar%d: Small free buffer queue empty.\n",
1173 card->index);
1174 for (i = 0; i < card->sbnr.min; i++) {
1175 sb = dev_alloc_skb(NS_SMSKBSIZE);
1176 if (sb == NULL) {
1177 writel(readl(card->membase + CFG) &
1178 ~NS_CFG_EFBIE, card->membase + CFG);
1179 card->efbie = 0;
1180 break;
1181 }
1182 NS_PRV_BUFTYPE(sb) = BUF_SM;
1183 skb_queue_tail(&card->sbpool.queue, sb);
1184 skb_reserve(sb, NS_AAL0_HEADER);
1185 push_rxbufs(card, sb);
1186 }
1187 card->sbfqc = i;
1188 process_rsq(card);
1189 }
1190
1191 /* Large buffer queue empty */
1192 if (stat_r & NS_STAT_LFBQE) {
1193 int i;
1194 struct sk_buff *lb;
1195
1196 writel(NS_STAT_LFBQE, card->membase + STAT);
1197 printk("nicstar%d: Large free buffer queue empty.\n",
1198 card->index);
1199 for (i = 0; i < card->lbnr.min; i++) {
1200 lb = dev_alloc_skb(NS_LGSKBSIZE);
1201 if (lb == NULL) {
1202 writel(readl(card->membase + CFG) &
1203 ~NS_CFG_EFBIE, card->membase + CFG);
1204 card->efbie = 0;
1205 break;
1206 }
1207 NS_PRV_BUFTYPE(lb) = BUF_LG;
1208 skb_queue_tail(&card->lbpool.queue, lb);
1209 skb_reserve(lb, NS_SMBUFSIZE);
1210 push_rxbufs(card, lb);
1211 }
1212 card->lbfqc = i;
1213 process_rsq(card);
1214 }
1215
1216 /* Receive Status Queue is 7/8 full */
1217 if (stat_r & NS_STAT_RSQAF) {
1218 writel(NS_STAT_RSQAF, card->membase + STAT);
1219 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1220 process_rsq(card);
1221 }
1222
1223 spin_unlock_irqrestore(&card->int_lock, flags);
1224 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1225 return IRQ_HANDLED;
1226}
1227
1228static int ns_open(struct atm_vcc *vcc)
1229{
1230 ns_dev *card;
1231 vc_map *vc;
1232 unsigned long tmpl, modl;
1233 int tcr, tcra; /* target cell rate, and absolute value */
1234 int n = 0; /* Number of entries in the TST. Initialized to remove
1235 the compiler warning. */
1236 u32 u32d[4];
1237 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1238 warning. How I wish compilers were clever enough to
1239 tell which variables can truly be used
1240 uninitialized... */
1241 int inuse; /* tx or rx vc already in use by another vcc */
1242 short vpi = vcc->vpi;
1243 int vci = vcc->vci;
1244
1245 card = (ns_dev *) vcc->dev->dev_data;
1246 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1247 vci);
1248 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1249 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1250 return -EINVAL;
1251 }
1252
1253 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1254 vcc->dev_data = vc;
1255
1256 inuse = 0;
1257 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1258 inuse = 1;
1259 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1260 inuse += 2;
1261 if (inuse) {
1262 printk("nicstar%d: %s vci already in use.\n", card->index,
1263 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1264 return -EINVAL;
1265 }
1266
1267 set_bit(ATM_VF_ADDR, &vcc->flags);
1268
1269 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1270 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1271 needed to do that. */
1272 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1273 scq_info *scq;
1274
1275 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1276 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1277 /* Check requested cell rate and availability of SCD */
1278 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1279 && vcc->qos.txtp.min_pcr == 0) {
1280 PRINTK
1281 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1282 card->index);
1283 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1284 clear_bit(ATM_VF_ADDR, &vcc->flags);
1285 return -EINVAL;
1286 }
1287
1288 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1289 tcra = tcr >= 0 ? tcr : -tcr;
1290
1291 PRINTK("nicstar%d: target cell rate = %d.\n",
1292 card->index, vcc->qos.txtp.max_pcr);
1293
1294 tmpl =
1295 (unsigned long)tcra *(unsigned long)
1296 NS_TST_NUM_ENTRIES;
1297 modl = tmpl % card->max_pcr;
1298
1299 n = (int)(tmpl / card->max_pcr);
1300 if (tcr > 0) {
1301 if (modl > 0)
1302 n++;
1303 } else if (tcr == 0) {
1304 if ((n =
1305 (card->tst_free_entries -
1306 NS_TST_RESERVED)) <= 0) {
1307 PRINTK
1308 ("nicstar%d: no CBR bandwidth free.\n",
1309 card->index);
1310 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1311 clear_bit(ATM_VF_ADDR, &vcc->flags);
1312 return -EINVAL;
1313 }
1314 }
1315
1316 if (n == 0) {
1317 printk
1318 ("nicstar%d: selected bandwidth < granularity.\n",
1319 card->index);
1320 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1321 clear_bit(ATM_VF_ADDR, &vcc->flags);
1322 return -EINVAL;
1323 }
1324
1325 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1326 PRINTK
1327 ("nicstar%d: not enough free CBR bandwidth.\n",
1328 card->index);
1329 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1330 clear_bit(ATM_VF_ADDR, &vcc->flags);
1331 return -EINVAL;
1332 } else
1333 card->tst_free_entries -= n;
1334
1335 XPRINTK("nicstar%d: writing %d tst entries.\n",
1336 card->index, n);
1337 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1338 if (card->scd2vc[frscdi] == NULL) {
1339 card->scd2vc[frscdi] = vc;
1340 break;
1341 }
1342 }
1343 if (frscdi == NS_FRSCD_NUM) {
1344 PRINTK
1345 ("nicstar%d: no SCD available for CBR channel.\n",
1346 card->index);
1347 card->tst_free_entries += n;
1348 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1349 clear_bit(ATM_VF_ADDR, &vcc->flags);
1350 return -EBUSY;
1351 }
1352
1353 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1354
1355 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1356 if (scq == NULL) {
1357 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1358 card->index);
1359 card->scd2vc[frscdi] = NULL;
1360 card->tst_free_entries += n;
1361 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1362 clear_bit(ATM_VF_ADDR, &vcc->flags);
1363 return -ENOMEM;
1364 }
1365 vc->scq = scq;
1366 u32d[0] = scq_virt_to_bus(scq, scq->base);
1367 u32d[1] = (u32) 0x00000000;
1368 u32d[2] = (u32) 0xffffffff;
1369 u32d[3] = (u32) 0x00000000;
1370 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1371
1372 fill_tst(card, n, vc);
1373 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1374 vc->cbr_scd = 0x00000000;
1375 vc->scq = card->scq0;
1376 }
1377
1378 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1379 vc->tx = 1;
1380 vc->tx_vcc = vcc;
1381 vc->tbd_count = 0;
1382 }
1383 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1384 u32 status;
1385
1386 vc->rx = 1;
1387 vc->rx_vcc = vcc;
1388 vc->rx_iov = NULL;
1389
1390 /* Open the connection in hardware */
1391 if (vcc->qos.aal == ATM_AAL5)
1392 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1393 else /* vcc->qos.aal == ATM_AAL0 */
1394 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1395#ifdef RCQ_SUPPORT
1396 status |= NS_RCTE_RAWCELLINTEN;
1397#endif /* RCQ_SUPPORT */
1398 ns_write_sram(card,
1399 NS_RCT +
1400 (vpi << card->vcibits | vci) *
1401 NS_RCT_ENTRY_SIZE, &status, 1);
1402 }
1403
1404 }
1405
1406 set_bit(ATM_VF_READY, &vcc->flags);
1407 return 0;
1408}
1409
1410static void ns_close(struct atm_vcc *vcc)
1411{
1412 vc_map *vc;
1413 ns_dev *card;
1414 u32 data;
1415 int i;
1416
1417 vc = vcc->dev_data;
1418 card = vcc->dev->dev_data;
1419 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1420 (int)vcc->vpi, vcc->vci);
1421
1422 clear_bit(ATM_VF_READY, &vcc->flags);
1423
1424 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1425 u32 addr;
1426 unsigned long flags;
1427
1428 addr =
1429 NS_RCT +
1430 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1431 spin_lock_irqsave(&card->res_lock, flags);
1432 while (CMD_BUSY(card)) ;
1433 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1434 card->membase + CMD);
1435 spin_unlock_irqrestore(&card->res_lock, flags);
1436
1437 vc->rx = 0;
1438 if (vc->rx_iov != NULL) {
1439 struct sk_buff *iovb;
1440 u32 stat;
1441
1442 stat = readl(card->membase + STAT);
1443 card->sbfqc = ns_stat_sfbqc_get(stat);
1444 card->lbfqc = ns_stat_lfbqc_get(stat);
1445
1446 PRINTK
1447 ("nicstar%d: closing a VC with pending rx buffers.\n",
1448 card->index);
1449 iovb = vc->rx_iov;
1450 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1451 NS_PRV_IOVCNT(iovb));
1452 NS_PRV_IOVCNT(iovb) = 0;
1453 spin_lock_irqsave(&card->int_lock, flags);
1454 recycle_iov_buf(card, iovb);
1455 spin_unlock_irqrestore(&card->int_lock, flags);
1456 vc->rx_iov = NULL;
1457 }
1458 }
1459
1460 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1461 vc->tx = 0;
1462 }
1463
1464 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1465 unsigned long flags;
1466 ns_scqe *scqep;
1467 scq_info *scq;
1468
1469 scq = vc->scq;
1470
1471 for (;;) {
1472 spin_lock_irqsave(&scq->lock, flags);
1473 scqep = scq->next;
1474 if (scqep == scq->base)
1475 scqep = scq->last;
1476 else
1477 scqep--;
1478 if (scqep == scq->tail) {
1479 spin_unlock_irqrestore(&scq->lock, flags);
1480 break;
1481 }
1482 /* If the last entry is not a TSR, place one in the SCQ in order to
1483 be able to completely drain it and then close. */
1484 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1485 ns_scqe tsr;
1486 u32 scdi, scqi;
1487 u32 data;
1488 int index;
1489
1490 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1491 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1492 scqi = scq->next - scq->base;
1493 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1494 tsr.word_3 = 0x00000000;
1495 tsr.word_4 = 0x00000000;
1496 *scq->next = tsr;
1497 index = (int)scqi;
1498 scq->skb[index] = NULL;
1499 if (scq->next == scq->last)
1500 scq->next = scq->base;
1501 else
1502 scq->next++;
1503 data = scq_virt_to_bus(scq, scq->next);
1504 ns_write_sram(card, scq->scd, &data, 1);
1505 }
1506 spin_unlock_irqrestore(&scq->lock, flags);
1507 schedule();
1508 }
1509
1510 /* Free all TST entries */
1511 data = NS_TST_OPCODE_VARIABLE;
1512 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1513 if (card->tste2vc[i] == vc) {
1514 ns_write_sram(card, card->tst_addr + i, &data,
1515 1);
1516 card->tste2vc[i] = NULL;
1517 card->tst_free_entries++;
1518 }
1519 }
1520
1521 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1522 free_scq(card, vc->scq, vcc);
1523 }
1524
1525 /* remove all references to vcc before deleting it */
1526 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1527 unsigned long flags;
1528 scq_info *scq = card->scq0;
1529
1530 spin_lock_irqsave(&scq->lock, flags);
1531
1532 for (i = 0; i < scq->num_entries; i++) {
1533 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1534 ATM_SKB(scq->skb[i])->vcc = NULL;
1535 atm_return(vcc, scq->skb[i]->truesize);
1536 PRINTK
1537 ("nicstar: deleted pending vcc mapping\n");
1538 }
1539 }
1540
1541 spin_unlock_irqrestore(&scq->lock, flags);
1542 }
1543
1544 vcc->dev_data = NULL;
1545 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1546 clear_bit(ATM_VF_ADDR, &vcc->flags);
1547
1548#ifdef RX_DEBUG
1549 {
1550 u32 stat, cfg;
1551 stat = readl(card->membase + STAT);
1552 cfg = readl(card->membase + CFG);
1553 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1554 printk
1555 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1556 card->tsq.base, card->tsq.next,
1557 card->tsq.last, readl(card->membase + TSQT));
1558 printk
1559 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1560 card->rsq.base, card->rsq.next,
1561 card->rsq.last, readl(card->membase + RSQT));
1562 printk("Empty free buffer queue interrupt %s \n",
1563 card->efbie ? "enabled" : "disabled");
1564 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1565 ns_stat_sfbqc_get(stat), card->sbpool.count,
1566 ns_stat_lfbqc_get(stat), card->lbpool.count);
1567 printk("hbpool.count = %d iovpool.count = %d \n",
1568 card->hbpool.count, card->iovpool.count);
1569 }
1570#endif /* RX_DEBUG */
1571}
1572
1573static void fill_tst(ns_dev * card, int n, vc_map * vc)
1574{
1575 u32 new_tst;
1576 unsigned long cl;
1577 int e, r;
1578 u32 data;
1579
1580 /* It would be very complicated to keep the two TSTs synchronized while
1581 assuring that writes are only made to the inactive TST. So, for now I
1582 will use only one TST. If problems occur, I will change this again */
1583
1584 new_tst = card->tst_addr;
1585
1586 /* Fill procedure */
1587
1588 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1589 if (card->tste2vc[e] == NULL)
1590 break;
1591 }
1592 if (e == NS_TST_NUM_ENTRIES) {
1593 printk("nicstar%d: No free TST entries found. \n", card->index);
1594 return;
1595 }
1596
1597 r = n;
1598 cl = NS_TST_NUM_ENTRIES;
1599 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1600
1601 while (r > 0) {
1602 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1603 card->tste2vc[e] = vc;
1604 ns_write_sram(card, new_tst + e, &data, 1);
1605 cl -= NS_TST_NUM_ENTRIES;
1606 r--;
1607 }
1608
1609 if (++e == NS_TST_NUM_ENTRIES) {
1610 e = 0;
1611 }
1612 cl += n;
1613 }
1614
1615 /* End of fill procedure */
1616
1617 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1618 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1619 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1620 card->tst_addr = new_tst;
1621}
1622
1623static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1624{
1625 ns_dev *card;
1626 vc_map *vc;
1627 scq_info *scq;
1628 unsigned long buflen;
1629 ns_scqe scqe;
1630 u32 flags; /* TBD flags, not CPU flags */
1631
1632 card = vcc->dev->dev_data;
1633 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1634 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1635 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1636 card->index);
1637 atomic_inc(&vcc->stats->tx_err);
1638 dev_kfree_skb_any(skb);
1639 return -EINVAL;
1640 }
1641
1642 if (!vc->tx) {
1643 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1644 card->index);
1645 atomic_inc(&vcc->stats->tx_err);
1646 dev_kfree_skb_any(skb);
1647 return -EINVAL;
1648 }
1649
1650 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1651 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1652 card->index);
1653 atomic_inc(&vcc->stats->tx_err);
1654 dev_kfree_skb_any(skb);
1655 return -EINVAL;
1656 }
1657
1658 if (skb_shinfo(skb)->nr_frags != 0) {
1659 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1660 atomic_inc(&vcc->stats->tx_err);
1661 dev_kfree_skb_any(skb);
1662 return -EINVAL;
1663 }
1664
1665 ATM_SKB(skb)->vcc = vcc;
1666
1667 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1668 skb->len, DMA_TO_DEVICE);
1669
1670 if (vcc->qos.aal == ATM_AAL5) {
1671 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1672 flags = NS_TBD_AAL5;
1673 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1674 scqe.word_3 = cpu_to_le32(skb->len);
1675 scqe.word_4 =
1676 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1677 ATM_SKB(skb)->
1678 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1679 flags |= NS_TBD_EOPDU;
1680 } else { /* (vcc->qos.aal == ATM_AAL0) */
1681
1682 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1683 flags = NS_TBD_AAL0;
1684 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1685 scqe.word_3 = cpu_to_le32(0x00000000);
1686 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1687 flags |= NS_TBD_EOPDU;
1688 scqe.word_4 =
1689 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1690 /* Force the VPI/VCI to be the same as in VCC struct */
1691 scqe.word_4 |=
1692 cpu_to_le32((((u32) vcc->
1693 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1694 vci) <<
1695 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1696 }
1697
1698 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1699 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1700 scq = ((vc_map *) vcc->dev_data)->scq;
1701 } else {
1702 scqe.word_1 =
1703 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1704 scq = card->scq0;
1705 }
1706
1707 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1708 atomic_inc(&vcc->stats->tx_err);
1709 dev_kfree_skb_any(skb);
1710 return -EIO;
1711 }
1712 atomic_inc(&vcc->stats->tx);
1713
1714 return 0;
1715}
1716
1717static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1718 struct sk_buff *skb)
1719{
1720 unsigned long flags;
1721 ns_scqe tsr;
1722 u32 scdi, scqi;
1723 int scq_is_vbr;
1724 u32 data;
1725 int index;
1726
1727 spin_lock_irqsave(&scq->lock, flags);
1728 while (scq->tail == scq->next) {
1729 if (in_interrupt()) {
1730 spin_unlock_irqrestore(&scq->lock, flags);
1731 printk("nicstar%d: Error pushing TBD.\n", card->index);
1732 return 1;
1733 }
1734
1735 scq->full = 1;
1736 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1737 scq->tail != scq->next,
1738 scq->lock,
1739 SCQFULL_TIMEOUT);
1740
1741 if (scq->full) {
1742 spin_unlock_irqrestore(&scq->lock, flags);
1743 printk("nicstar%d: Timeout pushing TBD.\n",
1744 card->index);
1745 return 1;
1746 }
1747 }
1748 *scq->next = *tbd;
1749 index = (int)(scq->next - scq->base);
1750 scq->skb[index] = skb;
1751 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1752 card->index, skb, index);
1753 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1754 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1755 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1756 scq->next);
1757 if (scq->next == scq->last)
1758 scq->next = scq->base;
1759 else
1760 scq->next++;
1761
1762 vc->tbd_count++;
1763 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1764 scq->tbd_count++;
1765 scq_is_vbr = 1;
1766 } else
1767 scq_is_vbr = 0;
1768
1769 if (vc->tbd_count >= MAX_TBD_PER_VC
1770 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1771 int has_run = 0;
1772
1773 while (scq->tail == scq->next) {
1774 if (in_interrupt()) {
1775 data = scq_virt_to_bus(scq, scq->next);
1776 ns_write_sram(card, scq->scd, &data, 1);
1777 spin_unlock_irqrestore(&scq->lock, flags);
1778 printk("nicstar%d: Error pushing TSR.\n",
1779 card->index);
1780 return 0;
1781 }
1782
1783 scq->full = 1;
1784 if (has_run++)
1785 break;
1786 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1787 scq->tail != scq->next,
1788 scq->lock,
1789 SCQFULL_TIMEOUT);
1790 }
1791
1792 if (!scq->full) {
1793 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1794 if (scq_is_vbr)
1795 scdi = NS_TSR_SCDISVBR;
1796 else
1797 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1798 scqi = scq->next - scq->base;
1799 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1800 tsr.word_3 = 0x00000000;
1801 tsr.word_4 = 0x00000000;
1802
1803 *scq->next = tsr;
1804 index = (int)scqi;
1805 scq->skb[index] = NULL;
1806 XPRINTK
1807 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1808 card->index, le32_to_cpu(tsr.word_1),
1809 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1810 le32_to_cpu(tsr.word_4), scq->next);
1811 if (scq->next == scq->last)
1812 scq->next = scq->base;
1813 else
1814 scq->next++;
1815 vc->tbd_count = 0;
1816 scq->tbd_count = 0;
1817 } else
1818 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1819 card->index);
1820 }
1821 data = scq_virt_to_bus(scq, scq->next);
1822 ns_write_sram(card, scq->scd, &data, 1);
1823
1824 spin_unlock_irqrestore(&scq->lock, flags);
1825
1826 return 0;
1827}
1828
1829static void process_tsq(ns_dev * card)
1830{
1831 u32 scdi;
1832 scq_info *scq;
1833 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1834 int serviced_entries; /* flag indicating at least on entry was serviced */
1835
1836 serviced_entries = 0;
1837
1838 if (card->tsq.next == card->tsq.last)
1839 one_ahead = card->tsq.base;
1840 else
1841 one_ahead = card->tsq.next + 1;
1842
1843 if (one_ahead == card->tsq.last)
1844 two_ahead = card->tsq.base;
1845 else
1846 two_ahead = one_ahead + 1;
1847
1848 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1849 !ns_tsi_isempty(two_ahead))
1850 /* At most two empty, as stated in the 77201 errata */
1851 {
1852 serviced_entries = 1;
1853
1854 /* Skip the one or two possible empty entries */
1855 while (ns_tsi_isempty(card->tsq.next)) {
1856 if (card->tsq.next == card->tsq.last)
1857 card->tsq.next = card->tsq.base;
1858 else
1859 card->tsq.next++;
1860 }
1861
1862 if (!ns_tsi_tmrof(card->tsq.next)) {
1863 scdi = ns_tsi_getscdindex(card->tsq.next);
1864 if (scdi == NS_TSI_SCDISVBR)
1865 scq = card->scq0;
1866 else {
1867 if (card->scd2vc[scdi] == NULL) {
1868 printk
1869 ("nicstar%d: could not find VC from SCD index.\n",
1870 card->index);
1871 ns_tsi_init(card->tsq.next);
1872 return;
1873 }
1874 scq = card->scd2vc[scdi]->scq;
1875 }
1876 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1877 scq->full = 0;
1878 wake_up_interruptible(&(scq->scqfull_waitq));
1879 }
1880
1881 ns_tsi_init(card->tsq.next);
1882 previous = card->tsq.next;
1883 if (card->tsq.next == card->tsq.last)
1884 card->tsq.next = card->tsq.base;
1885 else
1886 card->tsq.next++;
1887
1888 if (card->tsq.next == card->tsq.last)
1889 one_ahead = card->tsq.base;
1890 else
1891 one_ahead = card->tsq.next + 1;
1892
1893 if (one_ahead == card->tsq.last)
1894 two_ahead = card->tsq.base;
1895 else
1896 two_ahead = one_ahead + 1;
1897 }
1898
1899 if (serviced_entries)
1900 writel(PTR_DIFF(previous, card->tsq.base),
1901 card->membase + TSQH);
1902}
1903
1904static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1905{
1906 struct atm_vcc *vcc;
1907 struct sk_buff *skb;
1908 int i;
1909 unsigned long flags;
1910
1911 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1912 card->index, scq, pos);
1913 if (pos >= scq->num_entries) {
1914 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1915 return;
1916 }
1917
1918 spin_lock_irqsave(&scq->lock, flags);
1919 i = (int)(scq->tail - scq->base);
1920 if (++i == scq->num_entries)
1921 i = 0;
1922 while (i != pos) {
1923 skb = scq->skb[i];
1924 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1925 card->index, skb, i);
1926 if (skb != NULL) {
1927 dma_unmap_single(&card->pcidev->dev,
1928 NS_PRV_DMA(skb),
1929 skb->len,
1930 DMA_TO_DEVICE);
1931 vcc = ATM_SKB(skb)->vcc;
1932 if (vcc && vcc->pop != NULL) {
1933 vcc->pop(vcc, skb);
1934 } else {
1935 dev_kfree_skb_irq(skb);
1936 }
1937 scq->skb[i] = NULL;
1938 }
1939 if (++i == scq->num_entries)
1940 i = 0;
1941 }
1942 scq->tail = scq->base + pos;
1943 spin_unlock_irqrestore(&scq->lock, flags);
1944}
1945
1946static void process_rsq(ns_dev * card)
1947{
1948 ns_rsqe *previous;
1949
1950 if (!ns_rsqe_valid(card->rsq.next))
1951 return;
1952 do {
1953 dequeue_rx(card, card->rsq.next);
1954 ns_rsqe_init(card->rsq.next);
1955 previous = card->rsq.next;
1956 if (card->rsq.next == card->rsq.last)
1957 card->rsq.next = card->rsq.base;
1958 else
1959 card->rsq.next++;
1960 } while (ns_rsqe_valid(card->rsq.next));
1961 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1962}
1963
1964static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1965{
1966 u32 vpi, vci;
1967 vc_map *vc;
1968 struct sk_buff *iovb;
1969 struct iovec *iov;
1970 struct atm_vcc *vcc;
1971 struct sk_buff *skb;
1972 unsigned short aal5_len;
1973 int len;
1974 u32 stat;
1975 u32 id;
1976
1977 stat = readl(card->membase + STAT);
1978 card->sbfqc = ns_stat_sfbqc_get(stat);
1979 card->lbfqc = ns_stat_lfbqc_get(stat);
1980
1981 id = le32_to_cpu(rsqe->buffer_handle);
1982 skb = idr_remove(&card->idr, id);
1983 if (!skb) {
1984 RXPRINTK(KERN_ERR
1985 "nicstar%d: skb not found!\n", card->index);
1986 return;
1987 }
1988 dma_sync_single_for_cpu(&card->pcidev->dev,
1989 NS_PRV_DMA(skb),
1990 (NS_PRV_BUFTYPE(skb) == BUF_SM
1991 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1992 DMA_FROM_DEVICE);
1993 dma_unmap_single(&card->pcidev->dev,
1994 NS_PRV_DMA(skb),
1995 (NS_PRV_BUFTYPE(skb) == BUF_SM
1996 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1997 DMA_FROM_DEVICE);
1998 vpi = ns_rsqe_vpi(rsqe);
1999 vci = ns_rsqe_vci(rsqe);
2000 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2001 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2002 card->index, vpi, vci);
2003 recycle_rx_buf(card, skb);
2004 return;
2005 }
2006
2007 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2008 if (!vc->rx) {
2009 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2010 card->index, vpi, vci);
2011 recycle_rx_buf(card, skb);
2012 return;
2013 }
2014
2015 vcc = vc->rx_vcc;
2016
2017 if (vcc->qos.aal == ATM_AAL0) {
2018 struct sk_buff *sb;
2019 unsigned char *cell;
2020 int i;
2021
2022 cell = skb->data;
2023 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2024 sb = dev_alloc_skb(NS_SMSKBSIZE);
2025 if (!sb) {
2026 printk
2027 ("nicstar%d: Can't allocate buffers for aal0.\n",
2028 card->index);
2029 atomic_add(i, &vcc->stats->rx_drop);
2030 break;
2031 }
2032 if (!atm_charge(vcc, sb->truesize)) {
2033 RXPRINTK
2034 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2035 card->index);
2036 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2037 dev_kfree_skb_any(sb);
2038 break;
2039 }
2040 /* Rebuild the header */
2041 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2042 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2043 if (i == 1 && ns_rsqe_eopdu(rsqe))
2044 *((u32 *) sb->data) |= 0x00000002;
2045 skb_put(sb, NS_AAL0_HEADER);
2046 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2047 skb_put(sb, ATM_CELL_PAYLOAD);
2048 ATM_SKB(sb)->vcc = vcc;
2049 __net_timestamp(sb);
2050 vcc->push(vcc, sb);
2051 atomic_inc(&vcc->stats->rx);
2052 cell += ATM_CELL_PAYLOAD;
2053 }
2054
2055 recycle_rx_buf(card, skb);
2056 return;
2057 }
2058
2059 /* To reach this point, the AAL layer can only be AAL5 */
2060
2061 if ((iovb = vc->rx_iov) == NULL) {
2062 iovb = skb_dequeue(&(card->iovpool.queue));
2063 if (iovb == NULL) { /* No buffers in the queue */
2064 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2065 if (iovb == NULL) {
2066 printk("nicstar%d: Out of iovec buffers.\n",
2067 card->index);
2068 atomic_inc(&vcc->stats->rx_drop);
2069 recycle_rx_buf(card, skb);
2070 return;
2071 }
2072 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2073 } else if (--card->iovpool.count < card->iovnr.min) {
2074 struct sk_buff *new_iovb;
2075 if ((new_iovb =
2076 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2077 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2078 skb_queue_tail(&card->iovpool.queue, new_iovb);
2079 card->iovpool.count++;
2080 }
2081 }
2082 vc->rx_iov = iovb;
2083 NS_PRV_IOVCNT(iovb) = 0;
2084 iovb->len = 0;
2085 iovb->data = iovb->head;
2086 skb_reset_tail_pointer(iovb);
2087 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2088 buffer is stored as iovec base, NOT a pointer to the
2089 small or large buffer itself. */
2090 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2091 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2092 atomic_inc(&vcc->stats->rx_err);
2093 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2094 NS_MAX_IOVECS);
2095 NS_PRV_IOVCNT(iovb) = 0;
2096 iovb->len = 0;
2097 iovb->data = iovb->head;
2098 skb_reset_tail_pointer(iovb);
2099 }
2100 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2101 iov->iov_base = (void *)skb;
2102 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2103 iovb->len += iov->iov_len;
2104
2105#ifdef EXTRA_DEBUG
2106 if (NS_PRV_IOVCNT(iovb) == 1) {
2107 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2108 printk
2109 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2110 card->index);
2111 which_list(card, skb);
2112 atomic_inc(&vcc->stats->rx_err);
2113 recycle_rx_buf(card, skb);
2114 vc->rx_iov = NULL;
2115 recycle_iov_buf(card, iovb);
2116 return;
2117 }
2118 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2119
2120 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2121 printk
2122 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2123 card->index);
2124 which_list(card, skb);
2125 atomic_inc(&vcc->stats->rx_err);
2126 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2127 NS_PRV_IOVCNT(iovb));
2128 vc->rx_iov = NULL;
2129 recycle_iov_buf(card, iovb);
2130 return;
2131 }
2132 }
2133#endif /* EXTRA_DEBUG */
2134
2135 if (ns_rsqe_eopdu(rsqe)) {
2136 /* This works correctly regardless of the endianness of the host */
2137 unsigned char *L1L2 = (unsigned char *)
2138 (skb->data + iov->iov_len - 6);
2139 aal5_len = L1L2[0] << 8 | L1L2[1];
2140 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2141 if (ns_rsqe_crcerr(rsqe) ||
2142 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2143 printk("nicstar%d: AAL5 CRC error", card->index);
2144 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2145 printk(" - PDU size mismatch.\n");
2146 else
2147 printk(".\n");
2148 atomic_inc(&vcc->stats->rx_err);
2149 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2150 NS_PRV_IOVCNT(iovb));
2151 vc->rx_iov = NULL;
2152 recycle_iov_buf(card, iovb);
2153 return;
2154 }
2155
2156 /* By this point we (hopefully) have a complete SDU without errors. */
2157
2158 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2159 /* skb points to a small buffer */
2160 if (!atm_charge(vcc, skb->truesize)) {
2161 push_rxbufs(card, skb);
2162 atomic_inc(&vcc->stats->rx_drop);
2163 } else {
2164 skb_put(skb, len);
2165 dequeue_sm_buf(card, skb);
2166 ATM_SKB(skb)->vcc = vcc;
2167 __net_timestamp(skb);
2168 vcc->push(vcc, skb);
2169 atomic_inc(&vcc->stats->rx);
2170 }
2171 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2172 struct sk_buff *sb;
2173
2174 sb = (struct sk_buff *)(iov - 1)->iov_base;
2175 /* skb points to a large buffer */
2176
2177 if (len <= NS_SMBUFSIZE) {
2178 if (!atm_charge(vcc, sb->truesize)) {
2179 push_rxbufs(card, sb);
2180 atomic_inc(&vcc->stats->rx_drop);
2181 } else {
2182 skb_put(sb, len);
2183 dequeue_sm_buf(card, sb);
2184 ATM_SKB(sb)->vcc = vcc;
2185 __net_timestamp(sb);
2186 vcc->push(vcc, sb);
2187 atomic_inc(&vcc->stats->rx);
2188 }
2189
2190 push_rxbufs(card, skb);
2191
2192 } else { /* len > NS_SMBUFSIZE, the usual case */
2193
2194 if (!atm_charge(vcc, skb->truesize)) {
2195 push_rxbufs(card, skb);
2196 atomic_inc(&vcc->stats->rx_drop);
2197 } else {
2198 dequeue_lg_buf(card, skb);
2199 skb_push(skb, NS_SMBUFSIZE);
2200 skb_copy_from_linear_data(sb, skb->data,
2201 NS_SMBUFSIZE);
2202 skb_put(skb, len - NS_SMBUFSIZE);
2203 ATM_SKB(skb)->vcc = vcc;
2204 __net_timestamp(skb);
2205 vcc->push(vcc, skb);
2206 atomic_inc(&vcc->stats->rx);
2207 }
2208
2209 push_rxbufs(card, sb);
2210
2211 }
2212
2213 } else { /* Must push a huge buffer */
2214
2215 struct sk_buff *hb, *sb, *lb;
2216 int remaining, tocopy;
2217 int j;
2218
2219 hb = skb_dequeue(&(card->hbpool.queue));
2220 if (hb == NULL) { /* No buffers in the queue */
2221
2222 hb = dev_alloc_skb(NS_HBUFSIZE);
2223 if (hb == NULL) {
2224 printk
2225 ("nicstar%d: Out of huge buffers.\n",
2226 card->index);
2227 atomic_inc(&vcc->stats->rx_drop);
2228 recycle_iovec_rx_bufs(card,
2229 (struct iovec *)
2230 iovb->data,
2231 NS_PRV_IOVCNT(iovb));
2232 vc->rx_iov = NULL;
2233 recycle_iov_buf(card, iovb);
2234 return;
2235 } else if (card->hbpool.count < card->hbnr.min) {
2236 struct sk_buff *new_hb;
2237 if ((new_hb =
2238 dev_alloc_skb(NS_HBUFSIZE)) !=
2239 NULL) {
2240 skb_queue_tail(&card->hbpool.
2241 queue, new_hb);
2242 card->hbpool.count++;
2243 }
2244 }
2245 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2246 } else if (--card->hbpool.count < card->hbnr.min) {
2247 struct sk_buff *new_hb;
2248 if ((new_hb =
2249 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2250 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2251 skb_queue_tail(&card->hbpool.queue,
2252 new_hb);
2253 card->hbpool.count++;
2254 }
2255 if (card->hbpool.count < card->hbnr.min) {
2256 if ((new_hb =
2257 dev_alloc_skb(NS_HBUFSIZE)) !=
2258 NULL) {
2259 NS_PRV_BUFTYPE(new_hb) =
2260 BUF_NONE;
2261 skb_queue_tail(&card->hbpool.
2262 queue, new_hb);
2263 card->hbpool.count++;
2264 }
2265 }
2266 }
2267
2268 iov = (struct iovec *)iovb->data;
2269
2270 if (!atm_charge(vcc, hb->truesize)) {
2271 recycle_iovec_rx_bufs(card, iov,
2272 NS_PRV_IOVCNT(iovb));
2273 if (card->hbpool.count < card->hbnr.max) {
2274 skb_queue_tail(&card->hbpool.queue, hb);
2275 card->hbpool.count++;
2276 } else
2277 dev_kfree_skb_any(hb);
2278 atomic_inc(&vcc->stats->rx_drop);
2279 } else {
2280 /* Copy the small buffer to the huge buffer */
2281 sb = (struct sk_buff *)iov->iov_base;
2282 skb_copy_from_linear_data(sb, hb->data,
2283 iov->iov_len);
2284 skb_put(hb, iov->iov_len);
2285 remaining = len - iov->iov_len;
2286 iov++;
2287 /* Free the small buffer */
2288 push_rxbufs(card, sb);
2289
2290 /* Copy all large buffers to the huge buffer and free them */
2291 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2292 lb = (struct sk_buff *)iov->iov_base;
2293 tocopy =
2294 min_t(int, remaining, iov->iov_len);
2295 skb_copy_from_linear_data(lb,
2296 skb_tail_pointer
2297 (hb), tocopy);
2298 skb_put(hb, tocopy);
2299 iov++;
2300 remaining -= tocopy;
2301 push_rxbufs(card, lb);
2302 }
2303#ifdef EXTRA_DEBUG
2304 if (remaining != 0 || hb->len != len)
2305 printk
2306 ("nicstar%d: Huge buffer len mismatch.\n",
2307 card->index);
2308#endif /* EXTRA_DEBUG */
2309 ATM_SKB(hb)->vcc = vcc;
2310 __net_timestamp(hb);
2311 vcc->push(vcc, hb);
2312 atomic_inc(&vcc->stats->rx);
2313 }
2314 }
2315
2316 vc->rx_iov = NULL;
2317 recycle_iov_buf(card, iovb);
2318 }
2319
2320}
2321
2322static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2323{
2324 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2325 printk("nicstar%d: What kind of rx buffer is this?\n",
2326 card->index);
2327 dev_kfree_skb_any(skb);
2328 } else
2329 push_rxbufs(card, skb);
2330}
2331
2332static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2333{
2334 while (count-- > 0)
2335 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2336}
2337
2338static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2339{
2340 if (card->iovpool.count < card->iovnr.max) {
2341 skb_queue_tail(&card->iovpool.queue, iovb);
2342 card->iovpool.count++;
2343 } else
2344 dev_kfree_skb_any(iovb);
2345}
2346
2347static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2348{
2349 skb_unlink(sb, &card->sbpool.queue);
2350 if (card->sbfqc < card->sbnr.init) {
2351 struct sk_buff *new_sb;
2352 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2353 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2354 skb_queue_tail(&card->sbpool.queue, new_sb);
2355 skb_reserve(new_sb, NS_AAL0_HEADER);
2356 push_rxbufs(card, new_sb);
2357 }
2358 }
2359 if (card->sbfqc < card->sbnr.init)
2360 {
2361 struct sk_buff *new_sb;
2362 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2363 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2364 skb_queue_tail(&card->sbpool.queue, new_sb);
2365 skb_reserve(new_sb, NS_AAL0_HEADER);
2366 push_rxbufs(card, new_sb);
2367 }
2368 }
2369}
2370
2371static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2372{
2373 skb_unlink(lb, &card->lbpool.queue);
2374 if (card->lbfqc < card->lbnr.init) {
2375 struct sk_buff *new_lb;
2376 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2377 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2378 skb_queue_tail(&card->lbpool.queue, new_lb);
2379 skb_reserve(new_lb, NS_SMBUFSIZE);
2380 push_rxbufs(card, new_lb);
2381 }
2382 }
2383 if (card->lbfqc < card->lbnr.init)
2384 {
2385 struct sk_buff *new_lb;
2386 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2387 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2388 skb_queue_tail(&card->lbpool.queue, new_lb);
2389 skb_reserve(new_lb, NS_SMBUFSIZE);
2390 push_rxbufs(card, new_lb);
2391 }
2392 }
2393}
2394
2395static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2396{
2397 u32 stat;
2398 ns_dev *card;
2399 int left;
2400
2401 left = (int)*pos;
2402 card = (ns_dev *) dev->dev_data;
2403 stat = readl(card->membase + STAT);
2404 if (!left--)
2405 return sprintf(page, "Pool count min init max \n");
2406 if (!left--)
2407 return sprintf(page, "Small %5d %5d %5d %5d \n",
2408 ns_stat_sfbqc_get(stat), card->sbnr.min,
2409 card->sbnr.init, card->sbnr.max);
2410 if (!left--)
2411 return sprintf(page, "Large %5d %5d %5d %5d \n",
2412 ns_stat_lfbqc_get(stat), card->lbnr.min,
2413 card->lbnr.init, card->lbnr.max);
2414 if (!left--)
2415 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2416 card->hbpool.count, card->hbnr.min,
2417 card->hbnr.init, card->hbnr.max);
2418 if (!left--)
2419 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2420 card->iovpool.count, card->iovnr.min,
2421 card->iovnr.init, card->iovnr.max);
2422 if (!left--) {
2423 int retval;
2424 retval =
2425 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2426 card->intcnt = 0;
2427 return retval;
2428 }
2429#if 0
2430 /* Dump 25.6 Mbps PHY registers */
2431 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2432 here just in case it's needed for debugging. */
2433 if (card->max_pcr == ATM_25_PCR && !left--) {
2434 u32 phy_regs[4];
2435 u32 i;
2436
2437 for (i = 0; i < 4; i++) {
2438 while (CMD_BUSY(card)) ;
2439 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2440 card->membase + CMD);
2441 while (CMD_BUSY(card)) ;
2442 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2443 }
2444
2445 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2446 phy_regs[0], phy_regs[1], phy_regs[2],
2447 phy_regs[3]);
2448 }
2449#endif /* 0 - Dump 25.6 Mbps PHY registers */
2450#if 0
2451 /* Dump TST */
2452 if (left-- < NS_TST_NUM_ENTRIES) {
2453 if (card->tste2vc[left + 1] == NULL)
2454 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2455 else
2456 return sprintf(page, "%5d - %d %d \n", left + 1,
2457 card->tste2vc[left + 1]->tx_vcc->vpi,
2458 card->tste2vc[left + 1]->tx_vcc->vci);
2459 }
2460#endif /* 0 */
2461 return 0;
2462}
2463
2464static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2465{
2466 ns_dev *card;
2467 pool_levels pl;
2468 long btype;
2469 unsigned long flags;
2470
2471 card = dev->dev_data;
2472 switch (cmd) {
2473 case NS_GETPSTAT:
2474 if (get_user
2475 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2476 return -EFAULT;
2477 switch (pl.buftype) {
2478 case NS_BUFTYPE_SMALL:
2479 pl.count =
2480 ns_stat_sfbqc_get(readl(card->membase + STAT));
2481 pl.level.min = card->sbnr.min;
2482 pl.level.init = card->sbnr.init;
2483 pl.level.max = card->sbnr.max;
2484 break;
2485
2486 case NS_BUFTYPE_LARGE:
2487 pl.count =
2488 ns_stat_lfbqc_get(readl(card->membase + STAT));
2489 pl.level.min = card->lbnr.min;
2490 pl.level.init = card->lbnr.init;
2491 pl.level.max = card->lbnr.max;
2492 break;
2493
2494 case NS_BUFTYPE_HUGE:
2495 pl.count = card->hbpool.count;
2496 pl.level.min = card->hbnr.min;
2497 pl.level.init = card->hbnr.init;
2498 pl.level.max = card->hbnr.max;
2499 break;
2500
2501 case NS_BUFTYPE_IOVEC:
2502 pl.count = card->iovpool.count;
2503 pl.level.min = card->iovnr.min;
2504 pl.level.init = card->iovnr.init;
2505 pl.level.max = card->iovnr.max;
2506 break;
2507
2508 default:
2509 return -ENOIOCTLCMD;
2510
2511 }
2512 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2513 return (sizeof(pl));
2514 else
2515 return -EFAULT;
2516
2517 case NS_SETBUFLEV:
2518 if (!capable(CAP_NET_ADMIN))
2519 return -EPERM;
2520 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2521 return -EFAULT;
2522 if (pl.level.min >= pl.level.init
2523 || pl.level.init >= pl.level.max)
2524 return -EINVAL;
2525 if (pl.level.min == 0)
2526 return -EINVAL;
2527 switch (pl.buftype) {
2528 case NS_BUFTYPE_SMALL:
2529 if (pl.level.max > TOP_SB)
2530 return -EINVAL;
2531 card->sbnr.min = pl.level.min;
2532 card->sbnr.init = pl.level.init;
2533 card->sbnr.max = pl.level.max;
2534 break;
2535
2536 case NS_BUFTYPE_LARGE:
2537 if (pl.level.max > TOP_LB)
2538 return -EINVAL;
2539 card->lbnr.min = pl.level.min;
2540 card->lbnr.init = pl.level.init;
2541 card->lbnr.max = pl.level.max;
2542 break;
2543
2544 case NS_BUFTYPE_HUGE:
2545 if (pl.level.max > TOP_HB)
2546 return -EINVAL;
2547 card->hbnr.min = pl.level.min;
2548 card->hbnr.init = pl.level.init;
2549 card->hbnr.max = pl.level.max;
2550 break;
2551
2552 case NS_BUFTYPE_IOVEC:
2553 if (pl.level.max > TOP_IOVB)
2554 return -EINVAL;
2555 card->iovnr.min = pl.level.min;
2556 card->iovnr.init = pl.level.init;
2557 card->iovnr.max = pl.level.max;
2558 break;
2559
2560 default:
2561 return -EINVAL;
2562
2563 }
2564 return 0;
2565
2566 case NS_ADJBUFLEV:
2567 if (!capable(CAP_NET_ADMIN))
2568 return -EPERM;
2569 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2570 switch (btype) {
2571 case NS_BUFTYPE_SMALL:
2572 while (card->sbfqc < card->sbnr.init) {
2573 struct sk_buff *sb;
2574
2575 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2576 if (sb == NULL)
2577 return -ENOMEM;
2578 NS_PRV_BUFTYPE(sb) = BUF_SM;
2579 skb_queue_tail(&card->sbpool.queue, sb);
2580 skb_reserve(sb, NS_AAL0_HEADER);
2581 push_rxbufs(card, sb);
2582 }
2583 break;
2584
2585 case NS_BUFTYPE_LARGE:
2586 while (card->lbfqc < card->lbnr.init) {
2587 struct sk_buff *lb;
2588
2589 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2590 if (lb == NULL)
2591 return -ENOMEM;
2592 NS_PRV_BUFTYPE(lb) = BUF_LG;
2593 skb_queue_tail(&card->lbpool.queue, lb);
2594 skb_reserve(lb, NS_SMBUFSIZE);
2595 push_rxbufs(card, lb);
2596 }
2597 break;
2598
2599 case NS_BUFTYPE_HUGE:
2600 while (card->hbpool.count > card->hbnr.init) {
2601 struct sk_buff *hb;
2602
2603 spin_lock_irqsave(&card->int_lock, flags);
2604 hb = skb_dequeue(&card->hbpool.queue);
2605 card->hbpool.count--;
2606 spin_unlock_irqrestore(&card->int_lock, flags);
2607 if (hb == NULL)
2608 printk
2609 ("nicstar%d: huge buffer count inconsistent.\n",
2610 card->index);
2611 else
2612 dev_kfree_skb_any(hb);
2613
2614 }
2615 while (card->hbpool.count < card->hbnr.init) {
2616 struct sk_buff *hb;
2617
2618 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2619 if (hb == NULL)
2620 return -ENOMEM;
2621 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2622 spin_lock_irqsave(&card->int_lock, flags);
2623 skb_queue_tail(&card->hbpool.queue, hb);
2624 card->hbpool.count++;
2625 spin_unlock_irqrestore(&card->int_lock, flags);
2626 }
2627 break;
2628
2629 case NS_BUFTYPE_IOVEC:
2630 while (card->iovpool.count > card->iovnr.init) {
2631 struct sk_buff *iovb;
2632
2633 spin_lock_irqsave(&card->int_lock, flags);
2634 iovb = skb_dequeue(&card->iovpool.queue);
2635 card->iovpool.count--;
2636 spin_unlock_irqrestore(&card->int_lock, flags);
2637 if (iovb == NULL)
2638 printk
2639 ("nicstar%d: iovec buffer count inconsistent.\n",
2640 card->index);
2641 else
2642 dev_kfree_skb_any(iovb);
2643
2644 }
2645 while (card->iovpool.count < card->iovnr.init) {
2646 struct sk_buff *iovb;
2647
2648 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2649 if (iovb == NULL)
2650 return -ENOMEM;
2651 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2652 spin_lock_irqsave(&card->int_lock, flags);
2653 skb_queue_tail(&card->iovpool.queue, iovb);
2654 card->iovpool.count++;
2655 spin_unlock_irqrestore(&card->int_lock, flags);
2656 }
2657 break;
2658
2659 default:
2660 return -EINVAL;
2661
2662 }
2663 return 0;
2664
2665 default:
2666 if (dev->phy && dev->phy->ioctl) {
2667 return dev->phy->ioctl(dev, cmd, arg);
2668 } else {
2669 printk("nicstar%d: %s == NULL \n", card->index,
2670 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2671 return -ENOIOCTLCMD;
2672 }
2673 }
2674}
2675
2676#ifdef EXTRA_DEBUG
2677static void which_list(ns_dev * card, struct sk_buff *skb)
2678{
2679 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2680}
2681#endif /* EXTRA_DEBUG */
2682
2683static void ns_poll(struct timer_list *unused)
2684{
2685 int i;
2686 ns_dev *card;
2687 unsigned long flags;
2688 u32 stat_r, stat_w;
2689
2690 PRINTK("nicstar: Entering ns_poll().\n");
2691 for (i = 0; i < num_cards; i++) {
2692 card = cards[i];
2693 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2694 /* Probably it isn't worth spinning */
2695 continue;
2696 }
2697
2698 stat_w = 0;
2699 stat_r = readl(card->membase + STAT);
2700 if (stat_r & NS_STAT_TSIF)
2701 stat_w |= NS_STAT_TSIF;
2702 if (stat_r & NS_STAT_EOPDU)
2703 stat_w |= NS_STAT_EOPDU;
2704
2705 process_tsq(card);
2706 process_rsq(card);
2707
2708 writel(stat_w, card->membase + STAT);
2709 spin_unlock_irqrestore(&card->int_lock, flags);
2710 }
2711 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2712 PRINTK("nicstar: Leaving ns_poll().\n");
2713}
2714
2715static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2716 unsigned long addr)
2717{
2718 ns_dev *card;
2719 unsigned long flags;
2720
2721 card = dev->dev_data;
2722 spin_lock_irqsave(&card->res_lock, flags);
2723 while (CMD_BUSY(card)) ;
2724 writel((u32) value, card->membase + DR0);
2725 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2726 card->membase + CMD);
2727 spin_unlock_irqrestore(&card->res_lock, flags);
2728}
2729
2730static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2731{
2732 ns_dev *card;
2733 unsigned long flags;
2734 u32 data;
2735
2736 card = dev->dev_data;
2737 spin_lock_irqsave(&card->res_lock, flags);
2738 while (CMD_BUSY(card)) ;
2739 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2740 card->membase + CMD);
2741 while (CMD_BUSY(card)) ;
2742 data = readl(card->membase + DR0) & 0x000000FF;
2743 spin_unlock_irqrestore(&card->res_lock, flags);
2744 return (unsigned char)data;
2745}
2746
2747module_init(nicstar_init);
2748module_exit(nicstar_cleanup);