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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SGI UltraViolet TLB flush routines.
4 *
5 * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
6 */
7#include <linux/seq_file.h>
8#include <linux/proc_fs.h>
9#include <linux/debugfs.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/delay.h>
13
14#include <asm/mmu_context.h>
15#include <asm/uv/uv.h>
16#include <asm/uv/uv_mmrs.h>
17#include <asm/uv/uv_hub.h>
18#include <asm/uv/uv_bau.h>
19#include <asm/apic.h>
20#include <asm/tsc.h>
21#include <asm/irq_vectors.h>
22#include <asm/timer.h>
23
24static struct bau_operations ops __ro_after_init;
25
26/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
27static const int timeout_base_ns[] = {
28 20,
29 160,
30 1280,
31 10240,
32 81920,
33 655360,
34 5242880,
35 167772160
36};
37
38static int timeout_us;
39static bool nobau = true;
40static int nobau_perm;
41
42/* tunables: */
43static int max_concurr = MAX_BAU_CONCURRENT;
44static int max_concurr_const = MAX_BAU_CONCURRENT;
45static int plugged_delay = PLUGGED_DELAY;
46static int plugsb4reset = PLUGSB4RESET;
47static int giveup_limit = GIVEUP_LIMIT;
48static int timeoutsb4reset = TIMEOUTSB4RESET;
49static int ipi_reset_limit = IPI_RESET_LIMIT;
50static int complete_threshold = COMPLETE_THRESHOLD;
51static int congested_respns_us = CONGESTED_RESPONSE_US;
52static int congested_reps = CONGESTED_REPS;
53static int disabled_period = DISABLED_PERIOD;
54
55static struct tunables tunables[] = {
56 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
57 {&plugged_delay, PLUGGED_DELAY},
58 {&plugsb4reset, PLUGSB4RESET},
59 {&timeoutsb4reset, TIMEOUTSB4RESET},
60 {&ipi_reset_limit, IPI_RESET_LIMIT},
61 {&complete_threshold, COMPLETE_THRESHOLD},
62 {&congested_respns_us, CONGESTED_RESPONSE_US},
63 {&congested_reps, CONGESTED_REPS},
64 {&disabled_period, DISABLED_PERIOD},
65 {&giveup_limit, GIVEUP_LIMIT}
66};
67
68static struct dentry *tunables_dir;
69
70/* these correspond to the statistics printed by ptc_seq_show() */
71static char *stat_description[] = {
72 "sent: number of shootdown messages sent",
73 "stime: time spent sending messages",
74 "numuvhubs: number of hubs targeted with shootdown",
75 "numuvhubs16: number times 16 or more hubs targeted",
76 "numuvhubs8: number times 8 or more hubs targeted",
77 "numuvhubs4: number times 4 or more hubs targeted",
78 "numuvhubs2: number times 2 or more hubs targeted",
79 "numuvhubs1: number times 1 hub targeted",
80 "numcpus: number of cpus targeted with shootdown",
81 "dto: number of destination timeouts",
82 "retries: destination timeout retries sent",
83 "rok: : destination timeouts successfully retried",
84 "resetp: ipi-style resource resets for plugs",
85 "resett: ipi-style resource resets for timeouts",
86 "giveup: fall-backs to ipi-style shootdowns",
87 "sto: number of source timeouts",
88 "bz: number of stay-busy's",
89 "throt: number times spun in throttle",
90 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
91 "recv: shootdown messages received",
92 "rtime: time spent processing messages",
93 "all: shootdown all-tlb messages",
94 "one: shootdown one-tlb messages",
95 "mult: interrupts that found multiple messages",
96 "none: interrupts that found no messages",
97 "retry: number of retry messages processed",
98 "canc: number messages canceled by retries",
99 "nocan: number retries that found nothing to cancel",
100 "reset: number of ipi-style reset requests processed",
101 "rcan: number messages canceled by reset requests",
102 "disable: number times use of the BAU was disabled",
103 "enable: number times use of the BAU was re-enabled"
104};
105
106static int __init setup_bau(char *arg)
107{
108 int result;
109
110 if (!arg)
111 return -EINVAL;
112
113 result = strtobool(arg, &nobau);
114 if (result)
115 return result;
116
117 /* we need to flip the logic here, so that bau=y sets nobau to false */
118 nobau = !nobau;
119
120 if (!nobau)
121 pr_info("UV BAU Enabled\n");
122 else
123 pr_info("UV BAU Disabled\n");
124
125 return 0;
126}
127early_param("bau", setup_bau);
128
129/* base pnode in this partition */
130static int uv_base_pnode __read_mostly;
131
132static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
133static DEFINE_PER_CPU(struct bau_control, bau_control);
134static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
135
136static void
137set_bau_on(void)
138{
139 int cpu;
140 struct bau_control *bcp;
141
142 if (nobau_perm) {
143 pr_info("BAU not initialized; cannot be turned on\n");
144 return;
145 }
146 nobau = false;
147 for_each_present_cpu(cpu) {
148 bcp = &per_cpu(bau_control, cpu);
149 bcp->nobau = false;
150 }
151 pr_info("BAU turned on\n");
152 return;
153}
154
155static void
156set_bau_off(void)
157{
158 int cpu;
159 struct bau_control *bcp;
160
161 nobau = true;
162 for_each_present_cpu(cpu) {
163 bcp = &per_cpu(bau_control, cpu);
164 bcp->nobau = true;
165 }
166 pr_info("BAU turned off\n");
167 return;
168}
169
170/*
171 * Determine the first node on a uvhub. 'Nodes' are used for kernel
172 * memory allocation.
173 */
174static int __init uvhub_to_first_node(int uvhub)
175{
176 int node, b;
177
178 for_each_online_node(node) {
179 b = uv_node_to_blade_id(node);
180 if (uvhub == b)
181 return node;
182 }
183 return -1;
184}
185
186/*
187 * Determine the apicid of the first cpu on a uvhub.
188 */
189static int __init uvhub_to_first_apicid(int uvhub)
190{
191 int cpu;
192
193 for_each_present_cpu(cpu)
194 if (uvhub == uv_cpu_to_blade_id(cpu))
195 return per_cpu(x86_cpu_to_apicid, cpu);
196 return -1;
197}
198
199/*
200 * Free a software acknowledge hardware resource by clearing its Pending
201 * bit. This will return a reply to the sender.
202 * If the message has timed out, a reply has already been sent by the
203 * hardware but the resource has not been released. In that case our
204 * clear of the Timeout bit (as well) will free the resource. No reply will
205 * be sent (the hardware will only do one reply per message).
206 */
207static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
208 int do_acknowledge)
209{
210 unsigned long dw;
211 struct bau_pq_entry *msg;
212
213 msg = mdp->msg;
214 if (!msg->canceled && do_acknowledge) {
215 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
216 ops.write_l_sw_ack(dw);
217 }
218 msg->replied_to = 1;
219 msg->swack_vec = 0;
220}
221
222/*
223 * Process the receipt of a RETRY message
224 */
225static void bau_process_retry_msg(struct msg_desc *mdp,
226 struct bau_control *bcp)
227{
228 int i;
229 int cancel_count = 0;
230 unsigned long msg_res;
231 unsigned long mmr = 0;
232 struct bau_pq_entry *msg = mdp->msg;
233 struct bau_pq_entry *msg2;
234 struct ptc_stats *stat = bcp->statp;
235
236 stat->d_retries++;
237 /*
238 * cancel any message from msg+1 to the retry itself
239 */
240 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
241 if (msg2 > mdp->queue_last)
242 msg2 = mdp->queue_first;
243 if (msg2 == msg)
244 break;
245
246 /* same conditions for cancellation as do_reset */
247 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
248 (msg2->swack_vec) && ((msg2->swack_vec &
249 msg->swack_vec) == 0) &&
250 (msg2->sending_cpu == msg->sending_cpu) &&
251 (msg2->msg_type != MSG_NOOP)) {
252 mmr = ops.read_l_sw_ack();
253 msg_res = msg2->swack_vec;
254 /*
255 * This is a message retry; clear the resources held
256 * by the previous message only if they timed out.
257 * If it has not timed out we have an unexpected
258 * situation to report.
259 */
260 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
261 unsigned long mr;
262 /*
263 * Is the resource timed out?
264 * Make everyone ignore the cancelled message.
265 */
266 msg2->canceled = 1;
267 stat->d_canceled++;
268 cancel_count++;
269 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
270 ops.write_l_sw_ack(mr);
271 }
272 }
273 }
274 if (!cancel_count)
275 stat->d_nocanceled++;
276}
277
278/*
279 * Do all the things a cpu should do for a TLB shootdown message.
280 * Other cpu's may come here at the same time for this message.
281 */
282static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
283 int do_acknowledge)
284{
285 short socket_ack_count = 0;
286 short *sp;
287 struct atomic_short *asp;
288 struct ptc_stats *stat = bcp->statp;
289 struct bau_pq_entry *msg = mdp->msg;
290 struct bau_control *smaster = bcp->socket_master;
291
292 /*
293 * This must be a normal message, or retry of a normal message
294 */
295 if (msg->address == TLB_FLUSH_ALL) {
296 local_flush_tlb();
297 stat->d_alltlb++;
298 } else {
299 __flush_tlb_one_user(msg->address);
300 stat->d_onetlb++;
301 }
302 stat->d_requestee++;
303
304 /*
305 * One cpu on each uvhub has the additional job on a RETRY
306 * of releasing the resource held by the message that is
307 * being retried. That message is identified by sending
308 * cpu number.
309 */
310 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
311 bau_process_retry_msg(mdp, bcp);
312
313 /*
314 * This is a swack message, so we have to reply to it.
315 * Count each responding cpu on the socket. This avoids
316 * pinging the count's cache line back and forth between
317 * the sockets.
318 */
319 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
320 asp = (struct atomic_short *)sp;
321 socket_ack_count = atom_asr(1, asp);
322 if (socket_ack_count == bcp->cpus_in_socket) {
323 int msg_ack_count;
324 /*
325 * Both sockets dump their completed count total into
326 * the message's count.
327 */
328 *sp = 0;
329 asp = (struct atomic_short *)&msg->acknowledge_count;
330 msg_ack_count = atom_asr(socket_ack_count, asp);
331
332 if (msg_ack_count == bcp->cpus_in_uvhub) {
333 /*
334 * All cpus in uvhub saw it; reply
335 * (unless we are in the UV2 workaround)
336 */
337 reply_to_message(mdp, bcp, do_acknowledge);
338 }
339 }
340
341 return;
342}
343
344/*
345 * Determine the first cpu on a pnode.
346 */
347static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
348{
349 int cpu;
350 struct hub_and_pnode *hpp;
351
352 for_each_present_cpu(cpu) {
353 hpp = &smaster->thp[cpu];
354 if (pnode == hpp->pnode)
355 return cpu;
356 }
357 return -1;
358}
359
360/*
361 * Last resort when we get a large number of destination timeouts is
362 * to clear resources held by a given cpu.
363 * Do this with IPI so that all messages in the BAU message queue
364 * can be identified by their nonzero swack_vec field.
365 *
366 * This is entered for a single cpu on the uvhub.
367 * The sender want's this uvhub to free a specific message's
368 * swack resources.
369 */
370static void do_reset(void *ptr)
371{
372 int i;
373 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
374 struct reset_args *rap = (struct reset_args *)ptr;
375 struct bau_pq_entry *msg;
376 struct ptc_stats *stat = bcp->statp;
377
378 stat->d_resets++;
379 /*
380 * We're looking for the given sender, and
381 * will free its swack resource.
382 * If all cpu's finally responded after the timeout, its
383 * message 'replied_to' was set.
384 */
385 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
386 unsigned long msg_res;
387 /* do_reset: same conditions for cancellation as
388 bau_process_retry_msg() */
389 if ((msg->replied_to == 0) &&
390 (msg->canceled == 0) &&
391 (msg->sending_cpu == rap->sender) &&
392 (msg->swack_vec) &&
393 (msg->msg_type != MSG_NOOP)) {
394 unsigned long mmr;
395 unsigned long mr;
396 /*
397 * make everyone else ignore this message
398 */
399 msg->canceled = 1;
400 /*
401 * only reset the resource if it is still pending
402 */
403 mmr = ops.read_l_sw_ack();
404 msg_res = msg->swack_vec;
405 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
406 if (mmr & msg_res) {
407 stat->d_rcanceled++;
408 ops.write_l_sw_ack(mr);
409 }
410 }
411 }
412 return;
413}
414
415/*
416 * Use IPI to get all target uvhubs to release resources held by
417 * a given sending cpu number.
418 */
419static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
420{
421 int pnode;
422 int apnode;
423 int maskbits;
424 int sender = bcp->cpu;
425 cpumask_t *mask = bcp->uvhub_master->cpumask;
426 struct bau_control *smaster = bcp->socket_master;
427 struct reset_args reset_args;
428
429 reset_args.sender = sender;
430 cpumask_clear(mask);
431 /* find a single cpu for each uvhub in this distribution mask */
432 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
433 /* each bit is a pnode relative to the partition base pnode */
434 for (pnode = 0; pnode < maskbits; pnode++) {
435 int cpu;
436 if (!bau_uvhub_isset(pnode, distribution))
437 continue;
438 apnode = pnode + bcp->partition_base_pnode;
439 cpu = pnode_to_first_cpu(apnode, smaster);
440 cpumask_set_cpu(cpu, mask);
441 }
442
443 /* IPI all cpus; preemption is already disabled */
444 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
445 return;
446}
447
448/*
449 * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
450 * number, not an absolute. It converts a duration in cycles to a duration in
451 * ns.
452 */
453static inline unsigned long long cycles_2_ns(unsigned long long cyc)
454{
455 struct cyc2ns_data data;
456 unsigned long long ns;
457
458 cyc2ns_read_begin(&data);
459 ns = mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
460 cyc2ns_read_end();
461
462 return ns;
463}
464
465/*
466 * The reverse of the above; converts a duration in ns to a duration in cycles.
467 */
468static inline unsigned long long ns_2_cycles(unsigned long long ns)
469{
470 struct cyc2ns_data data;
471 unsigned long long cyc;
472
473 cyc2ns_read_begin(&data);
474 cyc = (ns << data.cyc2ns_shift) / data.cyc2ns_mul;
475 cyc2ns_read_end();
476
477 return cyc;
478}
479
480static inline unsigned long cycles_2_us(unsigned long long cyc)
481{
482 return cycles_2_ns(cyc) / NSEC_PER_USEC;
483}
484
485static inline cycles_t sec_2_cycles(unsigned long sec)
486{
487 return ns_2_cycles(sec * NSEC_PER_SEC);
488}
489
490static inline unsigned long long usec_2_cycles(unsigned long usec)
491{
492 return ns_2_cycles(usec * NSEC_PER_USEC);
493}
494
495/*
496 * wait for all cpus on this hub to finish their sends and go quiet
497 * leaves uvhub_quiesce set so that no new broadcasts are started by
498 * bau_flush_send_and_wait()
499 */
500static inline void quiesce_local_uvhub(struct bau_control *hmaster)
501{
502 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
503}
504
505/*
506 * mark this quiet-requestor as done
507 */
508static inline void end_uvhub_quiesce(struct bau_control *hmaster)
509{
510 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
511}
512
513static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
514{
515 unsigned long descriptor_status;
516
517 descriptor_status = uv_read_local_mmr(mmr_offset);
518 descriptor_status >>= right_shift;
519 descriptor_status &= UV_ACT_STATUS_MASK;
520 return descriptor_status;
521}
522
523/*
524 * Wait for completion of a broadcast software ack message
525 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
526 */
527static int uv1_wait_completion(struct bau_desc *bau_desc,
528 struct bau_control *bcp, long try)
529{
530 unsigned long descriptor_status;
531 cycles_t ttm;
532 u64 mmr_offset = bcp->status_mmr;
533 int right_shift = bcp->status_index;
534 struct ptc_stats *stat = bcp->statp;
535
536 descriptor_status = uv1_read_status(mmr_offset, right_shift);
537 /* spin on the status MMR, waiting for it to go idle */
538 while ((descriptor_status != DS_IDLE)) {
539 /*
540 * Our software ack messages may be blocked because
541 * there are no swack resources available. As long
542 * as none of them has timed out hardware will NACK
543 * our message and its state will stay IDLE.
544 */
545 if (descriptor_status == DS_SOURCE_TIMEOUT) {
546 stat->s_stimeout++;
547 return FLUSH_GIVEUP;
548 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
549 stat->s_dtimeout++;
550 ttm = get_cycles();
551
552 /*
553 * Our retries may be blocked by all destination
554 * swack resources being consumed, and a timeout
555 * pending. In that case hardware returns the
556 * ERROR that looks like a destination timeout.
557 */
558 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
559 bcp->conseccompletes = 0;
560 return FLUSH_RETRY_PLUGGED;
561 }
562
563 bcp->conseccompletes = 0;
564 return FLUSH_RETRY_TIMEOUT;
565 } else {
566 /*
567 * descriptor_status is still BUSY
568 */
569 cpu_relax();
570 }
571 descriptor_status = uv1_read_status(mmr_offset, right_shift);
572 }
573 bcp->conseccompletes++;
574 return FLUSH_COMPLETE;
575}
576
577/*
578 * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
579 * But not currently used.
580 */
581static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
582{
583 return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
584}
585
586/*
587 * Entered when a bau descriptor has gone into a permanent busy wait because
588 * of a hardware bug.
589 * Workaround the bug.
590 */
591static int handle_uv2_busy(struct bau_control *bcp)
592{
593 struct ptc_stats *stat = bcp->statp;
594
595 stat->s_uv2_wars++;
596 bcp->busy = 1;
597 return FLUSH_GIVEUP;
598}
599
600static int uv2_3_wait_completion(struct bau_desc *bau_desc,
601 struct bau_control *bcp, long try)
602{
603 unsigned long descriptor_stat;
604 cycles_t ttm;
605 u64 mmr_offset = bcp->status_mmr;
606 int right_shift = bcp->status_index;
607 int desc = bcp->uvhub_cpu;
608 long busy_reps = 0;
609 struct ptc_stats *stat = bcp->statp;
610
611 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
612
613 /* spin on the status MMR, waiting for it to go idle */
614 while (descriptor_stat != UV2H_DESC_IDLE) {
615 if (descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) {
616 /*
617 * A h/w bug on the destination side may
618 * have prevented the message being marked
619 * pending, thus it doesn't get replied to
620 * and gets continually nacked until it times
621 * out with a SOURCE_TIMEOUT.
622 */
623 stat->s_stimeout++;
624 return FLUSH_GIVEUP;
625 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
626 ttm = get_cycles();
627
628 /*
629 * Our retries may be blocked by all destination
630 * swack resources being consumed, and a timeout
631 * pending. In that case hardware returns the
632 * ERROR that looks like a destination timeout.
633 * Without using the extended status we have to
634 * deduce from the short time that this was a
635 * strong nack.
636 */
637 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
638 bcp->conseccompletes = 0;
639 stat->s_plugged++;
640 /* FLUSH_RETRY_PLUGGED causes hang on boot */
641 return FLUSH_GIVEUP;
642 }
643 stat->s_dtimeout++;
644 bcp->conseccompletes = 0;
645 /* FLUSH_RETRY_TIMEOUT causes hang on boot */
646 return FLUSH_GIVEUP;
647 } else {
648 busy_reps++;
649 if (busy_reps > 1000000) {
650 /* not to hammer on the clock */
651 busy_reps = 0;
652 ttm = get_cycles();
653 if ((ttm - bcp->send_message) > bcp->timeout_interval)
654 return handle_uv2_busy(bcp);
655 }
656 /*
657 * descriptor_stat is still BUSY
658 */
659 cpu_relax();
660 }
661 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
662 }
663 bcp->conseccompletes++;
664 return FLUSH_COMPLETE;
665}
666
667/*
668 * Returns the status of current BAU message for cpu desc as a bit field
669 * [Error][Busy][Aux]
670 */
671static u64 read_status(u64 status_mmr, int index, int desc)
672{
673 u64 stat;
674
675 stat = ((read_lmmr(status_mmr) >> index) & UV_ACT_STATUS_MASK) << 1;
676 stat |= (read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_2) >> desc) & 0x1;
677
678 return stat;
679}
680
681static int uv4_wait_completion(struct bau_desc *bau_desc,
682 struct bau_control *bcp, long try)
683{
684 struct ptc_stats *stat = bcp->statp;
685 u64 descriptor_stat;
686 u64 mmr = bcp->status_mmr;
687 int index = bcp->status_index;
688 int desc = bcp->uvhub_cpu;
689
690 descriptor_stat = read_status(mmr, index, desc);
691
692 /* spin on the status MMR, waiting for it to go idle */
693 while (descriptor_stat != UV2H_DESC_IDLE) {
694 switch (descriptor_stat) {
695 case UV2H_DESC_SOURCE_TIMEOUT:
696 stat->s_stimeout++;
697 return FLUSH_GIVEUP;
698
699 case UV2H_DESC_DEST_TIMEOUT:
700 stat->s_dtimeout++;
701 bcp->conseccompletes = 0;
702 return FLUSH_RETRY_TIMEOUT;
703
704 case UV2H_DESC_DEST_STRONG_NACK:
705 stat->s_plugged++;
706 bcp->conseccompletes = 0;
707 return FLUSH_RETRY_PLUGGED;
708
709 case UV2H_DESC_DEST_PUT_ERR:
710 bcp->conseccompletes = 0;
711 return FLUSH_GIVEUP;
712
713 default:
714 /* descriptor_stat is still BUSY */
715 cpu_relax();
716 }
717 descriptor_stat = read_status(mmr, index, desc);
718 }
719 bcp->conseccompletes++;
720 return FLUSH_COMPLETE;
721}
722
723/*
724 * Our retries are blocked by all destination sw ack resources being
725 * in use, and a timeout is pending. In that case hardware immediately
726 * returns the ERROR that looks like a destination timeout.
727 */
728static void destination_plugged(struct bau_desc *bau_desc,
729 struct bau_control *bcp,
730 struct bau_control *hmaster, struct ptc_stats *stat)
731{
732 udelay(bcp->plugged_delay);
733 bcp->plugged_tries++;
734
735 if (bcp->plugged_tries >= bcp->plugsb4reset) {
736 bcp->plugged_tries = 0;
737
738 quiesce_local_uvhub(hmaster);
739
740 spin_lock(&hmaster->queue_lock);
741 reset_with_ipi(&bau_desc->distribution, bcp);
742 spin_unlock(&hmaster->queue_lock);
743
744 end_uvhub_quiesce(hmaster);
745
746 bcp->ipi_attempts++;
747 stat->s_resets_plug++;
748 }
749}
750
751static void destination_timeout(struct bau_desc *bau_desc,
752 struct bau_control *bcp, struct bau_control *hmaster,
753 struct ptc_stats *stat)
754{
755 hmaster->max_concurr = 1;
756 bcp->timeout_tries++;
757 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
758 bcp->timeout_tries = 0;
759
760 quiesce_local_uvhub(hmaster);
761
762 spin_lock(&hmaster->queue_lock);
763 reset_with_ipi(&bau_desc->distribution, bcp);
764 spin_unlock(&hmaster->queue_lock);
765
766 end_uvhub_quiesce(hmaster);
767
768 bcp->ipi_attempts++;
769 stat->s_resets_timeout++;
770 }
771}
772
773/*
774 * Stop all cpus on a uvhub from using the BAU for a period of time.
775 * This is reversed by check_enable.
776 */
777static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
778{
779 int tcpu;
780 struct bau_control *tbcp;
781 struct bau_control *hmaster;
782 cycles_t tm1;
783
784 hmaster = bcp->uvhub_master;
785 spin_lock(&hmaster->disable_lock);
786 if (!bcp->baudisabled) {
787 stat->s_bau_disabled++;
788 tm1 = get_cycles();
789 for_each_present_cpu(tcpu) {
790 tbcp = &per_cpu(bau_control, tcpu);
791 if (tbcp->uvhub_master == hmaster) {
792 tbcp->baudisabled = 1;
793 tbcp->set_bau_on_time =
794 tm1 + bcp->disabled_period;
795 }
796 }
797 }
798 spin_unlock(&hmaster->disable_lock);
799}
800
801static void count_max_concurr(int stat, struct bau_control *bcp,
802 struct bau_control *hmaster)
803{
804 bcp->plugged_tries = 0;
805 bcp->timeout_tries = 0;
806 if (stat != FLUSH_COMPLETE)
807 return;
808 if (bcp->conseccompletes <= bcp->complete_threshold)
809 return;
810 if (hmaster->max_concurr >= hmaster->max_concurr_const)
811 return;
812 hmaster->max_concurr++;
813}
814
815static void record_send_stats(cycles_t time1, cycles_t time2,
816 struct bau_control *bcp, struct ptc_stats *stat,
817 int completion_status, int try)
818{
819 cycles_t elapsed;
820
821 if (time2 > time1) {
822 elapsed = time2 - time1;
823 stat->s_time += elapsed;
824
825 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
826 bcp->period_requests++;
827 bcp->period_time += elapsed;
828 if ((elapsed > usec_2_cycles(bcp->cong_response_us)) &&
829 (bcp->period_requests > bcp->cong_reps) &&
830 ((bcp->period_time / bcp->period_requests) >
831 usec_2_cycles(bcp->cong_response_us))) {
832 stat->s_congested++;
833 disable_for_period(bcp, stat);
834 }
835 }
836 } else
837 stat->s_requestor--;
838
839 if (completion_status == FLUSH_COMPLETE && try > 1)
840 stat->s_retriesok++;
841 else if (completion_status == FLUSH_GIVEUP) {
842 stat->s_giveup++;
843 if (get_cycles() > bcp->period_end)
844 bcp->period_giveups = 0;
845 bcp->period_giveups++;
846 if (bcp->period_giveups == 1)
847 bcp->period_end = get_cycles() + bcp->disabled_period;
848 if (bcp->period_giveups > bcp->giveup_limit) {
849 disable_for_period(bcp, stat);
850 stat->s_giveuplimit++;
851 }
852 }
853}
854
855/*
856 * Because of a uv1 hardware bug only a limited number of concurrent
857 * requests can be made.
858 */
859static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
860{
861 spinlock_t *lock = &hmaster->uvhub_lock;
862 atomic_t *v;
863
864 v = &hmaster->active_descriptor_count;
865 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
866 stat->s_throttles++;
867 do {
868 cpu_relax();
869 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
870 }
871}
872
873/*
874 * Handle the completion status of a message send.
875 */
876static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
877 struct bau_control *bcp, struct bau_control *hmaster,
878 struct ptc_stats *stat)
879{
880 if (completion_status == FLUSH_RETRY_PLUGGED)
881 destination_plugged(bau_desc, bcp, hmaster, stat);
882 else if (completion_status == FLUSH_RETRY_TIMEOUT)
883 destination_timeout(bau_desc, bcp, hmaster, stat);
884}
885
886/*
887 * Send a broadcast and wait for it to complete.
888 *
889 * The flush_mask contains the cpus the broadcast is to be sent to including
890 * cpus that are on the local uvhub.
891 *
892 * Returns 0 if all flushing represented in the mask was done.
893 * Returns 1 if it gives up entirely and the original cpu mask is to be
894 * returned to the kernel.
895 */
896static int uv_flush_send_and_wait(struct cpumask *flush_mask,
897 struct bau_control *bcp,
898 struct bau_desc *bau_desc)
899{
900 int seq_number = 0;
901 int completion_stat = 0;
902 int uv1 = 0;
903 long try = 0;
904 unsigned long index;
905 cycles_t time1;
906 cycles_t time2;
907 struct ptc_stats *stat = bcp->statp;
908 struct bau_control *hmaster = bcp->uvhub_master;
909 struct uv1_bau_msg_header *uv1_hdr = NULL;
910 struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
911
912 if (bcp->uvhub_version == UV_BAU_V1) {
913 uv1 = 1;
914 uv1_throttle(hmaster, stat);
915 }
916
917 while (hmaster->uvhub_quiesce)
918 cpu_relax();
919
920 time1 = get_cycles();
921 if (uv1)
922 uv1_hdr = &bau_desc->header.uv1_hdr;
923 else
924 /* uv2 and uv3 */
925 uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
926
927 do {
928 if (try == 0) {
929 if (uv1)
930 uv1_hdr->msg_type = MSG_REGULAR;
931 else
932 uv2_3_hdr->msg_type = MSG_REGULAR;
933 seq_number = bcp->message_number++;
934 } else {
935 if (uv1)
936 uv1_hdr->msg_type = MSG_RETRY;
937 else
938 uv2_3_hdr->msg_type = MSG_RETRY;
939 stat->s_retry_messages++;
940 }
941
942 if (uv1)
943 uv1_hdr->sequence = seq_number;
944 else
945 uv2_3_hdr->sequence = seq_number;
946 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
947 bcp->send_message = get_cycles();
948
949 write_mmr_activation(index);
950
951 try++;
952 completion_stat = ops.wait_completion(bau_desc, bcp, try);
953
954 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
955
956 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
957 bcp->ipi_attempts = 0;
958 stat->s_overipilimit++;
959 completion_stat = FLUSH_GIVEUP;
960 break;
961 }
962 cpu_relax();
963 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
964 (completion_stat == FLUSH_RETRY_TIMEOUT));
965
966 time2 = get_cycles();
967
968 count_max_concurr(completion_stat, bcp, hmaster);
969
970 while (hmaster->uvhub_quiesce)
971 cpu_relax();
972
973 atomic_dec(&hmaster->active_descriptor_count);
974
975 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
976
977 if (completion_stat == FLUSH_GIVEUP)
978 /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
979 return 1;
980 return 0;
981}
982
983/*
984 * The BAU is disabled for this uvhub. When the disabled time period has
985 * expired re-enable it.
986 * Return 0 if it is re-enabled for all cpus on this uvhub.
987 */
988static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
989{
990 int tcpu;
991 struct bau_control *tbcp;
992 struct bau_control *hmaster;
993
994 hmaster = bcp->uvhub_master;
995 spin_lock(&hmaster->disable_lock);
996 if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
997 stat->s_bau_reenabled++;
998 for_each_present_cpu(tcpu) {
999 tbcp = &per_cpu(bau_control, tcpu);
1000 if (tbcp->uvhub_master == hmaster) {
1001 tbcp->baudisabled = 0;
1002 tbcp->period_requests = 0;
1003 tbcp->period_time = 0;
1004 tbcp->period_giveups = 0;
1005 }
1006 }
1007 spin_unlock(&hmaster->disable_lock);
1008 return 0;
1009 }
1010 spin_unlock(&hmaster->disable_lock);
1011 return -1;
1012}
1013
1014static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
1015 int remotes, struct bau_desc *bau_desc)
1016{
1017 stat->s_requestor++;
1018 stat->s_ntargcpu += remotes + locals;
1019 stat->s_ntargremotes += remotes;
1020 stat->s_ntarglocals += locals;
1021
1022 /* uvhub statistics */
1023 hubs = bau_uvhub_weight(&bau_desc->distribution);
1024 if (locals) {
1025 stat->s_ntarglocaluvhub++;
1026 stat->s_ntargremoteuvhub += (hubs - 1);
1027 } else
1028 stat->s_ntargremoteuvhub += hubs;
1029
1030 stat->s_ntarguvhub += hubs;
1031
1032 if (hubs >= 16)
1033 stat->s_ntarguvhub16++;
1034 else if (hubs >= 8)
1035 stat->s_ntarguvhub8++;
1036 else if (hubs >= 4)
1037 stat->s_ntarguvhub4++;
1038 else if (hubs >= 2)
1039 stat->s_ntarguvhub2++;
1040 else
1041 stat->s_ntarguvhub1++;
1042}
1043
1044/*
1045 * Translate a cpu mask to the uvhub distribution mask in the BAU
1046 * activation descriptor.
1047 */
1048static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1049 struct bau_desc *bau_desc, int *localsp, int *remotesp)
1050{
1051 int cpu;
1052 int pnode;
1053 int cnt = 0;
1054 struct hub_and_pnode *hpp;
1055
1056 for_each_cpu(cpu, flush_mask) {
1057 /*
1058 * The distribution vector is a bit map of pnodes, relative
1059 * to the partition base pnode (and the partition base nasid
1060 * in the header).
1061 * Translate cpu to pnode and hub using a local memory array.
1062 */
1063 hpp = &bcp->socket_master->thp[cpu];
1064 pnode = hpp->pnode - bcp->partition_base_pnode;
1065 bau_uvhub_set(pnode, &bau_desc->distribution);
1066 cnt++;
1067 if (hpp->uvhub == bcp->uvhub)
1068 (*localsp)++;
1069 else
1070 (*remotesp)++;
1071 }
1072 if (!cnt)
1073 return 1;
1074 return 0;
1075}
1076
1077/*
1078 * globally purge translation cache of a virtual address or all TLB's
1079 * @cpumask: mask of all cpu's in which the address is to be removed
1080 * @mm: mm_struct containing virtual address range
1081 * @start: start virtual address to be removed from TLB
1082 * @end: end virtual address to be remove from TLB
1083 * @cpu: the current cpu
1084 *
1085 * This is the entry point for initiating any UV global TLB shootdown.
1086 *
1087 * Purges the translation caches of all specified processors of the given
1088 * virtual address, or purges all TLB's on specified processors.
1089 *
1090 * The caller has derived the cpumask from the mm_struct. This function
1091 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1092 *
1093 * The cpumask is converted into a uvhubmask of the uvhubs containing
1094 * those cpus.
1095 *
1096 * Note that this function should be called with preemption disabled.
1097 *
1098 * Returns NULL if all remote flushing was done.
1099 * Returns pointer to cpumask if some remote flushing remains to be
1100 * done. The returned pointer is valid till preemption is re-enabled.
1101 */
1102const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
1103 const struct flush_tlb_info *info)
1104{
1105 unsigned int cpu = smp_processor_id();
1106 int locals = 0, remotes = 0, hubs = 0;
1107 struct bau_desc *bau_desc;
1108 struct cpumask *flush_mask;
1109 struct ptc_stats *stat;
1110 struct bau_control *bcp;
1111 unsigned long descriptor_status, status, address;
1112
1113 bcp = &per_cpu(bau_control, cpu);
1114
1115 if (bcp->nobau)
1116 return cpumask;
1117
1118 stat = bcp->statp;
1119 stat->s_enters++;
1120
1121 if (bcp->busy) {
1122 descriptor_status =
1123 read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1124 status = ((descriptor_status >> (bcp->uvhub_cpu *
1125 UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1126 if (status == UV2H_DESC_BUSY)
1127 return cpumask;
1128 bcp->busy = 0;
1129 }
1130
1131 /* bau was disabled due to slow response */
1132 if (bcp->baudisabled) {
1133 if (check_enable(bcp, stat)) {
1134 stat->s_ipifordisabled++;
1135 return cpumask;
1136 }
1137 }
1138
1139 /*
1140 * Each sending cpu has a per-cpu mask which it fills from the caller's
1141 * cpu mask. All cpus are converted to uvhubs and copied to the
1142 * activation descriptor.
1143 */
1144 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
1145 /* don't actually do a shootdown of the local cpu */
1146 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
1147
1148 if (cpumask_test_cpu(cpu, cpumask))
1149 stat->s_ntargself++;
1150
1151 bau_desc = bcp->descriptor_base;
1152 bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
1153 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
1154 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
1155 return NULL;
1156
1157 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1158
1159 if (!info->end || (info->end - info->start) <= PAGE_SIZE)
1160 address = info->start;
1161 else
1162 address = TLB_FLUSH_ALL;
1163
1164 switch (bcp->uvhub_version) {
1165 case UV_BAU_V1:
1166 case UV_BAU_V2:
1167 case UV_BAU_V3:
1168 bau_desc->payload.uv1_2_3.address = address;
1169 bau_desc->payload.uv1_2_3.sending_cpu = cpu;
1170 break;
1171 case UV_BAU_V4:
1172 bau_desc->payload.uv4.address = address;
1173 bau_desc->payload.uv4.sending_cpu = cpu;
1174 bau_desc->payload.uv4.qualifier = BAU_DESC_QUALIFIER;
1175 break;
1176 }
1177
1178 /*
1179 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1180 * or 1 if it gave up and the original cpumask should be returned.
1181 */
1182 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
1183 return NULL;
1184 else
1185 return cpumask;
1186}
1187
1188/*
1189 * Search the message queue for any 'other' unprocessed message with the
1190 * same software acknowledge resource bit vector as the 'msg' message.
1191 */
1192static struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
1193 struct bau_control *bcp)
1194{
1195 struct bau_pq_entry *msg_next = msg + 1;
1196 unsigned char swack_vec = msg->swack_vec;
1197
1198 if (msg_next > bcp->queue_last)
1199 msg_next = bcp->queue_first;
1200 while (msg_next != msg) {
1201 if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1202 (msg_next->swack_vec == swack_vec))
1203 return msg_next;
1204 msg_next++;
1205 if (msg_next > bcp->queue_last)
1206 msg_next = bcp->queue_first;
1207 }
1208 return NULL;
1209}
1210
1211/*
1212 * UV2 needs to work around a bug in which an arriving message has not
1213 * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1214 * Such a message must be ignored.
1215 */
1216static void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1217{
1218 unsigned long mmr_image;
1219 unsigned char swack_vec;
1220 struct bau_pq_entry *msg = mdp->msg;
1221 struct bau_pq_entry *other_msg;
1222
1223 mmr_image = ops.read_l_sw_ack();
1224 swack_vec = msg->swack_vec;
1225
1226 if ((swack_vec & mmr_image) == 0) {
1227 /*
1228 * This message was assigned a swack resource, but no
1229 * reserved acknowlegment is pending.
1230 * The bug has prevented this message from setting the MMR.
1231 */
1232 /*
1233 * Some message has set the MMR 'pending' bit; it might have
1234 * been another message. Look for that message.
1235 */
1236 other_msg = find_another_by_swack(msg, bcp);
1237 if (other_msg) {
1238 /*
1239 * There is another. Process this one but do not
1240 * ack it.
1241 */
1242 bau_process_message(mdp, bcp, 0);
1243 /*
1244 * Let the natural processing of that other message
1245 * acknowledge it. Don't get the processing of sw_ack's
1246 * out of order.
1247 */
1248 return;
1249 }
1250 }
1251
1252 /*
1253 * Either the MMR shows this one pending a reply or there is no
1254 * other message using this sw_ack, so it is safe to acknowledge it.
1255 */
1256 bau_process_message(mdp, bcp, 1);
1257
1258 return;
1259}
1260
1261/*
1262 * The BAU message interrupt comes here. (registered by set_intr_gate)
1263 * See entry_64.S
1264 *
1265 * We received a broadcast assist message.
1266 *
1267 * Interrupts are disabled; this interrupt could represent
1268 * the receipt of several messages.
1269 *
1270 * All cores/threads on this hub get this interrupt.
1271 * The last one to see it does the software ack.
1272 * (the resource will not be freed until noninterruptable cpus see this
1273 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1274 */
1275void uv_bau_message_interrupt(struct pt_regs *regs)
1276{
1277 int count = 0;
1278 cycles_t time_start;
1279 struct bau_pq_entry *msg;
1280 struct bau_control *bcp;
1281 struct ptc_stats *stat;
1282 struct msg_desc msgdesc;
1283
1284 ack_APIC_irq();
1285 kvm_set_cpu_l1tf_flush_l1d();
1286 time_start = get_cycles();
1287
1288 bcp = &per_cpu(bau_control, smp_processor_id());
1289 stat = bcp->statp;
1290
1291 msgdesc.queue_first = bcp->queue_first;
1292 msgdesc.queue_last = bcp->queue_last;
1293
1294 msg = bcp->bau_msg_head;
1295 while (msg->swack_vec) {
1296 count++;
1297
1298 msgdesc.msg_slot = msg - msgdesc.queue_first;
1299 msgdesc.msg = msg;
1300 if (bcp->uvhub_version == UV_BAU_V2)
1301 process_uv2_message(&msgdesc, bcp);
1302 else
1303 /* no error workaround for uv1 or uv3 */
1304 bau_process_message(&msgdesc, bcp, 1);
1305
1306 msg++;
1307 if (msg > msgdesc.queue_last)
1308 msg = msgdesc.queue_first;
1309 bcp->bau_msg_head = msg;
1310 }
1311 stat->d_time += (get_cycles() - time_start);
1312 if (!count)
1313 stat->d_nomsg++;
1314 else if (count > 1)
1315 stat->d_multmsg++;
1316}
1317
1318/*
1319 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
1320 * shootdown message timeouts enabled. The timeout does not cause
1321 * an interrupt, but causes an error message to be returned to
1322 * the sender.
1323 */
1324static void __init enable_timeouts(void)
1325{
1326 int uvhub;
1327 int nuvhubs;
1328 int pnode;
1329 unsigned long mmr_image;
1330
1331 nuvhubs = uv_num_possible_blades();
1332
1333 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1334 if (!uv_blade_nr_possible_cpus(uvhub))
1335 continue;
1336
1337 pnode = uv_blade_to_pnode(uvhub);
1338 mmr_image = read_mmr_misc_control(pnode);
1339 /*
1340 * Set the timeout period and then lock it in, in three
1341 * steps; captures and locks in the period.
1342 *
1343 * To program the period, the SOFT_ACK_MODE must be off.
1344 */
1345 mmr_image &= ~(1L << SOFTACK_MSHIFT);
1346 write_mmr_misc_control(pnode, mmr_image);
1347 /*
1348 * Set the 4-bit period.
1349 */
1350 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1351 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1352 write_mmr_misc_control(pnode, mmr_image);
1353 /*
1354 * UV1:
1355 * Subsequent reversals of the timebase bit (3) cause an
1356 * immediate timeout of one or all INTD resources as
1357 * indicated in bits 2:0 (7 causes all of them to timeout).
1358 */
1359 mmr_image |= (1L << SOFTACK_MSHIFT);
1360 if (is_uv2_hub()) {
1361 /* do not touch the legacy mode bit */
1362 /* hw bug workaround; do not use extended status */
1363 mmr_image &= ~(1L << UV2_EXT_SHFT);
1364 } else if (is_uv3_hub()) {
1365 mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
1366 mmr_image |= (1L << SB_STATUS_SHFT);
1367 }
1368 write_mmr_misc_control(pnode, mmr_image);
1369 }
1370}
1371
1372static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1373{
1374 if (*offset < num_possible_cpus())
1375 return offset;
1376 return NULL;
1377}
1378
1379static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1380{
1381 (*offset)++;
1382 if (*offset < num_possible_cpus())
1383 return offset;
1384 return NULL;
1385}
1386
1387static void ptc_seq_stop(struct seq_file *file, void *data)
1388{
1389}
1390
1391/*
1392 * Display the statistics thru /proc/sgi_uv/ptc_statistics
1393 * 'data' points to the cpu number
1394 * Note: see the descriptions in stat_description[].
1395 */
1396static int ptc_seq_show(struct seq_file *file, void *data)
1397{
1398 struct ptc_stats *stat;
1399 struct bau_control *bcp;
1400 int cpu;
1401
1402 cpu = *(loff_t *)data;
1403 if (!cpu) {
1404 seq_puts(file,
1405 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
1406 seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1407 seq_puts(file,
1408 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1409 seq_puts(file,
1410 "rok resetp resett giveup sto bz throt disable ");
1411 seq_puts(file,
1412 "enable wars warshw warwaits enters ipidis plugged ");
1413 seq_puts(file,
1414 "ipiover glim cong swack recv rtime all one mult ");
1415 seq_puts(file, "none retry canc nocan reset rcan\n");
1416 }
1417 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
1418 bcp = &per_cpu(bau_control, cpu);
1419 if (bcp->nobau) {
1420 seq_printf(file, "cpu %d bau disabled\n", cpu);
1421 return 0;
1422 }
1423 stat = bcp->statp;
1424 /* source side statistics */
1425 seq_printf(file,
1426 "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1427 cpu, bcp->nobau, stat->s_requestor,
1428 cycles_2_us(stat->s_time),
1429 stat->s_ntargself, stat->s_ntarglocals,
1430 stat->s_ntargremotes, stat->s_ntargcpu,
1431 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1432 stat->s_ntarguvhub, stat->s_ntarguvhub16);
1433 seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
1434 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1435 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
1436 stat->s_dtimeout, stat->s_strongnacks);
1437 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
1438 stat->s_retry_messages, stat->s_retriesok,
1439 stat->s_resets_plug, stat->s_resets_timeout,
1440 stat->s_giveup, stat->s_stimeout,
1441 stat->s_busy, stat->s_throttles);
1442 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1443 stat->s_bau_disabled, stat->s_bau_reenabled,
1444 stat->s_uv2_wars, stat->s_uv2_wars_hw,
1445 stat->s_uv2_war_waits, stat->s_enters,
1446 stat->s_ipifordisabled, stat->s_plugged,
1447 stat->s_overipilimit, stat->s_giveuplimit,
1448 stat->s_congested);
1449
1450 /* destination side statistics */
1451 seq_printf(file,
1452 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
1453 ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)),
1454 stat->d_requestee, cycles_2_us(stat->d_time),
1455 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1456 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1457 stat->d_nocanceled, stat->d_resets,
1458 stat->d_rcanceled);
1459 }
1460 return 0;
1461}
1462
1463/*
1464 * Display the tunables thru debugfs
1465 */
1466static ssize_t tunables_read(struct file *file, char __user *userbuf,
1467 size_t count, loff_t *ppos)
1468{
1469 char *buf;
1470 int ret;
1471
1472 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1473 "max_concur plugged_delay plugsb4reset timeoutsb4reset",
1474 "ipi_reset_limit complete_threshold congested_response_us",
1475 "congested_reps disabled_period giveup_limit",
1476 max_concurr, plugged_delay, plugsb4reset,
1477 timeoutsb4reset, ipi_reset_limit, complete_threshold,
1478 congested_respns_us, congested_reps, disabled_period,
1479 giveup_limit);
1480
1481 if (!buf)
1482 return -ENOMEM;
1483
1484 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1485 kfree(buf);
1486 return ret;
1487}
1488
1489/*
1490 * handle a write to /proc/sgi_uv/ptc_statistics
1491 * -1: reset the statistics
1492 * 0: display meaning of the statistics
1493 */
1494static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1495 size_t count, loff_t *data)
1496{
1497 int cpu;
1498 int i;
1499 int elements;
1500 long input_arg;
1501 char optstr[64];
1502 struct ptc_stats *stat;
1503
1504 if (count == 0 || count > sizeof(optstr))
1505 return -EINVAL;
1506 if (copy_from_user(optstr, user, count))
1507 return -EFAULT;
1508 optstr[count - 1] = '\0';
1509
1510 if (!strcmp(optstr, "on")) {
1511 set_bau_on();
1512 return count;
1513 } else if (!strcmp(optstr, "off")) {
1514 set_bau_off();
1515 return count;
1516 }
1517
1518 if (kstrtol(optstr, 10, &input_arg) < 0) {
1519 pr_debug("%s is invalid\n", optstr);
1520 return -EINVAL;
1521 }
1522
1523 if (input_arg == 0) {
1524 elements = ARRAY_SIZE(stat_description);
1525 pr_debug("# cpu: cpu number\n");
1526 pr_debug("Sender statistics:\n");
1527 for (i = 0; i < elements; i++)
1528 pr_debug("%s\n", stat_description[i]);
1529 } else if (input_arg == -1) {
1530 for_each_present_cpu(cpu) {
1531 stat = &per_cpu(ptcstats, cpu);
1532 memset(stat, 0, sizeof(struct ptc_stats));
1533 }
1534 }
1535
1536 return count;
1537}
1538
1539static int local_atoi(const char *name)
1540{
1541 int val = 0;
1542
1543 for (;; name++) {
1544 switch (*name) {
1545 case '0' ... '9':
1546 val = 10*val+(*name-'0');
1547 break;
1548 default:
1549 return val;
1550 }
1551 }
1552}
1553
1554/*
1555 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1556 * Zero values reset them to defaults.
1557 */
1558static int parse_tunables_write(struct bau_control *bcp, char *instr,
1559 int count)
1560{
1561 char *p;
1562 char *q;
1563 int cnt = 0;
1564 int val;
1565 int e = ARRAY_SIZE(tunables);
1566
1567 p = instr + strspn(instr, WHITESPACE);
1568 q = p;
1569 for (; *p; p = q + strspn(q, WHITESPACE)) {
1570 q = p + strcspn(p, WHITESPACE);
1571 cnt++;
1572 if (q == p)
1573 break;
1574 }
1575 if (cnt != e) {
1576 pr_info("bau tunable error: should be %d values\n", e);
1577 return -EINVAL;
1578 }
1579
1580 p = instr + strspn(instr, WHITESPACE);
1581 q = p;
1582 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1583 q = p + strcspn(p, WHITESPACE);
1584 val = local_atoi(p);
1585 switch (cnt) {
1586 case 0:
1587 if (val == 0) {
1588 max_concurr = MAX_BAU_CONCURRENT;
1589 max_concurr_const = MAX_BAU_CONCURRENT;
1590 continue;
1591 }
1592 if (val < 1 || val > bcp->cpus_in_uvhub) {
1593 pr_debug(
1594 "Error: BAU max concurrent %d is invalid\n",
1595 val);
1596 return -EINVAL;
1597 }
1598 max_concurr = val;
1599 max_concurr_const = val;
1600 continue;
1601 default:
1602 if (val == 0)
1603 *tunables[cnt].tunp = tunables[cnt].deflt;
1604 else
1605 *tunables[cnt].tunp = val;
1606 continue;
1607 }
1608 }
1609 return 0;
1610}
1611
1612/*
1613 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1614 */
1615static ssize_t tunables_write(struct file *file, const char __user *user,
1616 size_t count, loff_t *data)
1617{
1618 int cpu;
1619 int ret;
1620 char instr[100];
1621 struct bau_control *bcp;
1622
1623 if (count == 0 || count > sizeof(instr)-1)
1624 return -EINVAL;
1625 if (copy_from_user(instr, user, count))
1626 return -EFAULT;
1627
1628 instr[count] = '\0';
1629
1630 cpu = get_cpu();
1631 bcp = &per_cpu(bau_control, cpu);
1632 ret = parse_tunables_write(bcp, instr, count);
1633 put_cpu();
1634 if (ret)
1635 return ret;
1636
1637 for_each_present_cpu(cpu) {
1638 bcp = &per_cpu(bau_control, cpu);
1639 bcp->max_concurr = max_concurr;
1640 bcp->max_concurr_const = max_concurr;
1641 bcp->plugged_delay = plugged_delay;
1642 bcp->plugsb4reset = plugsb4reset;
1643 bcp->timeoutsb4reset = timeoutsb4reset;
1644 bcp->ipi_reset_limit = ipi_reset_limit;
1645 bcp->complete_threshold = complete_threshold;
1646 bcp->cong_response_us = congested_respns_us;
1647 bcp->cong_reps = congested_reps;
1648 bcp->disabled_period = sec_2_cycles(disabled_period);
1649 bcp->giveup_limit = giveup_limit;
1650 }
1651 return count;
1652}
1653
1654static const struct seq_operations uv_ptc_seq_ops = {
1655 .start = ptc_seq_start,
1656 .next = ptc_seq_next,
1657 .stop = ptc_seq_stop,
1658 .show = ptc_seq_show
1659};
1660
1661static int ptc_proc_open(struct inode *inode, struct file *file)
1662{
1663 return seq_open(file, &uv_ptc_seq_ops);
1664}
1665
1666static int tunables_open(struct inode *inode, struct file *file)
1667{
1668 return 0;
1669}
1670
1671static const struct file_operations proc_uv_ptc_operations = {
1672 .open = ptc_proc_open,
1673 .read = seq_read,
1674 .write = ptc_proc_write,
1675 .llseek = seq_lseek,
1676 .release = seq_release,
1677};
1678
1679static const struct file_operations tunables_fops = {
1680 .open = tunables_open,
1681 .read = tunables_read,
1682 .write = tunables_write,
1683 .llseek = default_llseek,
1684};
1685
1686static int __init uv_ptc_init(void)
1687{
1688 struct proc_dir_entry *proc_uv_ptc;
1689
1690 if (!is_uv_system())
1691 return 0;
1692
1693 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1694 &proc_uv_ptc_operations);
1695 if (!proc_uv_ptc) {
1696 pr_err("unable to create %s proc entry\n",
1697 UV_PTC_BASENAME);
1698 return -EINVAL;
1699 }
1700
1701 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1702 debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, tunables_dir, NULL,
1703 &tunables_fops);
1704 return 0;
1705}
1706
1707/*
1708 * Initialize the sending side's sending buffers.
1709 */
1710static void activation_descriptor_init(int node, int pnode, int base_pnode)
1711{
1712 int i;
1713 int cpu;
1714 int uv1 = 0;
1715 unsigned long gpa;
1716 unsigned long m;
1717 unsigned long n;
1718 size_t dsize;
1719 struct bau_desc *bau_desc;
1720 struct bau_desc *bd2;
1721 struct uv1_bau_msg_header *uv1_hdr;
1722 struct uv2_3_bau_msg_header *uv2_3_hdr;
1723 struct bau_control *bcp;
1724
1725 /*
1726 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1727 * per cpu; and one per cpu on the uvhub (ADP_SZ)
1728 */
1729 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1730 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
1731 BUG_ON(!bau_desc);
1732
1733 gpa = uv_gpa(bau_desc);
1734 n = uv_gpa_to_gnode(gpa);
1735 m = ops.bau_gpa_to_offset(gpa);
1736 if (is_uv1_hub())
1737 uv1 = 1;
1738
1739 /* the 14-bit pnode */
1740 write_mmr_descriptor_base(pnode,
1741 (n << UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT | m));
1742 /*
1743 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
1744 * cpu even though we only use the first one; one descriptor can
1745 * describe a broadcast to 256 uv hubs.
1746 */
1747 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
1748 memset(bd2, 0, sizeof(struct bau_desc));
1749 if (uv1) {
1750 uv1_hdr = &bd2->header.uv1_hdr;
1751 uv1_hdr->swack_flag = 1;
1752 /*
1753 * The base_dest_nasid set in the message header
1754 * is the nasid of the first uvhub in the partition.
1755 * The bit map will indicate destination pnode numbers
1756 * relative to that base. They may not be consecutive
1757 * if nasid striding is being used.
1758 */
1759 uv1_hdr->base_dest_nasid =
1760 UV_PNODE_TO_NASID(base_pnode);
1761 uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1762 uv1_hdr->command = UV_NET_ENDPOINT_INTD;
1763 uv1_hdr->int_both = 1;
1764 /*
1765 * all others need to be set to zero:
1766 * fairness chaining multilevel count replied_to
1767 */
1768 } else {
1769 /*
1770 * BIOS uses legacy mode, but uv2 and uv3 hardware always
1771 * uses native mode for selective broadcasts.
1772 */
1773 uv2_3_hdr = &bd2->header.uv2_3_hdr;
1774 uv2_3_hdr->swack_flag = 1;
1775 uv2_3_hdr->base_dest_nasid =
1776 UV_PNODE_TO_NASID(base_pnode);
1777 uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1778 uv2_3_hdr->command = UV_NET_ENDPOINT_INTD;
1779 }
1780 }
1781 for_each_present_cpu(cpu) {
1782 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1783 continue;
1784 bcp = &per_cpu(bau_control, cpu);
1785 bcp->descriptor_base = bau_desc;
1786 }
1787}
1788
1789/*
1790 * initialize the destination side's receiving buffers
1791 * entered for each uvhub in the partition
1792 * - node is first node (kernel memory notion) on the uvhub
1793 * - pnode is the uvhub's physical identifier
1794 */
1795static void pq_init(int node, int pnode)
1796{
1797 int cpu;
1798 size_t plsize;
1799 char *cp;
1800 void *vp;
1801 unsigned long gnode, first, last, tail;
1802 struct bau_pq_entry *pqp;
1803 struct bau_control *bcp;
1804
1805 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1806 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1807 BUG_ON(!vp);
1808
1809 pqp = (struct bau_pq_entry *)vp;
1810 cp = (char *)pqp + 31;
1811 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
1812
1813 for_each_present_cpu(cpu) {
1814 if (pnode != uv_cpu_to_pnode(cpu))
1815 continue;
1816 /* for every cpu on this pnode: */
1817 bcp = &per_cpu(bau_control, cpu);
1818 bcp->queue_first = pqp;
1819 bcp->bau_msg_head = pqp;
1820 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
1821 }
1822
1823 first = ops.bau_gpa_to_offset(uv_gpa(pqp));
1824 last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1)));
1825
1826 /*
1827 * Pre UV4, the gnode is required to locate the payload queue
1828 * and the payload queue tail must be maintained by the kernel.
1829 */
1830 bcp = &per_cpu(bau_control, smp_processor_id());
1831 if (bcp->uvhub_version <= UV_BAU_V3) {
1832 tail = first;
1833 gnode = uv_gpa_to_gnode(uv_gpa(pqp));
1834 first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail;
1835 write_mmr_payload_tail(pnode, tail);
1836 }
1837
1838 ops.write_payload_first(pnode, first);
1839 ops.write_payload_last(pnode, last);
1840
1841 /* in effect, all msg_type's are set to MSG_NOOP */
1842 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
1843}
1844
1845/*
1846 * Initialization of each UV hub's structures
1847 */
1848static void __init init_uvhub(int uvhub, int vector, int base_pnode)
1849{
1850 int node;
1851 int pnode;
1852 unsigned long apicid;
1853
1854 node = uvhub_to_first_node(uvhub);
1855 pnode = uv_blade_to_pnode(uvhub);
1856
1857 activation_descriptor_init(node, pnode, base_pnode);
1858
1859 pq_init(node, pnode);
1860 /*
1861 * The below initialization can't be in firmware because the
1862 * messaging IRQ will be determined by the OS.
1863 */
1864 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1865 write_mmr_data_config(pnode, ((apicid << 32) | vector));
1866}
1867
1868/*
1869 * We will set BAU_MISC_CONTROL with a timeout period.
1870 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1871 * So the destination timeout period has to be calculated from them.
1872 */
1873static int calculate_destination_timeout(void)
1874{
1875 unsigned long mmr_image;
1876 int mult1;
1877 int mult2;
1878 int index;
1879 int base;
1880 int ret;
1881 unsigned long ts_ns;
1882
1883 if (is_uv1_hub()) {
1884 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
1885 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1886 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1887 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1888 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1889 ts_ns = timeout_base_ns[index];
1890 ts_ns *= (mult1 * mult2);
1891 ret = ts_ns / 1000;
1892 } else {
1893 /* same destination timeout for uv2 and uv3 */
1894 /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
1895 mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
1896 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1897 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
1898 base = 80;
1899 else
1900 base = 10;
1901 mult1 = mmr_image & UV2_ACK_MASK;
1902 ret = mult1 * base;
1903 }
1904 return ret;
1905}
1906
1907static void __init init_per_cpu_tunables(void)
1908{
1909 int cpu;
1910 struct bau_control *bcp;
1911
1912 for_each_present_cpu(cpu) {
1913 bcp = &per_cpu(bau_control, cpu);
1914 bcp->baudisabled = 0;
1915 if (nobau)
1916 bcp->nobau = true;
1917 bcp->statp = &per_cpu(ptcstats, cpu);
1918 /* time interval to catch a hardware stay-busy bug */
1919 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1920 bcp->max_concurr = max_concurr;
1921 bcp->max_concurr_const = max_concurr;
1922 bcp->plugged_delay = plugged_delay;
1923 bcp->plugsb4reset = plugsb4reset;
1924 bcp->timeoutsb4reset = timeoutsb4reset;
1925 bcp->ipi_reset_limit = ipi_reset_limit;
1926 bcp->complete_threshold = complete_threshold;
1927 bcp->cong_response_us = congested_respns_us;
1928 bcp->cong_reps = congested_reps;
1929 bcp->disabled_period = sec_2_cycles(disabled_period);
1930 bcp->giveup_limit = giveup_limit;
1931 spin_lock_init(&bcp->queue_lock);
1932 spin_lock_init(&bcp->uvhub_lock);
1933 spin_lock_init(&bcp->disable_lock);
1934 }
1935}
1936
1937/*
1938 * Scan all cpus to collect blade and socket summaries.
1939 */
1940static int __init get_cpu_topology(int base_pnode,
1941 struct uvhub_desc *uvhub_descs,
1942 unsigned char *uvhub_mask)
1943{
1944 int cpu;
1945 int pnode;
1946 int uvhub;
1947 int socket;
1948 struct bau_control *bcp;
1949 struct uvhub_desc *bdp;
1950 struct socket_desc *sdp;
1951
1952 for_each_present_cpu(cpu) {
1953 bcp = &per_cpu(bau_control, cpu);
1954
1955 memset(bcp, 0, sizeof(struct bau_control));
1956
1957 pnode = uv_cpu_hub_info(cpu)->pnode;
1958 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
1959 pr_emerg(
1960 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1961 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
1962 return 1;
1963 }
1964
1965 bcp->osnode = cpu_to_node(cpu);
1966 bcp->partition_base_pnode = base_pnode;
1967
1968 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1969 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1970 bdp = &uvhub_descs[uvhub];
1971
1972 bdp->num_cpus++;
1973 bdp->uvhub = uvhub;
1974 bdp->pnode = pnode;
1975
1976 /* kludge: 'assuming' one node per socket, and assuming that
1977 disabling a socket just leaves a gap in node numbers */
1978 socket = bcp->osnode & 1;
1979 bdp->socket_mask |= (1 << socket);
1980 sdp = &bdp->socket[socket];
1981 sdp->cpu_number[sdp->num_cpus] = cpu;
1982 sdp->num_cpus++;
1983 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1984 pr_emerg("%d cpus per socket invalid\n",
1985 sdp->num_cpus);
1986 return 1;
1987 }
1988 }
1989 return 0;
1990}
1991
1992/*
1993 * Each socket is to get a local array of pnodes/hubs.
1994 */
1995static void make_per_cpu_thp(struct bau_control *smaster)
1996{
1997 int cpu;
1998 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
1999
2000 smaster->thp = kzalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
2001 for_each_present_cpu(cpu) {
2002 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
2003 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
2004 }
2005}
2006
2007/*
2008 * Each uvhub is to get a local cpumask.
2009 */
2010static void make_per_hub_cpumask(struct bau_control *hmaster)
2011{
2012 int sz = sizeof(cpumask_t);
2013
2014 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
2015}
2016
2017/*
2018 * Initialize all the per_cpu information for the cpu's on a given socket,
2019 * given what has been gathered into the socket_desc struct.
2020 * And reports the chosen hub and socket masters back to the caller.
2021 */
2022static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
2023 struct bau_control **smasterp,
2024 struct bau_control **hmasterp)
2025{
2026 int i, cpu, uvhub_cpu;
2027 struct bau_control *bcp;
2028
2029 for (i = 0; i < sdp->num_cpus; i++) {
2030 cpu = sdp->cpu_number[i];
2031 bcp = &per_cpu(bau_control, cpu);
2032 bcp->cpu = cpu;
2033 if (i == 0) {
2034 *smasterp = bcp;
2035 if (!(*hmasterp))
2036 *hmasterp = bcp;
2037 }
2038 bcp->cpus_in_uvhub = bdp->num_cpus;
2039 bcp->cpus_in_socket = sdp->num_cpus;
2040 bcp->socket_master = *smasterp;
2041 bcp->uvhub = bdp->uvhub;
2042 if (is_uv1_hub())
2043 bcp->uvhub_version = UV_BAU_V1;
2044 else if (is_uv2_hub())
2045 bcp->uvhub_version = UV_BAU_V2;
2046 else if (is_uv3_hub())
2047 bcp->uvhub_version = UV_BAU_V3;
2048 else if (is_uv4_hub())
2049 bcp->uvhub_version = UV_BAU_V4;
2050 else {
2051 pr_emerg("uvhub version not 1, 2, 3, or 4\n");
2052 return 1;
2053 }
2054 bcp->uvhub_master = *hmasterp;
2055 uvhub_cpu = uv_cpu_blade_processor_id(cpu);
2056 bcp->uvhub_cpu = uvhub_cpu;
2057
2058 /*
2059 * The ERROR and BUSY status registers are located pairwise over
2060 * the STATUS_0 and STATUS_1 mmrs; each an array[32] of 2 bits.
2061 */
2062 if (uvhub_cpu < UV_CPUS_PER_AS) {
2063 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
2064 bcp->status_index = uvhub_cpu * UV_ACT_STATUS_SIZE;
2065 } else {
2066 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
2067 bcp->status_index = (uvhub_cpu - UV_CPUS_PER_AS)
2068 * UV_ACT_STATUS_SIZE;
2069 }
2070
2071 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2072 pr_emerg("%d cpus per uvhub invalid\n",
2073 bcp->uvhub_cpu);
2074 return 1;
2075 }
2076 }
2077 return 0;
2078}
2079
2080/*
2081 * Summarize the blade and socket topology into the per_cpu structures.
2082 */
2083static int __init summarize_uvhub_sockets(int nuvhubs,
2084 struct uvhub_desc *uvhub_descs,
2085 unsigned char *uvhub_mask)
2086{
2087 int socket;
2088 int uvhub;
2089 unsigned short socket_mask;
2090
2091 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2092 struct uvhub_desc *bdp;
2093 struct bau_control *smaster = NULL;
2094 struct bau_control *hmaster = NULL;
2095
2096 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2097 continue;
2098
2099 bdp = &uvhub_descs[uvhub];
2100 socket_mask = bdp->socket_mask;
2101 socket = 0;
2102 while (socket_mask) {
2103 struct socket_desc *sdp;
2104 if ((socket_mask & 1)) {
2105 sdp = &bdp->socket[socket];
2106 if (scan_sock(sdp, bdp, &smaster, &hmaster))
2107 return 1;
2108 make_per_cpu_thp(smaster);
2109 }
2110 socket++;
2111 socket_mask = (socket_mask >> 1);
2112 }
2113 make_per_hub_cpumask(hmaster);
2114 }
2115 return 0;
2116}
2117
2118/*
2119 * initialize the bau_control structure for each cpu
2120 */
2121static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2122{
2123 struct uvhub_desc *uvhub_descs;
2124 unsigned char *uvhub_mask = NULL;
2125
2126 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2127 timeout_us = calculate_destination_timeout();
2128
2129 uvhub_descs = kcalloc(nuvhubs, sizeof(struct uvhub_desc), GFP_KERNEL);
2130 if (!uvhub_descs)
2131 goto fail;
2132
2133 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2134 if (!uvhub_mask)
2135 goto fail;
2136
2137 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
2138 goto fail;
2139
2140 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
2141 goto fail;
2142
2143 kfree(uvhub_descs);
2144 kfree(uvhub_mask);
2145 init_per_cpu_tunables();
2146 return 0;
2147
2148fail:
2149 kfree(uvhub_descs);
2150 kfree(uvhub_mask);
2151 return 1;
2152}
2153
2154static const struct bau_operations uv1_bau_ops __initconst = {
2155 .bau_gpa_to_offset = uv_gpa_to_offset,
2156 .read_l_sw_ack = read_mmr_sw_ack,
2157 .read_g_sw_ack = read_gmmr_sw_ack,
2158 .write_l_sw_ack = write_mmr_sw_ack,
2159 .write_g_sw_ack = write_gmmr_sw_ack,
2160 .write_payload_first = write_mmr_payload_first,
2161 .write_payload_last = write_mmr_payload_last,
2162 .wait_completion = uv1_wait_completion,
2163};
2164
2165static const struct bau_operations uv2_3_bau_ops __initconst = {
2166 .bau_gpa_to_offset = uv_gpa_to_offset,
2167 .read_l_sw_ack = read_mmr_sw_ack,
2168 .read_g_sw_ack = read_gmmr_sw_ack,
2169 .write_l_sw_ack = write_mmr_sw_ack,
2170 .write_g_sw_ack = write_gmmr_sw_ack,
2171 .write_payload_first = write_mmr_payload_first,
2172 .write_payload_last = write_mmr_payload_last,
2173 .wait_completion = uv2_3_wait_completion,
2174};
2175
2176static const struct bau_operations uv4_bau_ops __initconst = {
2177 .bau_gpa_to_offset = uv_gpa_to_soc_phys_ram,
2178 .read_l_sw_ack = read_mmr_proc_sw_ack,
2179 .read_g_sw_ack = read_gmmr_proc_sw_ack,
2180 .write_l_sw_ack = write_mmr_proc_sw_ack,
2181 .write_g_sw_ack = write_gmmr_proc_sw_ack,
2182 .write_payload_first = write_mmr_proc_payload_first,
2183 .write_payload_last = write_mmr_proc_payload_last,
2184 .wait_completion = uv4_wait_completion,
2185};
2186
2187/*
2188 * Initialization of BAU-related structures
2189 */
2190static int __init uv_bau_init(void)
2191{
2192 int uvhub;
2193 int pnode;
2194 int nuvhubs;
2195 int cur_cpu;
2196 int cpus;
2197 int vector;
2198 cpumask_var_t *mask;
2199
2200 if (!is_uv_system())
2201 return 0;
2202
2203 if (is_uv4_hub())
2204 ops = uv4_bau_ops;
2205 else if (is_uv3_hub())
2206 ops = uv2_3_bau_ops;
2207 else if (is_uv2_hub())
2208 ops = uv2_3_bau_ops;
2209 else if (is_uv1_hub())
2210 ops = uv1_bau_ops;
2211
2212 nuvhubs = uv_num_possible_blades();
2213 if (nuvhubs < 2) {
2214 pr_crit("UV: BAU disabled - insufficient hub count\n");
2215 goto err_bau_disable;
2216 }
2217
2218 for_each_possible_cpu(cur_cpu) {
2219 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2220 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2221 }
2222
2223 uv_base_pnode = 0x7fffffff;
2224 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2225 cpus = uv_blade_nr_possible_cpus(uvhub);
2226 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2227 uv_base_pnode = uv_blade_to_pnode(uvhub);
2228 }
2229
2230 /* software timeouts are not supported on UV4 */
2231 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2232 enable_timeouts();
2233
2234 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
2235 pr_crit("UV: BAU disabled - per CPU init failed\n");
2236 goto err_bau_disable;
2237 }
2238
2239 vector = UV_BAU_MESSAGE;
2240 for_each_possible_blade(uvhub) {
2241 if (uv_blade_nr_possible_cpus(uvhub))
2242 init_uvhub(uvhub, vector, uv_base_pnode);
2243 }
2244
2245 for_each_possible_blade(uvhub) {
2246 if (uv_blade_nr_possible_cpus(uvhub)) {
2247 unsigned long val;
2248 unsigned long mmr;
2249 pnode = uv_blade_to_pnode(uvhub);
2250 /* INIT the bau */
2251 val = 1L << 63;
2252 write_gmmr_activation(pnode, val);
2253 mmr = 1; /* should be 1 to broadcast to both sockets */
2254 if (!is_uv1_hub())
2255 write_mmr_data_broadcast(pnode, mmr);
2256 }
2257 }
2258
2259 return 0;
2260
2261err_bau_disable:
2262
2263 for_each_possible_cpu(cur_cpu)
2264 free_cpumask_var(per_cpu(uv_flush_tlb_mask, cur_cpu));
2265
2266 set_bau_off();
2267 nobau_perm = 1;
2268
2269 return -EINVAL;
2270}
2271core_initcall(uv_bau_init);
2272fs_initcall(uv_ptc_init);