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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/mce.h>
7#include <asm/pvclock.h>
8#include "kvm_cache_regs.h"
9#include "kvm_emulate.h"
10
11struct kvm_caps {
12 /* control of guest tsc rate supported? */
13 bool has_tsc_control;
14 /* maximum supported tsc_khz for guests */
15 u32 max_guest_tsc_khz;
16 /* number of bits of the fractional part of the TSC scaling ratio */
17 u8 tsc_scaling_ratio_frac_bits;
18 /* maximum allowed value of TSC scaling ratio */
19 u64 max_tsc_scaling_ratio;
20 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */
21 u64 default_tsc_scaling_ratio;
22 /* bus lock detection supported? */
23 bool has_bus_lock_exit;
24 /* notify VM exit supported? */
25 bool has_notify_vmexit;
26
27 u64 supported_mce_cap;
28 u64 supported_xcr0;
29 u64 supported_xss;
30 u64 supported_perf_cap;
31};
32
33void kvm_spurious_fault(void);
34
35#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
36({ \
37 bool failed = (consistency_check); \
38 if (failed) \
39 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
40 failed; \
41})
42
43#define KVM_DEFAULT_PLE_GAP 128
44#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
45#define KVM_DEFAULT_PLE_WINDOW_GROW 2
46#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
47#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
48#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
49#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
50
51static inline unsigned int __grow_ple_window(unsigned int val,
52 unsigned int base, unsigned int modifier, unsigned int max)
53{
54 u64 ret = val;
55
56 if (modifier < 1)
57 return base;
58
59 if (modifier < base)
60 ret *= modifier;
61 else
62 ret += modifier;
63
64 return min(ret, (u64)max);
65}
66
67static inline unsigned int __shrink_ple_window(unsigned int val,
68 unsigned int base, unsigned int modifier, unsigned int min)
69{
70 if (modifier < 1)
71 return base;
72
73 if (modifier < base)
74 val /= modifier;
75 else
76 val -= modifier;
77
78 return max(val, min);
79}
80
81#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
82
83void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
84int kvm_check_nested_events(struct kvm_vcpu *vcpu);
85
86static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu)
87{
88 return vcpu->arch.exception.pending ||
89 vcpu->arch.exception_vmexit.pending ||
90 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
91}
92
93static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
94{
95 vcpu->arch.exception.pending = false;
96 vcpu->arch.exception.injected = false;
97 vcpu->arch.exception_vmexit.pending = false;
98}
99
100static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
101 bool soft)
102{
103 vcpu->arch.interrupt.injected = true;
104 vcpu->arch.interrupt.soft = soft;
105 vcpu->arch.interrupt.nr = vector;
106}
107
108static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
109{
110 vcpu->arch.interrupt.injected = false;
111}
112
113static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
114{
115 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
116 vcpu->arch.nmi_injected;
117}
118
119static inline bool kvm_exception_is_soft(unsigned int nr)
120{
121 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
122}
123
124static inline bool is_protmode(struct kvm_vcpu *vcpu)
125{
126 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
127}
128
129static inline int is_long_mode(struct kvm_vcpu *vcpu)
130{
131#ifdef CONFIG_X86_64
132 return vcpu->arch.efer & EFER_LMA;
133#else
134 return 0;
135#endif
136}
137
138static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
139{
140 int cs_db, cs_l;
141
142 WARN_ON_ONCE(vcpu->arch.guest_state_protected);
143
144 if (!is_long_mode(vcpu))
145 return false;
146 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
147 return cs_l;
148}
149
150static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
151{
152 /*
153 * If running with protected guest state, the CS register is not
154 * accessible. The hypercall register values will have had to been
155 * provided in 64-bit mode, so assume the guest is in 64-bit.
156 */
157 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
158}
159
160static inline bool x86_exception_has_error_code(unsigned int vector)
161{
162 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
163 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
164 BIT(PF_VECTOR) | BIT(AC_VECTOR);
165
166 return (1U << vector) & exception_has_error_code;
167}
168
169static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
170{
171 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
172}
173
174static inline int is_pae(struct kvm_vcpu *vcpu)
175{
176 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
177}
178
179static inline int is_pse(struct kvm_vcpu *vcpu)
180{
181 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
182}
183
184static inline int is_paging(struct kvm_vcpu *vcpu)
185{
186 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
187}
188
189static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
190{
191 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
192}
193
194static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
195{
196 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
197}
198
199static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
200{
201 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
202}
203
204static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
205 gva_t gva, gfn_t gfn, unsigned access)
206{
207 u64 gen = kvm_memslots(vcpu->kvm)->generation;
208
209 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
210 return;
211
212 /*
213 * If this is a shadow nested page table, the "GVA" is
214 * actually a nGPA.
215 */
216 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
217 vcpu->arch.mmio_access = access;
218 vcpu->arch.mmio_gfn = gfn;
219 vcpu->arch.mmio_gen = gen;
220}
221
222static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
223{
224 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
225}
226
227/*
228 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
229 * clear all mmio cache info.
230 */
231#define MMIO_GVA_ANY (~(gva_t)0)
232
233static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
234{
235 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
236 return;
237
238 vcpu->arch.mmio_gva = 0;
239}
240
241static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
242{
243 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
244 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
245 return true;
246
247 return false;
248}
249
250static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
251{
252 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
253 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
254 return true;
255
256 return false;
257}
258
259static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
260{
261 unsigned long val = kvm_register_read_raw(vcpu, reg);
262
263 return is_64_bit_mode(vcpu) ? val : (u32)val;
264}
265
266static inline void kvm_register_write(struct kvm_vcpu *vcpu,
267 int reg, unsigned long val)
268{
269 if (!is_64_bit_mode(vcpu))
270 val = (u32)val;
271 return kvm_register_write_raw(vcpu, reg, val);
272}
273
274static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
275{
276 return !(kvm->arch.disabled_quirks & quirk);
277}
278
279void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
280
281u64 get_kvmclock_ns(struct kvm *kvm);
282
283int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
284 gva_t addr, void *val, unsigned int bytes,
285 struct x86_exception *exception);
286
287int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
288 gva_t addr, void *val, unsigned int bytes,
289 struct x86_exception *exception);
290
291int handle_ud(struct kvm_vcpu *vcpu);
292
293void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
294 struct kvm_queued_exception *ex);
295
296void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
297u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
298bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
299int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
300int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
301bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
302 int page_num);
303bool kvm_vector_hashing_enabled(void);
304void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
305int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
306 void *insn, int insn_len);
307int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
308 int emulation_type, void *insn, int insn_len);
309fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
310
311extern u64 host_xcr0;
312extern u64 host_xss;
313
314extern struct kvm_caps kvm_caps;
315
316extern bool enable_pmu;
317
318static inline bool kvm_mpx_supported(void)
319{
320 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
321 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
322}
323
324extern unsigned int min_timer_period_us;
325
326extern bool enable_vmware_backdoor;
327
328extern int pi_inject_timer;
329
330extern bool report_ignored_msrs;
331
332extern bool eager_page_split;
333
334static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
335{
336 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
337 vcpu->arch.virtual_tsc_shift);
338}
339
340/* Same "calling convention" as do_div:
341 * - divide (n << 32) by base
342 * - put result in n
343 * - return remainder
344 */
345#define do_shl32_div32(n, base) \
346 ({ \
347 u32 __quot, __rem; \
348 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
349 : "rm" (base), "0" (0), "1" ((u32) n)); \
350 n = __quot; \
351 __rem; \
352 })
353
354static inline bool kvm_mwait_in_guest(struct kvm *kvm)
355{
356 return kvm->arch.mwait_in_guest;
357}
358
359static inline bool kvm_hlt_in_guest(struct kvm *kvm)
360{
361 return kvm->arch.hlt_in_guest;
362}
363
364static inline bool kvm_pause_in_guest(struct kvm *kvm)
365{
366 return kvm->arch.pause_in_guest;
367}
368
369static inline bool kvm_cstate_in_guest(struct kvm *kvm)
370{
371 return kvm->arch.cstate_in_guest;
372}
373
374static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
375{
376 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
377}
378
379enum kvm_intr_type {
380 /* Values are arbitrary, but must be non-zero. */
381 KVM_HANDLING_IRQ = 1,
382 KVM_HANDLING_NMI,
383};
384
385static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
386 enum kvm_intr_type intr)
387{
388 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
389}
390
391static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
392{
393 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
394}
395
396static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
397{
398 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
399}
400
401static inline bool kvm_pat_valid(u64 data)
402{
403 if (data & 0xF8F8F8F8F8F8F8F8ull)
404 return false;
405 /* 0, 1, 4, 5, 6, 7 are valid values. */
406 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
407}
408
409static inline bool kvm_dr7_valid(u64 data)
410{
411 /* Bits [63:32] are reserved */
412 return !(data >> 32);
413}
414static inline bool kvm_dr6_valid(u64 data)
415{
416 /* Bits [63:32] are reserved */
417 return !(data >> 32);
418}
419
420/*
421 * Trigger machine check on the host. We assume all the MSRs are already set up
422 * by the CPU and that we still run on the same CPU as the MCE occurred on.
423 * We pass a fake environment to the machine check handler because we want
424 * the guest to be always treated like user space, no matter what context
425 * it used internally.
426 */
427static inline void kvm_machine_check(void)
428{
429#if defined(CONFIG_X86_MCE)
430 struct pt_regs regs = {
431 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
432 .flags = X86_EFLAGS_IF,
433 };
434
435 do_machine_check(®s);
436#endif
437}
438
439void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
440void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
441int kvm_spec_ctrl_test_value(u64 value);
442bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
443int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
444 struct x86_exception *e);
445int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
446bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
447
448/*
449 * Internal error codes that are used to indicate that MSR emulation encountered
450 * an error that should result in #GP in the guest, unless userspace
451 * handles it.
452 */
453#define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
454#define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
455
456#define __cr4_reserved_bits(__cpu_has, __c) \
457({ \
458 u64 __reserved_bits = CR4_RESERVED_BITS; \
459 \
460 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
461 __reserved_bits |= X86_CR4_OSXSAVE; \
462 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
463 __reserved_bits |= X86_CR4_SMEP; \
464 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
465 __reserved_bits |= X86_CR4_SMAP; \
466 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
467 __reserved_bits |= X86_CR4_FSGSBASE; \
468 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
469 __reserved_bits |= X86_CR4_PKE; \
470 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
471 __reserved_bits |= X86_CR4_LA57; \
472 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
473 __reserved_bits |= X86_CR4_UMIP; \
474 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
475 __reserved_bits |= X86_CR4_VMXE; \
476 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
477 __reserved_bits |= X86_CR4_PCIDE; \
478 __reserved_bits; \
479})
480
481int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
482 void *dst);
483int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
484 void *dst);
485int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
486 unsigned int port, void *data, unsigned int count,
487 int in);
488
489#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/pvclock.h>
7#include "kvm_cache_regs.h"
8
9#define KVM_DEFAULT_PLE_GAP 128
10#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
11#define KVM_DEFAULT_PLE_WINDOW_GROW 2
12#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
13#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
14#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
15#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
16
17static inline unsigned int __grow_ple_window(unsigned int val,
18 unsigned int base, unsigned int modifier, unsigned int max)
19{
20 u64 ret = val;
21
22 if (modifier < 1)
23 return base;
24
25 if (modifier < base)
26 ret *= modifier;
27 else
28 ret += modifier;
29
30 return min(ret, (u64)max);
31}
32
33static inline unsigned int __shrink_ple_window(unsigned int val,
34 unsigned int base, unsigned int modifier, unsigned int min)
35{
36 if (modifier < 1)
37 return base;
38
39 if (modifier < base)
40 val /= modifier;
41 else
42 val -= modifier;
43
44 return max(val, min);
45}
46
47#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
48
49static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
50{
51 vcpu->arch.exception.pending = false;
52 vcpu->arch.exception.injected = false;
53}
54
55static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
56 bool soft)
57{
58 vcpu->arch.interrupt.injected = true;
59 vcpu->arch.interrupt.soft = soft;
60 vcpu->arch.interrupt.nr = vector;
61}
62
63static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
64{
65 vcpu->arch.interrupt.injected = false;
66}
67
68static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
69{
70 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
71 vcpu->arch.nmi_injected;
72}
73
74static inline bool kvm_exception_is_soft(unsigned int nr)
75{
76 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
77}
78
79static inline bool is_protmode(struct kvm_vcpu *vcpu)
80{
81 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
82}
83
84static inline int is_long_mode(struct kvm_vcpu *vcpu)
85{
86#ifdef CONFIG_X86_64
87 return vcpu->arch.efer & EFER_LMA;
88#else
89 return 0;
90#endif
91}
92
93static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
94{
95 int cs_db, cs_l;
96
97 if (!is_long_mode(vcpu))
98 return false;
99 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
100 return cs_l;
101}
102
103static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
104{
105#ifdef CONFIG_X86_64
106 return (vcpu->arch.efer & EFER_LMA) &&
107 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
108#else
109 return 0;
110#endif
111}
112
113static inline bool x86_exception_has_error_code(unsigned int vector)
114{
115 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
116 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
117 BIT(PF_VECTOR) | BIT(AC_VECTOR);
118
119 return (1U << vector) & exception_has_error_code;
120}
121
122static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
123{
124 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
125}
126
127static inline int is_pae(struct kvm_vcpu *vcpu)
128{
129 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
130}
131
132static inline int is_pse(struct kvm_vcpu *vcpu)
133{
134 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
135}
136
137static inline int is_paging(struct kvm_vcpu *vcpu)
138{
139 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
140}
141
142static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
143{
144 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
145}
146
147static inline u32 bit(int bitno)
148{
149 return 1 << (bitno & 31);
150}
151
152static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
153{
154 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
155}
156
157static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
158{
159 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
160}
161
162static inline u64 get_canonical(u64 la, u8 vaddr_bits)
163{
164 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
165}
166
167static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
168{
169#ifdef CONFIG_X86_64
170 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
171#else
172 return false;
173#endif
174}
175
176static inline bool emul_is_noncanonical_address(u64 la,
177 struct x86_emulate_ctxt *ctxt)
178{
179#ifdef CONFIG_X86_64
180 return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
181#else
182 return false;
183#endif
184}
185
186static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
187 gva_t gva, gfn_t gfn, unsigned access)
188{
189 u64 gen = kvm_memslots(vcpu->kvm)->generation;
190
191 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
192 return;
193
194 /*
195 * If this is a shadow nested page table, the "GVA" is
196 * actually a nGPA.
197 */
198 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
199 vcpu->arch.mmio_access = access;
200 vcpu->arch.mmio_gfn = gfn;
201 vcpu->arch.mmio_gen = gen;
202}
203
204static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
205{
206 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
207}
208
209/*
210 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
211 * clear all mmio cache info.
212 */
213#define MMIO_GVA_ANY (~(gva_t)0)
214
215static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
216{
217 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
218 return;
219
220 vcpu->arch.mmio_gva = 0;
221}
222
223static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
224{
225 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
226 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
227 return true;
228
229 return false;
230}
231
232static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
233{
234 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
235 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
236 return true;
237
238 return false;
239}
240
241static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu,
242 enum kvm_reg reg)
243{
244 unsigned long val = kvm_register_read(vcpu, reg);
245
246 return is_64_bit_mode(vcpu) ? val : (u32)val;
247}
248
249static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
250 enum kvm_reg reg,
251 unsigned long val)
252{
253 if (!is_64_bit_mode(vcpu))
254 val = (u32)val;
255 return kvm_register_write(vcpu, reg, val);
256}
257
258static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
259{
260 return !(kvm->arch.disabled_quirks & quirk);
261}
262
263void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
264void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
265
266void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
267u64 get_kvmclock_ns(struct kvm *kvm);
268
269int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
270 gva_t addr, void *val, unsigned int bytes,
271 struct x86_exception *exception);
272
273int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
274 gva_t addr, void *val, unsigned int bytes,
275 struct x86_exception *exception);
276
277int handle_ud(struct kvm_vcpu *vcpu);
278
279void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
280
281void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
282u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
283bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
284int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
285int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
286bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
287 int page_num);
288bool kvm_vector_hashing_enabled(void);
289int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
290 int emulation_type, void *insn, int insn_len);
291
292#define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
293 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
294 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
295 | XFEATURE_MASK_PKRU)
296extern u64 host_xcr0;
297
298extern u64 kvm_supported_xcr0(void);
299
300extern unsigned int min_timer_period_us;
301
302extern bool enable_vmware_backdoor;
303
304extern int pi_inject_timer;
305
306extern struct static_key kvm_no_apic_vcpu;
307
308static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
309{
310 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
311 vcpu->arch.virtual_tsc_shift);
312}
313
314/* Same "calling convention" as do_div:
315 * - divide (n << 32) by base
316 * - put result in n
317 * - return remainder
318 */
319#define do_shl32_div32(n, base) \
320 ({ \
321 u32 __quot, __rem; \
322 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
323 : "rm" (base), "0" (0), "1" ((u32) n)); \
324 n = __quot; \
325 __rem; \
326 })
327
328static inline bool kvm_mwait_in_guest(struct kvm *kvm)
329{
330 return kvm->arch.mwait_in_guest;
331}
332
333static inline bool kvm_hlt_in_guest(struct kvm *kvm)
334{
335 return kvm->arch.hlt_in_guest;
336}
337
338static inline bool kvm_pause_in_guest(struct kvm *kvm)
339{
340 return kvm->arch.pause_in_guest;
341}
342
343static inline bool kvm_cstate_in_guest(struct kvm *kvm)
344{
345 return kvm->arch.cstate_in_guest;
346}
347
348DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
349
350static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
351{
352 __this_cpu_write(current_vcpu, vcpu);
353}
354
355static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
356{
357 __this_cpu_write(current_vcpu, NULL);
358}
359
360
361static inline bool kvm_pat_valid(u64 data)
362{
363 if (data & 0xF8F8F8F8F8F8F8F8ull)
364 return false;
365 /* 0, 1, 4, 5, 6, 7 are valid values. */
366 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
367}
368
369void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu);
370void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu);
371
372#endif