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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Kernel execution entry point code.
4 *
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Rewritten for PReP
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 */
28
29#include <linux/init.h>
30#include <linux/threads.h>
31#include <asm/processor.h>
32#include <asm/page.h>
33#include <asm/mmu.h>
34#include <asm/pgtable.h>
35#include <asm/cputable.h>
36#include <asm/thread_info.h>
37#include <asm/ppc_asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/cache.h>
40#include <asm/ptrace.h>
41#include <asm/export.h>
42#include <asm/feature-fixups.h>
43#include "head_booke.h"
44
45/* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 __HEAD
57_ENTRY(_stext);
58_ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
64
65 /* Translate device tree address to physical, save in r30/r31 */
66 bl get_phys_addr
67 mr r30,r3
68 mr r31,r4
69
70 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */
72 li r23,0 /* phys kernel start (high) */
73
74#ifdef CONFIG_RELOCATABLE
75 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
76
77 /* Translate _stext address to physical, save in r23/r25 */
78 bl get_phys_addr
79 mr r23,r3
80 mr r25,r4
81
82 bl 0f
830: mflr r8
84 addis r3,r8,(is_second_reloc - 0b)@ha
85 lwz r19,(is_second_reloc - 0b)@l(r3)
86
87 /* Check if this is the second relocation. */
88 cmpwi r19,1
89 bne 1f
90
91 /*
92 * For the second relocation, we already get the real memstart_addr
93 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94 * then the virtual address of start kernel should be:
95 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
96 * Since the offset between kernstart_addr and memstart_addr should
97 * never be beyond 1G, so we can just use the lower 32bit of them
98 * for the calculation.
99 */
100 lis r3,PAGE_OFFSET@h
101
102 addis r4,r8,(kernstart_addr - 0b)@ha
103 addi r4,r4,(kernstart_addr - 0b)@l
104 lwz r5,4(r4)
105
106 addis r6,r8,(memstart_addr - 0b)@ha
107 addi r6,r6,(memstart_addr - 0b)@l
108 lwz r7,4(r6)
109
110 subf r5,r7,r5
111 add r3,r3,r5
112 b 2f
113
1141:
115 /*
116 * We have the runtime (virutal) address of our base.
117 * We calculate our shift of offset from a 64M page.
118 * We could map the 64M page we belong to at PAGE_OFFSET and
119 * get going from there.
120 */
121 lis r4,KERNELBASE@h
122 ori r4,r4,KERNELBASE@l
123 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
124 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
125 subf r3,r5,r6 /* r3 = r6 - r5 */
126 add r3,r4,r3 /* Required Virtual Address */
127
1282: bl relocate
129
130 /*
131 * For the second relocation, we already set the right tlb entries
132 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
133 */
134 cmpwi r19,1
135 beq set_ivor
136#endif
137
138/* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs. We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory. Any boot info passed from the
142 * bootloader needs to live in this first 64M.
143 *
144 * Requirement on bootloader:
145 * - The page we're executing in needs to reside in TLB1 and
146 * have IPROT=1. If not an invalidate broadcast could
147 * evict the entry we're currently executing in.
148 *
149 * r3 = Index of TLB1 were executing in
150 * r4 = Current MSR[IS]
151 * r5 = Index of TLB1 temp mapping
152 *
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
154 * if needed
155 */
156
157_ENTRY(__early_start)
158
159#define ENTRY_MAPPING_BOOT_SETUP
160#include "fsl_booke_entry_mapping.S"
161#undef ENTRY_MAPPING_BOOT_SETUP
162
163set_ivor:
164 /* Establish the interrupt vector offsets */
165 SET_IVOR(0, CriticalInput);
166 SET_IVOR(1, MachineCheck);
167 SET_IVOR(2, DataStorage);
168 SET_IVOR(3, InstructionStorage);
169 SET_IVOR(4, ExternalInput);
170 SET_IVOR(5, Alignment);
171 SET_IVOR(6, Program);
172 SET_IVOR(7, FloatingPointUnavailable);
173 SET_IVOR(8, SystemCall);
174 SET_IVOR(9, AuxillaryProcessorUnavailable);
175 SET_IVOR(10, Decrementer);
176 SET_IVOR(11, FixedIntervalTimer);
177 SET_IVOR(12, WatchdogTimer);
178 SET_IVOR(13, DataTLBError);
179 SET_IVOR(14, InstructionTLBError);
180 SET_IVOR(15, DebugCrit);
181
182 /* Establish the interrupt vector base */
183 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
184 mtspr SPRN_IVPR,r4
185
186 /* Setup the defaults for TLB entries */
187 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
188#ifdef CONFIG_E200
189 oris r2,r2,MAS4_TLBSELD(1)@h
190#endif
191 mtspr SPRN_MAS4, r2
192
193#if !defined(CONFIG_BDI_SWITCH)
194 /*
195 * The Abatron BDI JTAG debugger does not tolerate others
196 * mucking with the debug registers.
197 */
198 lis r2,DBCR0_IDM@h
199 mtspr SPRN_DBCR0,r2
200 isync
201 /* clear any residual debug events */
202 li r2,-1
203 mtspr SPRN_DBSR,r2
204#endif
205
206#ifdef CONFIG_SMP
207 /* Check to see if we're the second processor, and jump
208 * to the secondary_start code if so
209 */
210 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
211 lwz r24, 0(r24)
212 cmpwi r24, -1
213 mfspr r24,SPRN_PIR
214 bne __secondary_start
215#endif
216
217 /*
218 * This is where the main kernel code starts.
219 */
220
221 /* ptr to current */
222 lis r2,init_task@h
223 ori r2,r2,init_task@l
224
225 /* ptr to current thread */
226 addi r4,r2,THREAD /* init task's THREAD */
227 mtspr SPRN_SPRG_THREAD,r4
228
229 /* stack */
230 lis r1,init_thread_union@h
231 ori r1,r1,init_thread_union@l
232 li r0,0
233 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
234
235#ifdef CONFIG_SMP
236 stw r24, TASK_CPU(r2)
237#endif
238
239 bl early_init
240
241#ifdef CONFIG_RELOCATABLE
242 mr r3,r30
243 mr r4,r31
244#ifdef CONFIG_PHYS_64BIT
245 mr r5,r23
246 mr r6,r25
247#else
248 mr r5,r25
249#endif
250 bl relocate_init
251#endif
252
253#ifdef CONFIG_DYNAMIC_MEMSTART
254 lis r3,kernstart_addr@ha
255 la r3,kernstart_addr@l(r3)
256#ifdef CONFIG_PHYS_64BIT
257 stw r23,0(r3)
258 stw r25,4(r3)
259#else
260 stw r25,0(r3)
261#endif
262#endif
263
264/*
265 * Decide what sort of machine this is and initialize the MMU.
266 */
267#ifdef CONFIG_KASAN
268 bl kasan_early_init
269#endif
270 mr r3,r30
271 mr r4,r31
272 bl machine_init
273 bl MMU_init
274
275 /* Setup PTE pointers for the Abatron bdiGDB */
276 lis r6, swapper_pg_dir@h
277 ori r6, r6, swapper_pg_dir@l
278 lis r5, abatron_pteptrs@h
279 ori r5, r5, abatron_pteptrs@l
280 lis r4, KERNELBASE@h
281 ori r4, r4, KERNELBASE@l
282 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
283 stw r6, 0(r5)
284
285 /* Let's move on */
286 lis r4,start_kernel@h
287 ori r4,r4,start_kernel@l
288 lis r3,MSR_KERNEL@h
289 ori r3,r3,MSR_KERNEL@l
290 mtspr SPRN_SRR0,r4
291 mtspr SPRN_SRR1,r3
292 rfi /* change context and jump to start_kernel */
293
294/* Macros to hide the PTE size differences
295 *
296 * FIND_PTE -- walks the page tables given EA & pgdir pointer
297 * r10 -- EA of fault
298 * r11 -- PGDIR pointer
299 * r12 -- free
300 * label 2: is the bailout case
301 *
302 * if we find the pte (fall through):
303 * r11 is low pte word
304 * r12 is pointer to the pte
305 * r10 is the pshift from the PGD, if we're a hugepage
306 */
307#ifdef CONFIG_PTE_64BIT
308#ifdef CONFIG_HUGETLB_PAGE
309#define FIND_PTE \
310 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
311 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
312 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
313 blt 1000f; /* Normal non-huge page */ \
314 beq 2f; /* Bail if no table */ \
315 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
316 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
317 xor r12, r10, r11; /* drop size bits from pointer */ \
318 b 1001f; \
3191000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
320 li r10, 0; /* clear r10 */ \
3211001: lwz r11, 4(r12); /* Get pte entry */
322#else
323#define FIND_PTE \
324 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
325 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
326 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
327 beq 2f; /* Bail if no table */ \
328 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
329 lwz r11, 4(r12); /* Get pte entry */
330#endif /* HUGEPAGE */
331#else /* !PTE_64BIT */
332#define FIND_PTE \
333 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
334 lwz r11, 0(r11); /* Get L1 entry */ \
335 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
336 beq 2f; /* Bail if no table */ \
337 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
338 lwz r11, 0(r12); /* Get Linux PTE */
339#endif
340
341/*
342 * Interrupt vector entry code
343 *
344 * The Book E MMUs are always on so we don't need to handle
345 * interrupts in real mode as with previous PPC processors. In
346 * this case we handle interrupts in the kernel virtual address
347 * space.
348 *
349 * Interrupt vectors are dynamically placed relative to the
350 * interrupt prefix as determined by the address of interrupt_base.
351 * The interrupt vectors offsets are programmed using the labels
352 * for each interrupt vector entry.
353 *
354 * Interrupt vectors must be aligned on a 16 byte boundary.
355 * We align on a 32 byte cache line boundary for good measure.
356 */
357
358interrupt_base:
359 /* Critical Input Interrupt */
360 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
361
362 /* Machine Check Interrupt */
363#ifdef CONFIG_E200
364 /* no RFMCI, MCSRRs on E200 */
365 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
366 machine_check_exception)
367#else
368 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
369#endif
370
371 /* Data Storage Interrupt */
372 START_EXCEPTION(DataStorage)
373 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
374 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
375 stw r5,_ESR(r11)
376 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
377 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
378 bne 1f
379 EXC_XFER_LITE(0x0300, handle_page_fault)
3801:
381 addi r3,r1,STACK_FRAME_OVERHEAD
382 EXC_XFER_LITE(0x0300, CacheLockingException)
383
384 /* Instruction Storage Interrupt */
385 INSTRUCTION_STORAGE_EXCEPTION
386
387 /* External Input Interrupt */
388 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
389
390 /* Alignment Interrupt */
391 ALIGNMENT_EXCEPTION
392
393 /* Program Interrupt */
394 PROGRAM_EXCEPTION
395
396 /* Floating Point Unavailable Interrupt */
397#ifdef CONFIG_PPC_FPU
398 FP_UNAVAILABLE_EXCEPTION
399#else
400#ifdef CONFIG_E200
401 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
402 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
403 program_check_exception, EXC_XFER_STD)
404#else
405 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
406 unknown_exception, EXC_XFER_STD)
407#endif
408#endif
409
410 /* System Call Interrupt */
411 START_EXCEPTION(SystemCall)
412 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
413
414 /* Auxiliary Processor Unavailable Interrupt */
415 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
416 unknown_exception, EXC_XFER_STD)
417
418 /* Decrementer Interrupt */
419 DECREMENTER_EXCEPTION
420
421 /* Fixed Internal Timer Interrupt */
422 /* TODO: Add FIT support */
423 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
424 unknown_exception, EXC_XFER_STD)
425
426 /* Watchdog Timer Interrupt */
427#ifdef CONFIG_BOOKE_WDT
428 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
429#else
430 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
431#endif
432
433 /* Data TLB Error Interrupt */
434 START_EXCEPTION(DataTLBError)
435 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
436 mfspr r10, SPRN_SPRG_THREAD
437 stw r11, THREAD_NORMSAVE(0)(r10)
438#ifdef CONFIG_KVM_BOOKE_HV
439BEGIN_FTR_SECTION
440 mfspr r11, SPRN_SRR1
441END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
442#endif
443 stw r12, THREAD_NORMSAVE(1)(r10)
444 stw r13, THREAD_NORMSAVE(2)(r10)
445 mfcr r13
446 stw r13, THREAD_NORMSAVE(3)(r10)
447 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
448START_BTB_FLUSH_SECTION
449 mfspr r11, SPRN_SRR1
450 andi. r10,r11,MSR_PR
451 beq 1f
452 BTB_FLUSH(r10)
4531:
454END_BTB_FLUSH_SECTION
455 mfspr r10, SPRN_DEAR /* Get faulting address */
456
457 /* If we are faulting a kernel address, we have to use the
458 * kernel page tables.
459 */
460 lis r11, PAGE_OFFSET@h
461 cmplw 5, r10, r11
462 blt 5, 3f
463 lis r11, swapper_pg_dir@h
464 ori r11, r11, swapper_pg_dir@l
465
466 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
467 rlwinm r12,r12,0,16,1
468 mtspr SPRN_MAS1,r12
469
470 b 4f
471
472 /* Get the PGD for the current thread */
4733:
474 mfspr r11,SPRN_SPRG_THREAD
475 lwz r11,PGDIR(r11)
476
4774:
478 /* Mask of required permission bits. Note that while we
479 * do copy ESR:ST to _PAGE_RW position as trying to write
480 * to an RO page is pretty common, we don't do it with
481 * _PAGE_DIRTY. We could do it, but it's a fairly rare
482 * event so I'd rather take the overhead when it happens
483 * rather than adding an instruction here. We should measure
484 * whether the whole thing is worth it in the first place
485 * as we could avoid loading SPRN_ESR completely in the first
486 * place...
487 *
488 * TODO: Is it worth doing that mfspr & rlwimi in the first
489 * place or can we save a couple of instructions here ?
490 */
491 mfspr r12,SPRN_ESR
492#ifdef CONFIG_PTE_64BIT
493 li r13,_PAGE_PRESENT
494 oris r13,r13,_PAGE_ACCESSED@h
495#else
496 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
497#endif
498 rlwimi r13,r12,11,29,29
499
500 FIND_PTE
501 andc. r13,r13,r11 /* Check permission */
502
503#ifdef CONFIG_PTE_64BIT
504#ifdef CONFIG_SMP
505 subf r13,r11,r12 /* create false data dep */
506 lwzx r13,r11,r13 /* Get upper pte bits */
507#else
508 lwz r13,0(r12) /* Get upper pte bits */
509#endif
510#endif
511
512 bne 2f /* Bail if permission/valid mismach */
513
514 /* Jump to common tlb load */
515 b finish_tlb_load
5162:
517 /* The bailout. Restore registers to pre-exception conditions
518 * and call the heavyweights to help us out.
519 */
520 mfspr r10, SPRN_SPRG_THREAD
521 lwz r11, THREAD_NORMSAVE(3)(r10)
522 mtcr r11
523 lwz r13, THREAD_NORMSAVE(2)(r10)
524 lwz r12, THREAD_NORMSAVE(1)(r10)
525 lwz r11, THREAD_NORMSAVE(0)(r10)
526 mfspr r10, SPRN_SPRG_RSCRATCH0
527 b DataStorage
528
529 /* Instruction TLB Error Interrupt */
530 /*
531 * Nearly the same as above, except we get our
532 * information from different registers and bailout
533 * to a different point.
534 */
535 START_EXCEPTION(InstructionTLBError)
536 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
537 mfspr r10, SPRN_SPRG_THREAD
538 stw r11, THREAD_NORMSAVE(0)(r10)
539#ifdef CONFIG_KVM_BOOKE_HV
540BEGIN_FTR_SECTION
541 mfspr r11, SPRN_SRR1
542END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
543#endif
544 stw r12, THREAD_NORMSAVE(1)(r10)
545 stw r13, THREAD_NORMSAVE(2)(r10)
546 mfcr r13
547 stw r13, THREAD_NORMSAVE(3)(r10)
548 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
549START_BTB_FLUSH_SECTION
550 mfspr r11, SPRN_SRR1
551 andi. r10,r11,MSR_PR
552 beq 1f
553 BTB_FLUSH(r10)
5541:
555END_BTB_FLUSH_SECTION
556
557 mfspr r10, SPRN_SRR0 /* Get faulting address */
558
559 /* If we are faulting a kernel address, we have to use the
560 * kernel page tables.
561 */
562 lis r11, PAGE_OFFSET@h
563 cmplw 5, r10, r11
564 blt 5, 3f
565 lis r11, swapper_pg_dir@h
566 ori r11, r11, swapper_pg_dir@l
567
568 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
569 rlwinm r12,r12,0,16,1
570 mtspr SPRN_MAS1,r12
571
572 /* Make up the required permissions for kernel code */
573#ifdef CONFIG_PTE_64BIT
574 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
575 oris r13,r13,_PAGE_ACCESSED@h
576#else
577 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
578#endif
579 b 4f
580
581 /* Get the PGD for the current thread */
5823:
583 mfspr r11,SPRN_SPRG_THREAD
584 lwz r11,PGDIR(r11)
585
586 /* Make up the required permissions for user code */
587#ifdef CONFIG_PTE_64BIT
588 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
589 oris r13,r13,_PAGE_ACCESSED@h
590#else
591 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
592#endif
593
5944:
595 FIND_PTE
596 andc. r13,r13,r11 /* Check permission */
597
598#ifdef CONFIG_PTE_64BIT
599#ifdef CONFIG_SMP
600 subf r13,r11,r12 /* create false data dep */
601 lwzx r13,r11,r13 /* Get upper pte bits */
602#else
603 lwz r13,0(r12) /* Get upper pte bits */
604#endif
605#endif
606
607 bne 2f /* Bail if permission mismach */
608
609 /* Jump to common TLB load point */
610 b finish_tlb_load
611
6122:
613 /* The bailout. Restore registers to pre-exception conditions
614 * and call the heavyweights to help us out.
615 */
616 mfspr r10, SPRN_SPRG_THREAD
617 lwz r11, THREAD_NORMSAVE(3)(r10)
618 mtcr r11
619 lwz r13, THREAD_NORMSAVE(2)(r10)
620 lwz r12, THREAD_NORMSAVE(1)(r10)
621 lwz r11, THREAD_NORMSAVE(0)(r10)
622 mfspr r10, SPRN_SPRG_RSCRATCH0
623 b InstructionStorage
624
625/* Define SPE handlers for e200 and e500v2 */
626#ifdef CONFIG_SPE
627 /* SPE Unavailable */
628 START_EXCEPTION(SPEUnavailable)
629 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
630 beq 1f
631 bl load_up_spe
632 b fast_exception_return
6331: addi r3,r1,STACK_FRAME_OVERHEAD
634 EXC_XFER_LITE(0x2010, KernelSPE)
635#elif defined(CONFIG_SPE_POSSIBLE)
636 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
637 unknown_exception, EXC_XFER_STD)
638#endif /* CONFIG_SPE_POSSIBLE */
639
640 /* SPE Floating Point Data */
641#ifdef CONFIG_SPE
642 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
643 SPEFloatingPointException, EXC_XFER_STD)
644
645 /* SPE Floating Point Round */
646 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
647 SPEFloatingPointRoundException, EXC_XFER_STD)
648#elif defined(CONFIG_SPE_POSSIBLE)
649 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
650 unknown_exception, EXC_XFER_STD)
651 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
652 unknown_exception, EXC_XFER_STD)
653#endif /* CONFIG_SPE_POSSIBLE */
654
655
656 /* Performance Monitor */
657 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
658 performance_monitor_exception, EXC_XFER_STD)
659
660 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
661
662 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
663 CriticalDoorbell, unknown_exception)
664
665 /* Debug Interrupt */
666 DEBUG_DEBUG_EXCEPTION
667 DEBUG_CRIT_EXCEPTION
668
669 GUEST_DOORBELL_EXCEPTION
670
671 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
672 unknown_exception)
673
674 /* Hypercall */
675 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
676
677 /* Embedded Hypervisor Privilege */
678 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
679
680interrupt_end:
681
682/*
683 * Local functions
684 */
685
686/*
687 * Both the instruction and data TLB miss get to this
688 * point to load the TLB.
689 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
690 * r11 - TLB (info from Linux PTE)
691 * r12 - available to use
692 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
693 * CR5 - results of addr >= PAGE_OFFSET
694 * MAS0, MAS1 - loaded with proper value when we get here
695 * MAS2, MAS3 - will need additional info from Linux PTE
696 * Upon exit, we reload everything and RFI.
697 */
698finish_tlb_load:
699#ifdef CONFIG_HUGETLB_PAGE
700 cmpwi 6, r10, 0 /* check for huge page */
701 beq 6, finish_tlb_load_cont /* !huge */
702
703 /* Alas, we need more scratch registers for hugepages */
704 mfspr r12, SPRN_SPRG_THREAD
705 stw r14, THREAD_NORMSAVE(4)(r12)
706 stw r15, THREAD_NORMSAVE(5)(r12)
707 stw r16, THREAD_NORMSAVE(6)(r12)
708 stw r17, THREAD_NORMSAVE(7)(r12)
709
710 /* Get the next_tlbcam_idx percpu var */
711#ifdef CONFIG_SMP
712 lwz r15, TASK_CPU-THREAD(r12)
713 lis r14, __per_cpu_offset@h
714 ori r14, r14, __per_cpu_offset@l
715 rlwinm r15, r15, 2, 0, 29
716 lwzx r16, r14, r15
717#else
718 li r16, 0
719#endif
720 lis r17, next_tlbcam_idx@h
721 ori r17, r17, next_tlbcam_idx@l
722 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
723 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
724
725 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
726 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
727 mtspr SPRN_MAS0, r14
728
729 /* Extract TLB1CFG(NENTRY) */
730 mfspr r16, SPRN_TLB1CFG
731 andi. r16, r16, 0xfff
732
733 /* Update next_tlbcam_idx, wrapping when necessary */
734 addi r15, r15, 1
735 cmpw r15, r16
736 blt 100f
737 lis r14, tlbcam_index@h
738 ori r14, r14, tlbcam_index@l
739 lwz r15, 0(r14)
740100: stw r15, 0(r17)
741
742 /*
743 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
744 * tlb_enc = (pshift - 10).
745 */
746 subi r15, r10, 10
747 mfspr r16, SPRN_MAS1
748 rlwimi r16, r15, 7, 20, 24
749 mtspr SPRN_MAS1, r16
750
751 /* copy the pshift for use later */
752 mr r14, r10
753
754 /* fall through */
755
756#endif /* CONFIG_HUGETLB_PAGE */
757
758 /*
759 * We set execute, because we don't have the granularity to
760 * properly set this at the page level (Linux problem).
761 * Many of these bits are software only. Bits we don't set
762 * here we (properly should) assume have the appropriate value.
763 */
764finish_tlb_load_cont:
765#ifdef CONFIG_PTE_64BIT
766 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
767 andi. r10, r11, _PAGE_DIRTY
768 bne 1f
769 li r10, MAS3_SW | MAS3_UW
770 andc r12, r12, r10
7711: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
772 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
7732: mtspr SPRN_MAS3, r12
774BEGIN_MMU_FTR_SECTION
775 srwi r10, r13, 12 /* grab RPN[12:31] */
776 mtspr SPRN_MAS7, r10
777END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
778#else
779 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
780 mr r13, r11
781 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
782 and r12, r11, r10
783 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
784 slwi r10, r12, 1
785 or r10, r10, r12
786 iseleq r12, r12, r10
787 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
788 mtspr SPRN_MAS3, r13
789#endif
790
791 mfspr r12, SPRN_MAS2
792#ifdef CONFIG_PTE_64BIT
793 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
794#else
795 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
796#endif
797#ifdef CONFIG_HUGETLB_PAGE
798 beq 6, 3f /* don't mask if page isn't huge */
799 li r13, 1
800 slw r13, r13, r14
801 subi r13, r13, 1
802 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
803 andc r12, r12, r13 /* mask off ea bits within the page */
804#endif
8053: mtspr SPRN_MAS2, r12
806
807#ifdef CONFIG_E200
808 /* Round robin TLB1 entries assignment */
809 mfspr r12, SPRN_MAS0
810
811 /* Extract TLB1CFG(NENTRY) */
812 mfspr r11, SPRN_TLB1CFG
813 andi. r11, r11, 0xfff
814
815 /* Extract MAS0(NV) */
816 andi. r13, r12, 0xfff
817 addi r13, r13, 1
818 cmpw 0, r13, r11
819 addi r12, r12, 1
820
821 /* check if we need to wrap */
822 blt 7f
823
824 /* wrap back to first free tlbcam entry */
825 lis r13, tlbcam_index@ha
826 lwz r13, tlbcam_index@l(r13)
827 rlwimi r12, r13, 0, 20, 31
8287:
829 mtspr SPRN_MAS0,r12
830#endif /* CONFIG_E200 */
831
832tlb_write_entry:
833 tlbwe
834
835 /* Done...restore registers and get out of here. */
836 mfspr r10, SPRN_SPRG_THREAD
837#ifdef CONFIG_HUGETLB_PAGE
838 beq 6, 8f /* skip restore for 4k page faults */
839 lwz r14, THREAD_NORMSAVE(4)(r10)
840 lwz r15, THREAD_NORMSAVE(5)(r10)
841 lwz r16, THREAD_NORMSAVE(6)(r10)
842 lwz r17, THREAD_NORMSAVE(7)(r10)
843#endif
8448: lwz r11, THREAD_NORMSAVE(3)(r10)
845 mtcr r11
846 lwz r13, THREAD_NORMSAVE(2)(r10)
847 lwz r12, THREAD_NORMSAVE(1)(r10)
848 lwz r11, THREAD_NORMSAVE(0)(r10)
849 mfspr r10, SPRN_SPRG_RSCRATCH0
850 rfi /* Force context change */
851
852#ifdef CONFIG_SPE
853/* Note that the SPE support is closely modeled after the AltiVec
854 * support. Changes to one are likely to be applicable to the
855 * other! */
856_GLOBAL(load_up_spe)
857/*
858 * Disable SPE for the task which had SPE previously,
859 * and save its SPE registers in its thread_struct.
860 * Enables SPE for use in the kernel on return.
861 * On SMP we know the SPE units are free, since we give it up every
862 * switch. -- Kumar
863 */
864 mfmsr r5
865 oris r5,r5,MSR_SPE@h
866 mtmsr r5 /* enable use of SPE now */
867 isync
868 /* enable use of SPE after return */
869 oris r9,r9,MSR_SPE@h
870 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
871 li r4,1
872 li r10,THREAD_ACC
873 stw r4,THREAD_USED_SPE(r5)
874 evlddx evr4,r10,r5
875 evmra evr4,evr4
876 REST_32EVRS(0,r10,r5,THREAD_EVR0)
877 blr
878
879/*
880 * SPE unavailable trap from kernel - print a message, but let
881 * the task use SPE in the kernel until it returns to user mode.
882 */
883KernelSPE:
884 lwz r3,_MSR(r1)
885 oris r3,r3,MSR_SPE@h
886 stw r3,_MSR(r1) /* enable use of SPE after return */
887#ifdef CONFIG_PRINTK
888 lis r3,87f@h
889 ori r3,r3,87f@l
890 mr r4,r2 /* current */
891 lwz r5,_NIP(r1)
892 bl printk
893#endif
894 b ret_from_except
895#ifdef CONFIG_PRINTK
89687: .string "SPE used in kernel (task=%p, pc=%x) \n"
897#endif
898 .align 4,0
899
900#endif /* CONFIG_SPE */
901
902/*
903 * Translate the effec addr in r3 to phys addr. The phys addr will be put
904 * into r3(higher 32bit) and r4(lower 32bit)
905 */
906get_phys_addr:
907 mfmsr r8
908 mfspr r9,SPRN_PID
909 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
910 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
911 mtspr SPRN_MAS6,r9
912
913 tlbsx 0,r3 /* must succeed */
914
915 mfspr r8,SPRN_MAS1
916 mfspr r12,SPRN_MAS3
917 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
918 li r10,1024
919 slw r10,r10,r9 /* r10 = page size */
920 addi r10,r10,-1
921 and r11,r3,r10 /* r11 = page offset */
922 andc r4,r12,r10 /* r4 = page base */
923 or r4,r4,r11 /* r4 = devtree phys addr */
924#ifdef CONFIG_PHYS_64BIT
925 mfspr r3,SPRN_MAS7
926#endif
927 blr
928
929/*
930 * Global functions
931 */
932
933#ifdef CONFIG_E200
934/* Adjust or setup IVORs for e200 */
935_GLOBAL(__setup_e200_ivors)
936 li r3,DebugDebug@l
937 mtspr SPRN_IVOR15,r3
938 li r3,SPEUnavailable@l
939 mtspr SPRN_IVOR32,r3
940 li r3,SPEFloatingPointData@l
941 mtspr SPRN_IVOR33,r3
942 li r3,SPEFloatingPointRound@l
943 mtspr SPRN_IVOR34,r3
944 sync
945 blr
946#endif
947
948#ifdef CONFIG_E500
949#ifndef CONFIG_PPC_E500MC
950/* Adjust or setup IVORs for e500v1/v2 */
951_GLOBAL(__setup_e500_ivors)
952 li r3,DebugCrit@l
953 mtspr SPRN_IVOR15,r3
954 li r3,SPEUnavailable@l
955 mtspr SPRN_IVOR32,r3
956 li r3,SPEFloatingPointData@l
957 mtspr SPRN_IVOR33,r3
958 li r3,SPEFloatingPointRound@l
959 mtspr SPRN_IVOR34,r3
960 li r3,PerformanceMonitor@l
961 mtspr SPRN_IVOR35,r3
962 sync
963 blr
964#else
965/* Adjust or setup IVORs for e500mc */
966_GLOBAL(__setup_e500mc_ivors)
967 li r3,DebugDebug@l
968 mtspr SPRN_IVOR15,r3
969 li r3,PerformanceMonitor@l
970 mtspr SPRN_IVOR35,r3
971 li r3,Doorbell@l
972 mtspr SPRN_IVOR36,r3
973 li r3,CriticalDoorbell@l
974 mtspr SPRN_IVOR37,r3
975 sync
976 blr
977
978/* setup ehv ivors for */
979_GLOBAL(__setup_ehv_ivors)
980 li r3,GuestDoorbell@l
981 mtspr SPRN_IVOR38,r3
982 li r3,CriticalGuestDoorbell@l
983 mtspr SPRN_IVOR39,r3
984 li r3,Hypercall@l
985 mtspr SPRN_IVOR40,r3
986 li r3,Ehvpriv@l
987 mtspr SPRN_IVOR41,r3
988 sync
989 blr
990#endif /* CONFIG_PPC_E500MC */
991#endif /* CONFIG_E500 */
992
993#ifdef CONFIG_SPE
994/*
995 * extern void __giveup_spe(struct task_struct *prev)
996 *
997 */
998_GLOBAL(__giveup_spe)
999 addi r3,r3,THREAD /* want THREAD of task */
1000 lwz r5,PT_REGS(r3)
1001 cmpi 0,r5,0
1002 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1003 evxor evr6, evr6, evr6 /* clear out evr6 */
1004 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1005 li r4,THREAD_ACC
1006 evstddx evr6, r4, r3 /* save off accumulator */
1007 beq 1f
1008 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1009 lis r3,MSR_SPE@h
1010 andc r4,r4,r3 /* disable SPE for previous task */
1011 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
10121:
1013 blr
1014#endif /* CONFIG_SPE */
1015
1016/*
1017 * extern void abort(void)
1018 *
1019 * At present, this routine just applies a system reset.
1020 */
1021_GLOBAL(abort)
1022 li r13,0
1023 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1024 isync
1025 mfmsr r13
1026 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1027 mtmsr r13
1028 isync
1029 mfspr r13,SPRN_DBCR0
1030 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1031 mtspr SPRN_DBCR0,r13
1032 isync
1033
1034_GLOBAL(set_context)
1035
1036#ifdef CONFIG_BDI_SWITCH
1037 /* Context switch the PTE pointer for the Abatron BDI2000.
1038 * The PGDIR is the second parameter.
1039 */
1040 lis r5, abatron_pteptrs@h
1041 ori r5, r5, abatron_pteptrs@l
1042 stw r4, 0x4(r5)
1043#endif
1044 mtspr SPRN_PID,r3
1045 isync /* Force context change */
1046 blr
1047
1048#ifdef CONFIG_SMP
1049/* When we get here, r24 needs to hold the CPU # */
1050 .globl __secondary_start
1051__secondary_start:
1052 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1053 lwz r3,0(r3)
1054 mtctr r3
1055 li r26,0 /* r26 safe? */
1056
1057 bl switch_to_as1
1058 mr r27,r3 /* tlb entry */
1059 /* Load each CAM entry */
10601: mr r3,r26
1061 bl loadcam_entry
1062 addi r26,r26,1
1063 bdnz 1b
1064 mr r3,r27 /* tlb entry */
1065 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1066 lwz r4,0(r4)
1067 mr r5,r25 /* phys kernel start */
1068 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1069 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1070 li r5,0 /* no device tree */
1071 li r6,0 /* not boot cpu */
1072 bl restore_to_as0
1073
1074
1075 lis r3,__secondary_hold_acknowledge@h
1076 ori r3,r3,__secondary_hold_acknowledge@l
1077 stw r24,0(r3)
1078
1079 li r3,0
1080 mr r4,r24 /* Why? */
1081 bl call_setup_cpu
1082
1083 /* get current's stack and current */
1084 lis r2,secondary_current@ha
1085 lwz r2,secondary_current@l(r2)
1086 lwz r1,TASK_STACK(r2)
1087
1088 /* stack */
1089 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1090 li r0,0
1091 stw r0,0(r1)
1092
1093 /* ptr to current thread */
1094 addi r4,r2,THREAD /* address of our thread_struct */
1095 mtspr SPRN_SPRG_THREAD,r4
1096
1097 /* Setup the defaults for TLB entries */
1098 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1099 mtspr SPRN_MAS4,r4
1100
1101 /* Jump to start_secondary */
1102 lis r4,MSR_KERNEL@h
1103 ori r4,r4,MSR_KERNEL@l
1104 lis r3,start_secondary@h
1105 ori r3,r3,start_secondary@l
1106 mtspr SPRN_SRR0,r3
1107 mtspr SPRN_SRR1,r4
1108 sync
1109 rfi
1110 sync
1111
1112 .globl __secondary_hold_acknowledge
1113__secondary_hold_acknowledge:
1114 .long -1
1115#endif
1116
1117/*
1118 * Create a tlb entry with the same effective and physical address as
1119 * the tlb entry used by the current running code. But set the TS to 1.
1120 * Then switch to the address space 1. It will return with the r3 set to
1121 * the ESEL of the new created tlb.
1122 */
1123_GLOBAL(switch_to_as1)
1124 mflr r5
1125
1126 /* Find a entry not used */
1127 mfspr r3,SPRN_TLB1CFG
1128 andi. r3,r3,0xfff
1129 mfspr r4,SPRN_PID
1130 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1131 mtspr SPRN_MAS6,r4
11321: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1133 addi r3,r3,-1
1134 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1135 mtspr SPRN_MAS0,r4
1136 tlbre
1137 mfspr r4,SPRN_MAS1
1138 andis. r4,r4,MAS1_VALID@h
1139 bne 1b
1140
1141 /* Get the tlb entry used by the current running code */
1142 bl 0f
11430: mflr r4
1144 tlbsx 0,r4
1145
1146 mfspr r4,SPRN_MAS1
1147 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1148 mtspr SPRN_MAS1,r4
1149
1150 mfspr r4,SPRN_MAS0
1151 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1152 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1153 mtspr SPRN_MAS0,r4
1154 tlbwe
1155 isync
1156 sync
1157
1158 mfmsr r4
1159 ori r4,r4,MSR_IS | MSR_DS
1160 mtspr SPRN_SRR0,r5
1161 mtspr SPRN_SRR1,r4
1162 sync
1163 rfi
1164
1165/*
1166 * Restore to the address space 0 and also invalidate the tlb entry created
1167 * by switch_to_as1.
1168 * r3 - the tlb entry which should be invalidated
1169 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1170 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1171 * r6 - boot cpu
1172*/
1173_GLOBAL(restore_to_as0)
1174 mflr r0
1175
1176 bl 0f
11770: mflr r9
1178 addi r9,r9,1f - 0b
1179
1180 /*
1181 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1182 * so we need calculate the right jump and device tree address based
1183 * on the offset passed by r4.
1184 */
1185 add r9,r9,r4
1186 add r5,r5,r4
1187 add r0,r0,r4
1188
11892: mfmsr r7
1190 li r8,(MSR_IS | MSR_DS)
1191 andc r7,r7,r8
1192
1193 mtspr SPRN_SRR0,r9
1194 mtspr SPRN_SRR1,r7
1195 sync
1196 rfi
1197
1198 /* Invalidate the temporary tlb entry for AS1 */
11991: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1200 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1201 mtspr SPRN_MAS0,r9
1202 tlbre
1203 mfspr r9,SPRN_MAS1
1204 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1205 mtspr SPRN_MAS1,r9
1206 tlbwe
1207 isync
1208
1209 cmpwi r4,0
1210 cmpwi cr1,r6,0
1211 cror eq,4*cr1+eq,eq
1212 bne 3f /* offset != 0 && is_boot_cpu */
1213 mtlr r0
1214 blr
1215
1216 /*
1217 * The PAGE_OFFSET will map to a different physical address,
1218 * jump to _start to do another relocation again.
1219 */
12203: mr r3,r5
1221 bl _start
1222
1223/*
1224 * We put a few things here that have to be page-aligned. This stuff
1225 * goes at the beginning of the data segment, which is page-aligned.
1226 */
1227 .data
1228 .align 12
1229 .globl sdata
1230sdata:
1231 .globl empty_zero_page
1232empty_zero_page:
1233 .space 4096
1234EXPORT_SYMBOL(empty_zero_page)
1235 .globl swapper_pg_dir
1236swapper_pg_dir:
1237 .space PGD_TABLE_SIZE
1238
1239/*
1240 * Room for two PTE pointers, usually the kernel and current user pointers
1241 * to their respective root page table.
1242 */
1243abatron_pteptrs:
1244 .space 8