Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __HEAD_BOOKE_H__
3#define __HEAD_BOOKE_H__
4
5#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6#include <asm/kvm_asm.h>
7#include <asm/kvm_booke_hv_asm.h>
8
9#ifdef __ASSEMBLY__
10
11/*
12 * Macros used for common Book-e exception handling
13 */
14
15#define SET_IVOR(vector_number, vector_label) \
16 li r26,vector_label@l; \
17 mtspr SPRN_IVOR##vector_number,r26; \
18 sync
19
20#if (THREAD_SHIFT < 15)
21#define ALLOC_STACK_FRAME(reg, val) \
22 addi reg,reg,val
23#else
24#define ALLOC_STACK_FRAME(reg, val) \
25 addis reg,reg,val@ha; \
26 addi reg,reg,val@l
27#endif
28
29/*
30 * Macro used to get to thread save registers.
31 * Note that entries 0-3 are used for the prolog code, and the remaining
32 * entries are available for specific exception use in the event a handler
33 * requires more than 4 scratch registers.
34 */
35#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
36
37#ifdef CONFIG_PPC_E500
38#define BOOKE_CLEAR_BTB(reg) \
39START_BTB_FLUSH_SECTION \
40 BTB_FLUSH(reg) \
41END_BTB_FLUSH_SECTION
42#else
43#define BOOKE_CLEAR_BTB(reg)
44#endif
45
46
47#define NORMAL_EXCEPTION_PROLOG(trapno, intno) \
48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
49 mfspr r10, SPRN_SPRG_THREAD; \
50 stw r11, THREAD_NORMSAVE(0)(r10); \
51 stw r13, THREAD_NORMSAVE(2)(r10); \
52 mfcr r13; /* save CR in r13 for now */\
53 mfspr r11, SPRN_SRR1; \
54 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
55 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
56 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \
57 mtmsr r11; \
58 mr r11, r1; \
59 beq 1f; \
60 BOOKE_CLEAR_BTB(r11) \
61 /* if from user, start at top of this thread's kernel stack */ \
62 lwz r11, TASK_STACK - THREAD(r10); \
63 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
641 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
65 stw r13, _CCR(r11); /* save various registers */ \
66 stw r12,GPR12(r11); \
67 stw r9,GPR9(r11); \
68 mfspr r13, SPRN_SPRG_RSCRATCH0; \
69 stw r13, GPR10(r11); \
70 lwz r12, THREAD_NORMSAVE(0)(r10); \
71 stw r12,GPR11(r11); \
72 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
73 mflr r10; \
74 stw r10,_LINK(r11); \
75 mfspr r12,SPRN_SRR0; \
76 stw r1, GPR1(r11); \
77 mfspr r9,SPRN_SRR1; \
78 stw r1, 0(r11); \
79 mr r1, r11; \
80 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
81 COMMON_EXCEPTION_PROLOG_END trapno
82
83.macro COMMON_EXCEPTION_PROLOG_END trapno
84 stw r0,GPR0(r1)
85 lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
86 addi r10, r10, STACK_FRAME_REGS_MARKER@l
87 stw r10, STACK_INT_FRAME_MARKER(r1)
88 li r10, \trapno
89 stw r10,_TRAP(r1)
90 SAVE_GPRS(3, 8, r1)
91 SAVE_NVGPRS(r1)
92 stw r2,GPR2(r1)
93 stw r12,_NIP(r1)
94 stw r9,_MSR(r1)
95 mfctr r10
96 mfspr r2,SPRN_SPRG_THREAD
97 stw r10,_CTR(r1)
98 tovirt(r2, r2)
99 mfspr r10,SPRN_XER
100 addi r2, r2, -THREAD
101 stw r10,_XER(r1)
102 addi r3,r1,STACK_INT_FRAME_REGS
103.endm
104
105.macro prepare_transfer_to_handler
106#ifdef CONFIG_PPC_E500
107 andi. r12,r9,MSR_PR
108 bne 777f
109 bl prepare_transfer_to_handler
110777:
111#endif
112.endm
113
114.macro SYSCALL_ENTRY trapno intno srr1
115 mfspr r10, SPRN_SPRG_THREAD
116#ifdef CONFIG_KVM_BOOKE_HV
117BEGIN_FTR_SECTION
118 mtspr SPRN_SPRG_WSCRATCH0, r10
119 stw r11, THREAD_NORMSAVE(0)(r10)
120 stw r13, THREAD_NORMSAVE(2)(r10)
121 mfcr r13 /* save CR in r13 for now */
122 mfspr r11, SPRN_SRR1
123 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
124 bf 3, 1975f
125 b kvmppc_handler_\intno\()_\srr1
1261975:
127 mr r12, r13
128 lwz r13, THREAD_NORMSAVE(2)(r10)
129FTR_SECTION_ELSE
130 mfcr r12
131ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
132#else
133 mfcr r12
134#endif
135 mfspr r9, SPRN_SRR1
136 BOOKE_CLEAR_BTB(r11)
137 mr r11, r1
138 lwz r1, TASK_STACK - THREAD(r10)
139 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
140 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE)
141 stw r12, _CCR(r1)
142 mfspr r12,SPRN_SRR0
143 stw r12,_NIP(r1)
144 b transfer_to_syscall /* jump to handler */
145.endm
146
147/* To handle the additional exception priority levels on 40x and Book-E
148 * processors we allocate a stack per additional priority level.
149 *
150 * On 40x critical is the only additional level
151 * On 44x/e500 we have critical and machine check
152 *
153 * Additionally we reserve a SPRG for each priority level so we can free up a
154 * GPR to use as the base for indirect access to the exception stacks. This
155 * is necessary since the MMU is always on, for Book-E parts, and the stacks
156 * are offset from KERNELBASE.
157 *
158 * There is some space optimization to be had here if desired. However
159 * to allow for a common kernel with support for debug exceptions either
160 * going to critical or their own debug level we aren't currently
161 * providing configurations that micro-optimize space usage.
162 */
163
164#define MC_STACK_BASE mcheckirq_ctx
165#define CRIT_STACK_BASE critirq_ctx
166
167/* only on e500mc */
168#define DBG_STACK_BASE dbgirq_ctx
169
170#ifdef CONFIG_SMP
171#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
172 mfspr r8,SPRN_PIR; \
173 slwi r8,r8,2; \
174 addis r8,r8,level##_STACK_BASE@ha; \
175 lwz r8,level##_STACK_BASE@l(r8); \
176 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
177#else
178#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
179 lis r8,level##_STACK_BASE@ha; \
180 lwz r8,level##_STACK_BASE@l(r8); \
181 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
182#endif
183
184/*
185 * Exception prolog for critical/machine check exceptions. This is a
186 * little different from the normal exception prolog above since a
187 * critical/machine check exception can potentially occur at any point
188 * during normal exception processing. Thus we cannot use the same SPRG
189 * registers as the normal prolog above. Instead we use a portion of the
190 * critical/machine check exception stack at low physical addresses.
191 */
192#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \
193 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
194 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
195 stw r9,GPR9(r8); /* save various registers */\
196 mfcr r9; /* save CR in r9 for now */\
197 stw r10,GPR10(r8); \
198 stw r11,GPR11(r8); \
199 stw r9,_CCR(r8); /* save CR on stack */\
200 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
201 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
202 BOOKE_CLEAR_BTB(r10) \
203 andi. r11,r11,MSR_PR; \
204 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
205 mtmsr r11; \
206 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
207 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
208 addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE; /* allocate stack frame */\
209 beq 1f; \
210 /* COMING FROM USER MODE */ \
211 stw r9,_CCR(r11); /* save CR */\
212 lwz r10,GPR10(r8); /* copy regs from exception stack */\
213 lwz r9,GPR9(r8); \
214 stw r10,GPR10(r11); \
215 lwz r10,GPR11(r8); \
216 stw r9,GPR9(r11); \
217 stw r10,GPR11(r11); \
218 b 2f; \
219 /* COMING FROM PRIV MODE */ \
2201: mr r11, r8; \
2212: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
222 stw r12,GPR12(r11); /* save various registers */\
223 mflr r10; \
224 stw r10,_LINK(r11); \
225 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
226 stw r12,_DEAR(r11); /* since they may have had stuff */\
227 mfspr r9,SPRN_ESR; /* in them at the point where the */\
228 stw r9,_ESR(r11); /* exception was taken */\
229 mfspr r12,exc_level_srr0; \
230 stw r1,GPR1(r11); \
231 mfspr r9,exc_level_srr1; \
232 stw r1,0(r11); \
233 mr r1,r11; \
234 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
235 COMMON_EXCEPTION_PROLOG_END trapno
236
237#define SAVE_xSRR(xSRR) \
238 mfspr r0,SPRN_##xSRR##0; \
239 stw r0,_##xSRR##0(r1); \
240 mfspr r0,SPRN_##xSRR##1; \
241 stw r0,_##xSRR##1(r1)
242
243
244.macro SAVE_MMU_REGS
245#ifdef CONFIG_PPC_E500
246 mfspr r0,SPRN_MAS0
247 stw r0,MAS0(r1)
248 mfspr r0,SPRN_MAS1
249 stw r0,MAS1(r1)
250 mfspr r0,SPRN_MAS2
251 stw r0,MAS2(r1)
252 mfspr r0,SPRN_MAS3
253 stw r0,MAS3(r1)
254 mfspr r0,SPRN_MAS6
255 stw r0,MAS6(r1)
256#ifdef CONFIG_PHYS_64BIT
257 mfspr r0,SPRN_MAS7
258 stw r0,MAS7(r1)
259#endif /* CONFIG_PHYS_64BIT */
260#endif /* CONFIG_PPC_E500 */
261#ifdef CONFIG_44x
262 mfspr r0,SPRN_MMUCR
263 stw r0,MMUCR(r1)
264#endif
265.endm
266
267#define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \
268 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1)
269#define DEBUG_EXCEPTION_PROLOG(trapno) \
270 EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
271#define MCHECK_EXCEPTION_PROLOG(trapno) \
272 EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \
273 SPRN_MCSRR0, SPRN_MCSRR1)
274
275/*
276 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
277 * being delivered to the host. This exception can only happen
278 * inside a KVM guest -- so we just handle up to the DO_KVM rather
279 * than try to fit this into one of the existing prolog macros.
280 */
281#define GUEST_DOORBELL_EXCEPTION \
282 START_EXCEPTION(GuestDoorbell); \
283 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
284 mfspr r10, SPRN_SPRG_THREAD; \
285 stw r11, THREAD_NORMSAVE(0)(r10); \
286 mfspr r11, SPRN_SRR1; \
287 stw r13, THREAD_NORMSAVE(2)(r10); \
288 mfcr r13; /* save CR in r13 for now */\
289 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
290 trap
291
292/*
293 * Exception vectors.
294 */
295#define START_EXCEPTION(label) \
296 .align 5; \
297label:
298
299#define EXCEPTION(n, intno, label, hdlr) \
300 START_EXCEPTION(label); \
301 NORMAL_EXCEPTION_PROLOG(n, intno); \
302 prepare_transfer_to_handler; \
303 bl hdlr; \
304 b interrupt_return
305
306#define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
307 START_EXCEPTION(label); \
308 CRITICAL_EXCEPTION_PROLOG(n, intno); \
309 SAVE_MMU_REGS; \
310 SAVE_xSRR(SRR); \
311 prepare_transfer_to_handler; \
312 bl hdlr; \
313 b ret_from_crit_exc
314
315#define MCHECK_EXCEPTION(n, label, hdlr) \
316 START_EXCEPTION(label); \
317 MCHECK_EXCEPTION_PROLOG(n); \
318 mfspr r5,SPRN_ESR; \
319 stw r5,_ESR(r11); \
320 SAVE_xSRR(DSRR); \
321 SAVE_xSRR(CSRR); \
322 SAVE_MMU_REGS; \
323 SAVE_xSRR(SRR); \
324 prepare_transfer_to_handler; \
325 bl hdlr; \
326 b ret_from_mcheck_exc
327
328/* Check for a single step debug exception while in an exception
329 * handler before state has been saved. This is to catch the case
330 * where an instruction that we are trying to single step causes
331 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
332 * the exception handler generates a single step debug exception.
333 *
334 * If we get a debug trap on the first instruction of an exception handler,
335 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
336 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
337 * The exception handler was handling a non-critical interrupt, so it will
338 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
339 * the MSR_DE bit set.
340 */
341#define DEBUG_DEBUG_EXCEPTION \
342 START_EXCEPTION(DebugDebug); \
343 DEBUG_EXCEPTION_PROLOG(2000); \
344 \
345 /* \
346 * If there is a single step or branch-taken exception in an \
347 * exception entry sequence, it was probably meant to apply to \
348 * the code where the exception occurred (since exception entry \
349 * doesn't turn off DE automatically). We simulate the effect \
350 * of turning off DE on entry to an exception handler by turning \
351 * off DE in the DSRR1 value and clearing the debug status. \
352 */ \
353 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
354 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
355 beq+ 2f; \
356 \
357 lis r10,interrupt_base@h; /* check if exception in vectors */ \
358 ori r10,r10,interrupt_base@l; \
359 cmplw r12,r10; \
360 blt+ 2f; /* addr below exception vectors */ \
361 \
362 lis r10,interrupt_end@h; \
363 ori r10,r10,interrupt_end@l; \
364 cmplw r12,r10; \
365 bgt+ 2f; /* addr above exception vectors */ \
366 \
367 /* here it looks like we got an inappropriate debug exception. */ \
3681: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
369 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
370 mtspr SPRN_DBSR,r10; \
371 /* restore state and get out */ \
372 lwz r10,_CCR(r11); \
373 lwz r0,GPR0(r11); \
374 lwz r1,GPR1(r11); \
375 mtcrf 0x80,r10; \
376 mtspr SPRN_DSRR0,r12; \
377 mtspr SPRN_DSRR1,r9; \
378 lwz r9,GPR9(r11); \
379 lwz r12,GPR12(r11); \
380 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
381 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
382 lwz r10,GPR10(r8); \
383 lwz r11,GPR11(r8); \
384 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
385 \
386 PPC_RFDI; \
387 b .; \
388 \
389 /* continue normal handling for a debug exception... */ \
3902: mfspr r4,SPRN_DBSR; \
391 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
392 SAVE_xSRR(CSRR); \
393 SAVE_MMU_REGS; \
394 SAVE_xSRR(SRR); \
395 prepare_transfer_to_handler; \
396 bl DebugException; \
397 b ret_from_debug_exc
398
399#define DEBUG_CRIT_EXCEPTION \
400 START_EXCEPTION(DebugCrit); \
401 CRITICAL_EXCEPTION_PROLOG(2000,DEBUG); \
402 \
403 /* \
404 * If there is a single step or branch-taken exception in an \
405 * exception entry sequence, it was probably meant to apply to \
406 * the code where the exception occurred (since exception entry \
407 * doesn't turn off DE automatically). We simulate the effect \
408 * of turning off DE on entry to an exception handler by turning \
409 * off DE in the CSRR1 value and clearing the debug status. \
410 */ \
411 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
412 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
413 beq+ 2f; \
414 \
415 lis r10,interrupt_base@h; /* check if exception in vectors */ \
416 ori r10,r10,interrupt_base@l; \
417 cmplw r12,r10; \
418 blt+ 2f; /* addr below exception vectors */ \
419 \
420 lis r10,interrupt_end@h; \
421 ori r10,r10,interrupt_end@l; \
422 cmplw r12,r10; \
423 bgt+ 2f; /* addr above exception vectors */ \
424 \
425 /* here it looks like we got an inappropriate debug exception. */ \
4261: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
427 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
428 mtspr SPRN_DBSR,r10; \
429 /* restore state and get out */ \
430 lwz r10,_CCR(r11); \
431 lwz r0,GPR0(r11); \
432 lwz r1,GPR1(r11); \
433 mtcrf 0x80,r10; \
434 mtspr SPRN_CSRR0,r12; \
435 mtspr SPRN_CSRR1,r9; \
436 lwz r9,GPR9(r11); \
437 lwz r12,GPR12(r11); \
438 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
439 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
440 lwz r10,GPR10(r8); \
441 lwz r11,GPR11(r8); \
442 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
443 \
444 rfci; \
445 b .; \
446 \
447 /* continue normal handling for a critical exception... */ \
4482: mfspr r4,SPRN_DBSR; \
449 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
450 SAVE_MMU_REGS; \
451 SAVE_xSRR(SRR); \
452 prepare_transfer_to_handler; \
453 bl DebugException; \
454 b ret_from_crit_exc
455
456#define DATA_STORAGE_EXCEPTION \
457 START_EXCEPTION(DataStorage) \
458 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE); \
459 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
460 stw r5,_ESR(r11); \
461 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
462 stw r4, _DEAR(r11); \
463 prepare_transfer_to_handler; \
464 bl do_page_fault; \
465 b interrupt_return
466
467/*
468 * Instruction TLB Error interrupt handlers may call InstructionStorage
469 * directly without clearing ESR, so the ESR at this point may be left over
470 * from a prior interrupt.
471 *
472 * In any case, do_page_fault for BOOK3E does not use ESR and always expects
473 * dsisr to be 0. ESR_DST from a prior store in particular would confuse fault
474 * handling.
475 */
476#define INSTRUCTION_STORAGE_EXCEPTION \
477 START_EXCEPTION(InstructionStorage) \
478 NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
479 li r5,0; /* Store 0 in regs->esr (dsisr) */ \
480 stw r5,_ESR(r11); \
481 stw r12, _DEAR(r11); /* Set regs->dear (dar) to SRR0 */ \
482 prepare_transfer_to_handler; \
483 bl do_page_fault; \
484 b interrupt_return
485
486#define ALIGNMENT_EXCEPTION \
487 START_EXCEPTION(Alignment) \
488 NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT); \
489 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
490 stw r4,_DEAR(r11); \
491 prepare_transfer_to_handler; \
492 bl alignment_exception; \
493 REST_NVGPRS(r1); \
494 b interrupt_return
495
496#define PROGRAM_EXCEPTION \
497 START_EXCEPTION(Program) \
498 NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM); \
499 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
500 stw r4,_ESR(r11); \
501 prepare_transfer_to_handler; \
502 bl program_check_exception; \
503 REST_NVGPRS(r1); \
504 b interrupt_return
505
506#define DECREMENTER_EXCEPTION \
507 START_EXCEPTION(Decrementer) \
508 NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER); \
509 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
510 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
511 prepare_transfer_to_handler; \
512 bl timer_interrupt; \
513 b interrupt_return
514
515#define FP_UNAVAILABLE_EXCEPTION \
516 START_EXCEPTION(FloatingPointUnavailable) \
517 NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL); \
518 beq 1f; \
519 bl load_up_fpu; /* if from user, just load it up */ \
520 b fast_exception_return; \
5211: prepare_transfer_to_handler; \
522 bl kernel_fp_unavailable_exception; \
523 b interrupt_return
524
525#endif /* __ASSEMBLY__ */
526#endif /* __HEAD_BOOKE_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __HEAD_BOOKE_H__
3#define __HEAD_BOOKE_H__
4
5#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6#include <asm/kvm_asm.h>
7#include <asm/kvm_booke_hv_asm.h>
8
9#ifdef __ASSEMBLY__
10
11/*
12 * Macros used for common Book-e exception handling
13 */
14
15#define SET_IVOR(vector_number, vector_label) \
16 li r26,vector_label@l; \
17 mtspr SPRN_IVOR##vector_number,r26; \
18 sync
19
20#if (THREAD_SHIFT < 15)
21#define ALLOC_STACK_FRAME(reg, val) \
22 addi reg,reg,val
23#else
24#define ALLOC_STACK_FRAME(reg, val) \
25 addis reg,reg,val@ha; \
26 addi reg,reg,val@l
27#endif
28
29/*
30 * Macro used to get to thread save registers.
31 * Note that entries 0-3 are used for the prolog code, and the remaining
32 * entries are available for specific exception use in the event a handler
33 * requires more than 4 scratch registers.
34 */
35#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
36
37#ifdef CONFIG_PPC_FSL_BOOK3E
38#define BOOKE_CLEAR_BTB(reg) \
39START_BTB_FLUSH_SECTION \
40 BTB_FLUSH(reg) \
41END_BTB_FLUSH_SECTION
42#else
43#define BOOKE_CLEAR_BTB(reg)
44#endif
45
46
47#define NORMAL_EXCEPTION_PROLOG(intno) \
48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
49 mfspr r10, SPRN_SPRG_THREAD; \
50 stw r11, THREAD_NORMSAVE(0)(r10); \
51 stw r13, THREAD_NORMSAVE(2)(r10); \
52 mfcr r13; /* save CR in r13 for now */\
53 mfspr r11, SPRN_SRR1; \
54 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
55 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
56 mr r11, r1; \
57 beq 1f; \
58 BOOKE_CLEAR_BTB(r11) \
59 /* if from user, start at top of this thread's kernel stack */ \
60 lwz r11, TASK_STACK - THREAD(r10); \
61 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
621 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
63 stw r13, _CCR(r11); /* save various registers */ \
64 stw r12,GPR12(r11); \
65 stw r9,GPR9(r11); \
66 mfspr r13, SPRN_SPRG_RSCRATCH0; \
67 stw r13, GPR10(r11); \
68 lwz r12, THREAD_NORMSAVE(0)(r10); \
69 stw r12,GPR11(r11); \
70 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
71 mflr r10; \
72 stw r10,_LINK(r11); \
73 mfspr r12,SPRN_SRR0; \
74 stw r1, GPR1(r11); \
75 mfspr r9,SPRN_SRR1; \
76 stw r1, 0(r11); \
77 mr r1, r11; \
78 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
79 stw r0,GPR0(r11); \
80 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
81 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
82 stw r10, 8(r11); \
83 SAVE_4GPRS(3, r11); \
84 SAVE_2GPRS(7, r11)
85
86.macro SYSCALL_ENTRY trapno intno srr1
87 mfspr r10, SPRN_SPRG_THREAD
88#ifdef CONFIG_KVM_BOOKE_HV
89BEGIN_FTR_SECTION
90 mtspr SPRN_SPRG_WSCRATCH0, r10
91 stw r11, THREAD_NORMSAVE(0)(r10)
92 stw r13, THREAD_NORMSAVE(2)(r10)
93 mfcr r13 /* save CR in r13 for now */
94 mfspr r11, SPRN_SRR1
95 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
96 bf 3, 1975f
97 b kvmppc_handler_\intno\()_\srr1
981975:
99 mr r12, r13
100 lwz r13, THREAD_NORMSAVE(2)(r10)
101FTR_SECTION_ELSE
102#endif
103 mfcr r12
104#ifdef CONFIG_KVM_BOOKE_HV
105ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
106#endif
107 BOOKE_CLEAR_BTB(r11)
108 lwz r11, TASK_STACK - THREAD(r10)
109 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
110 ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
111 stw r12, _CCR(r11) /* save various registers */
112 mflr r12
113 stw r12,_LINK(r11)
114 mfspr r12,SPRN_SRR0
115 stw r1, GPR1(r11)
116 mfspr r9,SPRN_SRR1
117 stw r1, 0(r11)
118 mr r1, r11
119 stw r12,_NIP(r11)
120 rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
121 lis r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
122 stw r2,GPR2(r11)
123 addi r12, r12, STACK_FRAME_REGS_MARKER@l
124 stw r9,_MSR(r11)
125 li r2, \trapno + 1
126 stw r12, 8(r11)
127 stw r2,_TRAP(r11)
128 SAVE_GPR(0, r11)
129 SAVE_4GPRS(3, r11)
130 SAVE_2GPRS(7, r11)
131
132 addi r11,r1,STACK_FRAME_OVERHEAD
133 addi r2,r10,-THREAD
134 stw r11,PT_REGS(r10)
135 /* Check to see if the dbcr0 register is set up to debug. Use the
136 internal debug mode bit to do this. */
137 lwz r12,THREAD_DBCR0(r10)
138 andis. r12,r12,DBCR0_IDM@h
139 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
140 beq+ 3f
141 /* From user and task is ptraced - load up global dbcr0 */
142 li r12,-1 /* clear all pending debug events */
143 mtspr SPRN_DBSR,r12
144 lis r11,global_dbcr0@ha
145 tophys(r11,r11)
146 addi r11,r11,global_dbcr0@l
147#ifdef CONFIG_SMP
148 lwz r10, TASK_CPU(r2)
149 slwi r10, r10, 3
150 add r11, r11, r10
151#endif
152 lwz r12,0(r11)
153 mtspr SPRN_DBCR0,r12
154 lwz r12,4(r11)
155 addi r12,r12,-1
156 stw r12,4(r11)
157
1583:
159 tovirt(r2, r2) /* set r2 to current */
160 lis r11, transfer_to_syscall@h
161 ori r11, r11, transfer_to_syscall@l
162#ifdef CONFIG_TRACE_IRQFLAGS
163 /*
164 * If MSR is changing we need to keep interrupts disabled at this point
165 * otherwise we might risk taking an interrupt before we tell lockdep
166 * they are enabled.
167 */
168 lis r10, MSR_KERNEL@h
169 ori r10, r10, MSR_KERNEL@l
170 rlwimi r10, r9, 0, MSR_EE
171#else
172 lis r10, (MSR_KERNEL | MSR_EE)@h
173 ori r10, r10, (MSR_KERNEL | MSR_EE)@l
174#endif
175 mtspr SPRN_SRR1,r10
176 mtspr SPRN_SRR0,r11
177 SYNC
178 RFI /* jump to handler, enable MMU */
179.endm
180
181/* To handle the additional exception priority levels on 40x and Book-E
182 * processors we allocate a stack per additional priority level.
183 *
184 * On 40x critical is the only additional level
185 * On 44x/e500 we have critical and machine check
186 * On e200 we have critical and debug (machine check occurs via critical)
187 *
188 * Additionally we reserve a SPRG for each priority level so we can free up a
189 * GPR to use as the base for indirect access to the exception stacks. This
190 * is necessary since the MMU is always on, for Book-E parts, and the stacks
191 * are offset from KERNELBASE.
192 *
193 * There is some space optimization to be had here if desired. However
194 * to allow for a common kernel with support for debug exceptions either
195 * going to critical or their own debug level we aren't currently
196 * providing configurations that micro-optimize space usage.
197 */
198
199#define MC_STACK_BASE mcheckirq_ctx
200#define CRIT_STACK_BASE critirq_ctx
201
202/* only on e500mc/e200 */
203#define DBG_STACK_BASE dbgirq_ctx
204
205#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
206
207#ifdef CONFIG_SMP
208#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
209 mfspr r8,SPRN_PIR; \
210 slwi r8,r8,2; \
211 addis r8,r8,level##_STACK_BASE@ha; \
212 lwz r8,level##_STACK_BASE@l(r8); \
213 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
214#else
215#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
216 lis r8,level##_STACK_BASE@ha; \
217 lwz r8,level##_STACK_BASE@l(r8); \
218 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
219#endif
220
221/*
222 * Exception prolog for critical/machine check exceptions. This is a
223 * little different from the normal exception prolog above since a
224 * critical/machine check exception can potentially occur at any point
225 * during normal exception processing. Thus we cannot use the same SPRG
226 * registers as the normal prolog above. Instead we use a portion of the
227 * critical/machine check exception stack at low physical addresses.
228 */
229#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
230 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
231 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
232 stw r9,GPR9(r8); /* save various registers */\
233 mfcr r9; /* save CR in r9 for now */\
234 stw r10,GPR10(r8); \
235 stw r11,GPR11(r8); \
236 stw r9,_CCR(r8); /* save CR on stack */\
237 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
238 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
239 BOOKE_CLEAR_BTB(r10) \
240 andi. r11,r11,MSR_PR; \
241 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
242 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
243 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
244 beq 1f; \
245 /* COMING FROM USER MODE */ \
246 stw r9,_CCR(r11); /* save CR */\
247 lwz r10,GPR10(r8); /* copy regs from exception stack */\
248 lwz r9,GPR9(r8); \
249 stw r10,GPR10(r11); \
250 lwz r10,GPR11(r8); \
251 stw r9,GPR9(r11); \
252 stw r10,GPR11(r11); \
253 b 2f; \
254 /* COMING FROM PRIV MODE */ \
2551: mr r11, r8; \
2562: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
257 stw r12,GPR12(r11); /* save various registers */\
258 mflr r10; \
259 stw r10,_LINK(r11); \
260 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
261 stw r12,_DEAR(r11); /* since they may have had stuff */\
262 mfspr r9,SPRN_ESR; /* in them at the point where the */\
263 stw r9,_ESR(r11); /* exception was taken */\
264 mfspr r12,exc_level_srr0; \
265 stw r1,GPR1(r11); \
266 mfspr r9,exc_level_srr1; \
267 stw r1,0(r11); \
268 mr r1,r11; \
269 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
270 stw r0,GPR0(r11); \
271 SAVE_4GPRS(3, r11); \
272 SAVE_2GPRS(7, r11)
273
274#define CRITICAL_EXCEPTION_PROLOG(intno) \
275 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
276#define DEBUG_EXCEPTION_PROLOG \
277 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
278#define MCHECK_EXCEPTION_PROLOG \
279 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
280 SPRN_MCSRR0, SPRN_MCSRR1)
281
282/*
283 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
284 * being delivered to the host. This exception can only happen
285 * inside a KVM guest -- so we just handle up to the DO_KVM rather
286 * than try to fit this into one of the existing prolog macros.
287 */
288#define GUEST_DOORBELL_EXCEPTION \
289 START_EXCEPTION(GuestDoorbell); \
290 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
291 mfspr r10, SPRN_SPRG_THREAD; \
292 stw r11, THREAD_NORMSAVE(0)(r10); \
293 mfspr r11, SPRN_SRR1; \
294 stw r13, THREAD_NORMSAVE(2)(r10); \
295 mfcr r13; /* save CR in r13 for now */\
296 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
297 trap
298
299/*
300 * Exception vectors.
301 */
302#define START_EXCEPTION(label) \
303 .align 5; \
304label:
305
306#define EXCEPTION(n, intno, label, hdlr, xfer) \
307 START_EXCEPTION(label); \
308 NORMAL_EXCEPTION_PROLOG(intno); \
309 addi r3,r1,STACK_FRAME_OVERHEAD; \
310 xfer(n, hdlr)
311
312#define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
313 START_EXCEPTION(label); \
314 CRITICAL_EXCEPTION_PROLOG(intno); \
315 addi r3,r1,STACK_FRAME_OVERHEAD; \
316 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
317 crit_transfer_to_handler, ret_from_crit_exc)
318
319#define MCHECK_EXCEPTION(n, label, hdlr) \
320 START_EXCEPTION(label); \
321 MCHECK_EXCEPTION_PROLOG; \
322 mfspr r5,SPRN_ESR; \
323 stw r5,_ESR(r11); \
324 addi r3,r1,STACK_FRAME_OVERHEAD; \
325 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
326 mcheck_transfer_to_handler, ret_from_mcheck_exc)
327
328#define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \
329 li r10,trap; \
330 stw r10,_TRAP(r11); \
331 lis r10,msr@h; \
332 ori r10,r10,msr@l; \
333 bl tfer; \
334 .long hdlr; \
335 .long ret
336
337#define EXC_XFER_STD(n, hdlr) \
338 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
339 ret_from_except_full)
340
341#define EXC_XFER_LITE(n, hdlr) \
342 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
343 ret_from_except)
344
345/* Check for a single step debug exception while in an exception
346 * handler before state has been saved. This is to catch the case
347 * where an instruction that we are trying to single step causes
348 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
349 * the exception handler generates a single step debug exception.
350 *
351 * If we get a debug trap on the first instruction of an exception handler,
352 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
353 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
354 * The exception handler was handling a non-critical interrupt, so it will
355 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
356 * the MSR_DE bit set.
357 */
358#define DEBUG_DEBUG_EXCEPTION \
359 START_EXCEPTION(DebugDebug); \
360 DEBUG_EXCEPTION_PROLOG; \
361 \
362 /* \
363 * If there is a single step or branch-taken exception in an \
364 * exception entry sequence, it was probably meant to apply to \
365 * the code where the exception occurred (since exception entry \
366 * doesn't turn off DE automatically). We simulate the effect \
367 * of turning off DE on entry to an exception handler by turning \
368 * off DE in the DSRR1 value and clearing the debug status. \
369 */ \
370 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
371 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
372 beq+ 2f; \
373 \
374 lis r10,interrupt_base@h; /* check if exception in vectors */ \
375 ori r10,r10,interrupt_base@l; \
376 cmplw r12,r10; \
377 blt+ 2f; /* addr below exception vectors */ \
378 \
379 lis r10,interrupt_end@h; \
380 ori r10,r10,interrupt_end@l; \
381 cmplw r12,r10; \
382 bgt+ 2f; /* addr above exception vectors */ \
383 \
384 /* here it looks like we got an inappropriate debug exception. */ \
3851: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
386 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
387 mtspr SPRN_DBSR,r10; \
388 /* restore state and get out */ \
389 lwz r10,_CCR(r11); \
390 lwz r0,GPR0(r11); \
391 lwz r1,GPR1(r11); \
392 mtcrf 0x80,r10; \
393 mtspr SPRN_DSRR0,r12; \
394 mtspr SPRN_DSRR1,r9; \
395 lwz r9,GPR9(r11); \
396 lwz r12,GPR12(r11); \
397 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
398 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
399 lwz r10,GPR10(r8); \
400 lwz r11,GPR11(r8); \
401 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
402 \
403 PPC_RFDI; \
404 b .; \
405 \
406 /* continue normal handling for a debug exception... */ \
4072: mfspr r4,SPRN_DBSR; \
408 addi r3,r1,STACK_FRAME_OVERHEAD; \
409 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)
410
411#define DEBUG_CRIT_EXCEPTION \
412 START_EXCEPTION(DebugCrit); \
413 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
414 \
415 /* \
416 * If there is a single step or branch-taken exception in an \
417 * exception entry sequence, it was probably meant to apply to \
418 * the code where the exception occurred (since exception entry \
419 * doesn't turn off DE automatically). We simulate the effect \
420 * of turning off DE on entry to an exception handler by turning \
421 * off DE in the CSRR1 value and clearing the debug status. \
422 */ \
423 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
424 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
425 beq+ 2f; \
426 \
427 lis r10,interrupt_base@h; /* check if exception in vectors */ \
428 ori r10,r10,interrupt_base@l; \
429 cmplw r12,r10; \
430 blt+ 2f; /* addr below exception vectors */ \
431 \
432 lis r10,interrupt_end@h; \
433 ori r10,r10,interrupt_end@l; \
434 cmplw r12,r10; \
435 bgt+ 2f; /* addr above exception vectors */ \
436 \
437 /* here it looks like we got an inappropriate debug exception. */ \
4381: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
439 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
440 mtspr SPRN_DBSR,r10; \
441 /* restore state and get out */ \
442 lwz r10,_CCR(r11); \
443 lwz r0,GPR0(r11); \
444 lwz r1,GPR1(r11); \
445 mtcrf 0x80,r10; \
446 mtspr SPRN_CSRR0,r12; \
447 mtspr SPRN_CSRR1,r9; \
448 lwz r9,GPR9(r11); \
449 lwz r12,GPR12(r11); \
450 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
451 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
452 lwz r10,GPR10(r8); \
453 lwz r11,GPR11(r8); \
454 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
455 \
456 rfci; \
457 b .; \
458 \
459 /* continue normal handling for a critical exception... */ \
4602: mfspr r4,SPRN_DBSR; \
461 addi r3,r1,STACK_FRAME_OVERHEAD; \
462 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)
463
464#define DATA_STORAGE_EXCEPTION \
465 START_EXCEPTION(DataStorage) \
466 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
467 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
468 stw r5,_ESR(r11); \
469 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
470 EXC_XFER_LITE(0x0300, handle_page_fault)
471
472#define INSTRUCTION_STORAGE_EXCEPTION \
473 START_EXCEPTION(InstructionStorage) \
474 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
475 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
476 stw r5,_ESR(r11); \
477 mr r4,r12; /* Pass SRR0 as arg2 */ \
478 li r5,0; /* Pass zero as arg3 */ \
479 EXC_XFER_LITE(0x0400, handle_page_fault)
480
481#define ALIGNMENT_EXCEPTION \
482 START_EXCEPTION(Alignment) \
483 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
484 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
485 stw r4,_DEAR(r11); \
486 addi r3,r1,STACK_FRAME_OVERHEAD; \
487 EXC_XFER_STD(0x0600, alignment_exception)
488
489#define PROGRAM_EXCEPTION \
490 START_EXCEPTION(Program) \
491 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
492 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
493 stw r4,_ESR(r11); \
494 addi r3,r1,STACK_FRAME_OVERHEAD; \
495 EXC_XFER_STD(0x0700, program_check_exception)
496
497#define DECREMENTER_EXCEPTION \
498 START_EXCEPTION(Decrementer) \
499 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
500 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
501 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
502 addi r3,r1,STACK_FRAME_OVERHEAD; \
503 EXC_XFER_LITE(0x0900, timer_interrupt)
504
505#define FP_UNAVAILABLE_EXCEPTION \
506 START_EXCEPTION(FloatingPointUnavailable) \
507 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
508 beq 1f; \
509 bl load_up_fpu; /* if from user, just load it up */ \
510 b fast_exception_return; \
5111: addi r3,r1,STACK_FRAME_OVERHEAD; \
512 EXC_XFER_STD(0x800, kernel_fp_unavailable_exception)
513
514#else /* __ASSEMBLY__ */
515struct exception_regs {
516 unsigned long mas0;
517 unsigned long mas1;
518 unsigned long mas2;
519 unsigned long mas3;
520 unsigned long mas6;
521 unsigned long mas7;
522 unsigned long srr0;
523 unsigned long srr1;
524 unsigned long csrr0;
525 unsigned long csrr1;
526 unsigned long dsrr0;
527 unsigned long dsrr1;
528 unsigned long saved_ksp_limit;
529};
530
531/* ensure this structure is always sized to a multiple of the stack alignment */
532#define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
533
534#endif /* __ASSEMBLY__ */
535#endif /* __HEAD_BOOKE_H__ */