1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 *  Boot code and exception vectors for Book3E processors
   4 *
   5 *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
   6 */
   7
   8#include <linux/threads.h>
   9#include <asm/reg.h>
  10#include <asm/page.h>
  11#include <asm/ppc_asm.h>
  12#include <asm/asm-offsets.h>
  13#include <asm/cputable.h>
  14#include <asm/setup.h>
  15#include <asm/thread_info.h>
  16#include <asm/reg_a2.h>
  17#include <asm/exception-64e.h>
  18#include <asm/bug.h>
  19#include <asm/irqflags.h>
  20#include <asm/ptrace.h>
  21#include <asm/ppc-opcode.h>
  22#include <asm/mmu.h>
  23#include <asm/hw_irq.h>
  24#include <asm/kvm_asm.h>
  25#include <asm/kvm_booke_hv_asm.h>
  26#include <asm/feature-fixups.h>
  27#include <asm/context_tracking.h>
  28
  29/* 64e interrupt returns always use SRR registers */
  30#define fast_interrupt_return fast_interrupt_return_srr
  31#define interrupt_return interrupt_return_srr
  32
  33/* XXX This will ultimately add space for a special exception save
  34 *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
  35 *     when taking special interrupts. For now we don't support that,
  36 *     special interrupts from within a non-standard level will probably
  37 *     blow you up
  38 */
  39#define SPECIAL_EXC_SRR0	0
  40#define SPECIAL_EXC_SRR1	1
  41#define SPECIAL_EXC_SPRG_GEN	2
  42#define SPECIAL_EXC_SPRG_TLB	3
  43#define SPECIAL_EXC_MAS0	4
  44#define SPECIAL_EXC_MAS1	5
  45#define SPECIAL_EXC_MAS2	6
  46#define SPECIAL_EXC_MAS3	7
  47#define SPECIAL_EXC_MAS6	8
  48#define SPECIAL_EXC_MAS7	9
  49#define SPECIAL_EXC_MAS5	10	/* E.HV only */
  50#define SPECIAL_EXC_MAS8	11	/* E.HV only */
  51#define SPECIAL_EXC_IRQHAPPENED	12
  52#define SPECIAL_EXC_DEAR	13
  53#define SPECIAL_EXC_ESR		14
  54#define SPECIAL_EXC_SOFTE	15
  55#define SPECIAL_EXC_CSRR0	16
  56#define SPECIAL_EXC_CSRR1	17
  57/* must be even to keep 16-byte stack alignment */
  58#define SPECIAL_EXC_END		18
  59
  60#define SPECIAL_EXC_FRAME_SIZE	(INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
  61#define SPECIAL_EXC_FRAME_OFFS  (INT_FRAME_SIZE - 288)
  62
  63#define SPECIAL_EXC_STORE(reg, name) \
  64	std	reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  65
  66#define SPECIAL_EXC_LOAD(reg, name) \
  67	ld	reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  68
  69special_reg_save:
 
 
 
  70	/*
  71	 * We only need (or have stack space) to save this stuff if
  72	 * we interrupted the kernel.
  73	 */
  74	ld	r3,_MSR(r1)
  75	andi.	r3,r3,MSR_PR
  76	bnelr
  77
  78	/*
  79	 * Advance to the next TLB exception frame for handler
  80	 * types that don't do it automatically.
  81	 */
  82	LOAD_REG_ADDR(r11,extlb_level_exc)
  83	lwz	r12,0(r11)
  84	mfspr	r10,SPRN_SPRG_TLB_EXFRAME
  85	add	r10,r10,r12
  86	mtspr	SPRN_SPRG_TLB_EXFRAME,r10
  87
  88	/*
  89	 * Save registers needed to allow nesting of certain exceptions
  90	 * (such as TLB misses) inside special exception levels
  91	 */
  92	mfspr	r10,SPRN_SRR0
  93	SPECIAL_EXC_STORE(r10,SRR0)
  94	mfspr	r10,SPRN_SRR1
  95	SPECIAL_EXC_STORE(r10,SRR1)
  96	mfspr	r10,SPRN_SPRG_GEN_SCRATCH
  97	SPECIAL_EXC_STORE(r10,SPRG_GEN)
  98	mfspr	r10,SPRN_SPRG_TLB_SCRATCH
  99	SPECIAL_EXC_STORE(r10,SPRG_TLB)
 100	mfspr	r10,SPRN_MAS0
 101	SPECIAL_EXC_STORE(r10,MAS0)
 102	mfspr	r10,SPRN_MAS1
 103	SPECIAL_EXC_STORE(r10,MAS1)
 104	mfspr	r10,SPRN_MAS2
 105	SPECIAL_EXC_STORE(r10,MAS2)
 106	mfspr	r10,SPRN_MAS3
 107	SPECIAL_EXC_STORE(r10,MAS3)
 108	mfspr	r10,SPRN_MAS6
 109	SPECIAL_EXC_STORE(r10,MAS6)
 110	mfspr	r10,SPRN_MAS7
 111	SPECIAL_EXC_STORE(r10,MAS7)
 112BEGIN_FTR_SECTION
 113	mfspr	r10,SPRN_MAS5
 114	SPECIAL_EXC_STORE(r10,MAS5)
 115	mfspr	r10,SPRN_MAS8
 116	SPECIAL_EXC_STORE(r10,MAS8)
 117
 118	/* MAS5/8 could have inappropriate values if we interrupted KVM code */
 119	li	r10,0
 120	mtspr	SPRN_MAS5,r10
 121	mtspr	SPRN_MAS8,r10
 122END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 
 
 123	mfspr	r10,SPRN_DEAR
 124	SPECIAL_EXC_STORE(r10,DEAR)
 125	mfspr	r10,SPRN_ESR
 126	SPECIAL_EXC_STORE(r10,ESR)
 127
 
 
 128	ld	r10,_NIP(r1)
 129	SPECIAL_EXC_STORE(r10,CSRR0)
 130	ld	r10,_MSR(r1)
 131	SPECIAL_EXC_STORE(r10,CSRR1)
 132
 133	blr
 134
 135ret_from_level_except:
 136	ld	r3,_MSR(r1)
 137	andi.	r3,r3,MSR_PR
 138	beq	1f
 139	REST_NVGPRS(r1)
 140	b	interrupt_return
 1411:
 142
 143	LOAD_REG_ADDR(r11,extlb_level_exc)
 144	lwz	r12,0(r11)
 145	mfspr	r10,SPRN_SPRG_TLB_EXFRAME
 146	sub	r10,r10,r12
 147	mtspr	SPRN_SPRG_TLB_EXFRAME,r10
 148
 149	/*
 150	 * It's possible that the special level exception interrupted a
 151	 * TLB miss handler, and inserted the same entry that the
 152	 * interrupted handler was about to insert.  On CPUs without TLB
 153	 * write conditional, this can result in a duplicate TLB entry.
 154	 * Wipe all non-bolted entries to be safe.
 155	 *
 156	 * Note that this doesn't protect against any TLB misses
 157	 * we may take accessing the stack from here to the end of
 158	 * the special level exception.  It's not clear how we can
 159	 * reasonably protect against that, but only CPUs with
 160	 * neither TLB write conditional nor bolted kernel memory
 161	 * are affected.  Do any such CPUs even exist?
 162	 */
 163	PPC_TLBILX_ALL(0,R0)
 164
 165	REST_NVGPRS(r1)
 166
 167	SPECIAL_EXC_LOAD(r10,SRR0)
 168	mtspr	SPRN_SRR0,r10
 169	SPECIAL_EXC_LOAD(r10,SRR1)
 170	mtspr	SPRN_SRR1,r10
 171	SPECIAL_EXC_LOAD(r10,SPRG_GEN)
 172	mtspr	SPRN_SPRG_GEN_SCRATCH,r10
 173	SPECIAL_EXC_LOAD(r10,SPRG_TLB)
 174	mtspr	SPRN_SPRG_TLB_SCRATCH,r10
 175	SPECIAL_EXC_LOAD(r10,MAS0)
 176	mtspr	SPRN_MAS0,r10
 177	SPECIAL_EXC_LOAD(r10,MAS1)
 178	mtspr	SPRN_MAS1,r10
 179	SPECIAL_EXC_LOAD(r10,MAS2)
 180	mtspr	SPRN_MAS2,r10
 181	SPECIAL_EXC_LOAD(r10,MAS3)
 182	mtspr	SPRN_MAS3,r10
 183	SPECIAL_EXC_LOAD(r10,MAS6)
 184	mtspr	SPRN_MAS6,r10
 185	SPECIAL_EXC_LOAD(r10,MAS7)
 186	mtspr	SPRN_MAS7,r10
 187BEGIN_FTR_SECTION
 188	SPECIAL_EXC_LOAD(r10,MAS5)
 189	mtspr	SPRN_MAS5,r10
 190	SPECIAL_EXC_LOAD(r10,MAS8)
 191	mtspr	SPRN_MAS8,r10
 192END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 193
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 194	SPECIAL_EXC_LOAD(r10,DEAR)
 195	mtspr	SPRN_DEAR,r10
 196	SPECIAL_EXC_LOAD(r10,ESR)
 197	mtspr	SPRN_ESR,r10
 198
 199	stdcx.	r0,0,r1		/* to clear the reservation */
 200
 201	REST_GPRS(2, 9, r1)
 
 202
 203	ld	r10,_CTR(r1)
 204	ld	r11,_XER(r1)
 205	mtctr	r10
 206	mtxer	r11
 207
 208	blr
 209
 210.macro ret_from_level srr0 srr1 paca_ex scratch
 211	bl	ret_from_level_except
 212
 213	ld	r10,_LINK(r1)
 214	ld	r11,_CCR(r1)
 215	ld	r0,GPR13(r1)
 216	mtlr	r10
 217	mtcr	r11
 218
 219	REST_GPRS(10, 12, r1)
 
 
 220	mtspr	\scratch,r0
 221
 222	std	r10,\paca_ex+EX_R10(r13);
 223	std	r11,\paca_ex+EX_R11(r13);
 224	ld	r10,_NIP(r1)
 225	ld	r11,_MSR(r1)
 226	REST_GPR(0, r1)
 227	REST_GPR(1, r1)
 228	mtspr	\srr0,r10
 229	mtspr	\srr1,r11
 230	ld	r10,\paca_ex+EX_R10(r13)
 231	ld	r11,\paca_ex+EX_R11(r13)
 232	mfspr	r13,\scratch
 233.endm
 234
 235ret_from_crit_except:
 236	ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
 237	rfci
 238
 239ret_from_mc_except:
 240	ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
 241	rfmci
 242
 243/* Exception prolog code for all exceptions */
 244#define EXCEPTION_PROLOG(n, intnum, type, addition)	    		    \
 245	mtspr	SPRN_SPRG_##type##_SCRATCH,r13;	/* get spare registers */   \
 246	mfspr	r13,SPRN_SPRG_PACA;	/* get PACA */			    \
 247	std	r10,PACA_EX##type+EX_R10(r13);				    \
 248	std	r11,PACA_EX##type+EX_R11(r13);				    \
 249	mfcr	r10;			/* save CR */			    \
 250	mfspr	r11,SPRN_##type##_SRR1;/* what are we coming from */	    \
 251	DO_KVM	intnum,SPRN_##type##_SRR1;    /* KVM hook */		    \
 252	stw	r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 253	addition;			/* additional code for that exc. */ \
 254	std	r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 255	type##_SET_KSTACK;		/* get special stack if necessary */\
 256	andi.	r10,r11,MSR_PR;		/* save stack pointer */	    \
 257	beq	1f;			/* branch around if supervisor */   \
 258	ld	r1,PACAKSAVE(r13);	/* get kernel stack coming from usr */\
 2591:	type##_BTB_FLUSH		\
 260	cmpdi	cr1,r1,0;		/* check if SP makes sense */	    \
 261	bge-	cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
 262	mfspr	r10,SPRN_##type##_SRR0;	/* read SRR0 before touching stack */
 263
 264/* Exception type-specific macros */
 265#define	GEN_SET_KSTACK							    \
 266	subi	r1,r1,INT_FRAME_SIZE;	/* alloc frame on kernel stack */
 267#define SPRN_GEN_SRR0	SPRN_SRR0
 268#define SPRN_GEN_SRR1	SPRN_SRR1
 269
 270#define	GDBELL_SET_KSTACK	GEN_SET_KSTACK
 271#define SPRN_GDBELL_SRR0	SPRN_GSRR0
 272#define SPRN_GDBELL_SRR1	SPRN_GSRR1
 273
 274#define CRIT_SET_KSTACK						            \
 275	ld	r1,PACA_CRIT_STACK(r13);				    \
 276	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 277#define SPRN_CRIT_SRR0	SPRN_CSRR0
 278#define SPRN_CRIT_SRR1	SPRN_CSRR1
 279
 280#define DBG_SET_KSTACK						            \
 281	ld	r1,PACA_DBG_STACK(r13);					    \
 282	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 283#define SPRN_DBG_SRR0	SPRN_DSRR0
 284#define SPRN_DBG_SRR1	SPRN_DSRR1
 285
 286#define MC_SET_KSTACK						            \
 287	ld	r1,PACA_MC_STACK(r13);					    \
 288	subi	r1,r1,SPECIAL_EXC_FRAME_SIZE
 289#define SPRN_MC_SRR0	SPRN_MCSRR0
 290#define SPRN_MC_SRR1	SPRN_MCSRR1
 291
 
 292#define GEN_BTB_FLUSH			\
 293	START_BTB_FLUSH_SECTION		\
 294		beq 1f;			\
 295		BTB_FLUSH(r10)			\
 296		1:		\
 297	END_BTB_FLUSH_SECTION
 298
 299#define CRIT_BTB_FLUSH			\
 300	START_BTB_FLUSH_SECTION		\
 301		BTB_FLUSH(r10)		\
 302	END_BTB_FLUSH_SECTION
 303
 304#define DBG_BTB_FLUSH CRIT_BTB_FLUSH
 305#define MC_BTB_FLUSH CRIT_BTB_FLUSH
 306#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
 
 
 
 
 
 
 
 307
 308#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)			    \
 309	EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
 310
 311#define CRIT_EXCEPTION_PROLOG(n, intnum, addition)			    \
 312	EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
 313
 314#define DBG_EXCEPTION_PROLOG(n, intnum, addition)			    \
 315	EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
 316
 317#define MC_EXCEPTION_PROLOG(n, intnum, addition)			    \
 318	EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
 319
 320#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)			    \
 321	EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 322
 323/* Variants of the "addition" argument for the prolog
 324 */
 325#define PROLOG_ADDITION_NONE_GEN(n)
 326#define PROLOG_ADDITION_NONE_GDBELL(n)
 327#define PROLOG_ADDITION_NONE_CRIT(n)
 328#define PROLOG_ADDITION_NONE_DBG(n)
 329#define PROLOG_ADDITION_NONE_MC(n)
 330
 331#define PROLOG_ADDITION_MASKABLE_GEN(n)					    \
 332	lbz	r10,PACAIRQSOFTMASK(r13);	/* are irqs soft-masked? */ \
 333	andi.	r10,r10,IRQS_DISABLED;	/* yes -> go out of line */ \
 334	bne	masked_interrupt_book3e_##n
 335
 336/*
 337 * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is
 338 * called, because that does SAVE_NVGPRS which must see the original register
 339 * values, otherwise the scratch values might be restored when exiting the
 340 * interrupt.
 341 */
 342#define PROLOG_ADDITION_2REGS_GEN(n)					    \
 343	std	r14,PACA_EXGEN+EX_R14(r13);				    \
 344	std	r15,PACA_EXGEN+EX_R15(r13)
 345
 346#define PROLOG_ADDITION_1REG_GEN(n)					    \
 347	std	r14,PACA_EXGEN+EX_R14(r13);
 348
 349#define PROLOG_ADDITION_2REGS_CRIT(n)					    \
 350	std	r14,PACA_EXCRIT+EX_R14(r13);				    \
 351	std	r15,PACA_EXCRIT+EX_R15(r13)
 352
 353#define PROLOG_ADDITION_2REGS_DBG(n)					    \
 354	std	r14,PACA_EXDBG+EX_R14(r13);				    \
 355	std	r15,PACA_EXDBG+EX_R15(r13)
 356
 357#define PROLOG_ADDITION_2REGS_MC(n)					    \
 358	std	r14,PACA_EXMC+EX_R14(r13);				    \
 359	std	r15,PACA_EXMC+EX_R15(r13)
 360
 
 361/* Core exception code for all exceptions except TLB misses. */
 362#define EXCEPTION_COMMON_LVL(n, scratch, excf)				    \
 363exc_##n##_common:							    \
 364	SAVE_GPR(0, r1);		/* save r0 in stackframe */	    \
 365	SAVE_GPRS(2, 9, r1);		/* save r2 - r9 in stackframe */    \
 
 
 
 366	std	r10,_NIP(r1);		/* save SRR0 to stackframe */	    \
 367	std	r11,_MSR(r1);		/* save SRR1 to stackframe */	    \
 368	beq	2f;			/* if from kernel mode */	    \
 
 3692:	ld	r3,excf+EX_R10(r13);	/* get back r10 */		    \
 370	ld	r4,excf+EX_R11(r13);	/* get back r11 */		    \
 371	mfspr	r5,scratch;		/* get back r13 */		    \
 372	SAVE_GPR(12, r1);		/* save r12 in stackframe */	    \
 373	LOAD_PACA_TOC();		/* get kernel TOC into r2 */	    \
 374	mflr	r6;			/* save LR in stackframe */	    \
 375	mfctr	r7;			/* save CTR in stackframe */	    \
 376	mfspr	r8,SPRN_XER;		/* save XER in stackframe */	    \
 377	ld	r9,excf+EX_R1(r13);	/* load orig r1 back from PACA */   \
 378	lwz	r10,excf+EX_CR(r13);	/* load orig CR back from PACA	*/  \
 379	lbz	r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */	    \
 380	LOAD_REG_IMMEDIATE(r12, STACK_FRAME_REGS_MARKER);		    \
 381	ZEROIZE_GPR(0);							    \
 382	std	r3,GPR10(r1);		/* save r10 to stackframe */	    \
 383	std	r4,GPR11(r1);		/* save r11 to stackframe */	    \
 384	std	r5,GPR13(r1);		/* save it to stackframe */	    \
 385	std	r6,_LINK(r1);						    \
 386	std	r7,_CTR(r1);						    \
 387	std	r8,_XER(r1);						    \
 388	li	r3,(n);			/* regs.trap vector */		    \
 389	std	r9,0(r1);		/* store stack frame back link */   \
 390	std	r10,_CCR(r1);		/* store orig CR in stackframe */   \
 391	std	r9,GPR1(r1);		/* store stack frame back link */   \
 392	std	r11,SOFTE(r1);		/* and save it to stackframe */     \
 393	std	r12,STACK_INT_FRAME_MARKER(r1); /* mark the frame */	    \
 394	std	r3,_TRAP(r1);		/* set trap number		*/  \
 395	std	r0,RESULT(r1);		/* clear regs->result */	    \
 396	SAVE_NVGPRS(r1);						    \
 397	SANITIZE_NVGPRS();		/* minimise speculation influence */
 398
 399#define EXCEPTION_COMMON(n) \
 400	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
 401#define EXCEPTION_COMMON_CRIT(n) \
 402	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
 403#define EXCEPTION_COMMON_MC(n) \
 404	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
 405#define EXCEPTION_COMMON_DBG(n) \
 406	EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
 407
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 408/* XXX FIXME: Restore r14/r15 when necessary */
 409#define BAD_STACK_TRAMPOLINE(n)						    \
 410exc_##n##_bad_stack:							    \
 411	li	r1,(n);			/* get exception number */	    \
 412	sth	r1,PACA_TRAP_SAVE(r13);	/* store trap */		    \
 413	b	bad_stack_book3e;	/* bad stack error */
 414
 415/* WARNING: If you change the layout of this stub, make sure you check
 416	*   the debug exception handler which handles single stepping
 417	*   into exceptions from userspace, and the MM code in
 418	*   arch/powerpc/mm/tlb_nohash.c which patches the branch here
 419	*   and would need to be updated if that branch is moved
 420	*/
 421#define	EXCEPTION_STUB(loc, label)					\
 422	. = interrupt_base_book3e + loc;				\
 423	nop;	/* To make debug interrupts happy */			\
 424	b	exc_##label##_book3e;
 425
 426#define ACK_NONE(r)
 427#define ACK_DEC(r)							\
 428	lis	r,TSR_DIS@h;						\
 429	mtspr	SPRN_TSR,r
 430#define ACK_FIT(r)							\
 431	lis	r,TSR_FIS@h;						\
 432	mtspr	SPRN_TSR,r
 433
 434/* Used by asynchronous interrupt that may happen in the idle loop.
 435 *
 436 * This check if the thread was in the idle loop, and if yes, returns
 437 * to the caller rather than the PC. This is to avoid a race if
 438 * interrupts happen before the wait instruction.
 439 */
 440#define CHECK_NAPPING()							\
 441	ld	r11, PACA_THREAD_INFO(r13);				\
 442	ld	r10,TI_LOCAL_FLAGS(r11);				\
 443	andi.	r9,r10,_TLF_NAPPING;					\
 444	beq+	1f;							\
 445	ld	r8,_LINK(r1);						\
 446	rlwinm	r7,r10,0,~_TLF_NAPPING;					\
 447	std	r8,_NIP(r1);						\
 448	std	r7,TI_LOCAL_FLAGS(r11);					\
 4491:
 450
 451
 452#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)		\
 453	START_EXCEPTION(label);						\
 454	NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
 455	EXCEPTION_COMMON(trapnum)					\
 
 456	ack(r8);							\
 457	CHECK_NAPPING();						\
 458	addi	r3,r1,STACK_INT_FRAME_REGS;				\
 459	bl	hdlr;							\
 460	b	interrupt_return
 
 
 
 
 
 
 461
 462/*
 463 * And here we have the exception vectors !
 464 */
 465
 466	.text
 467	.balign	0x1000
 468	.globl interrupt_base_book3e
 469interrupt_base_book3e:					/* fake trap */
 470	EXCEPTION_STUB(0x000, machine_check)
 471	EXCEPTION_STUB(0x020, critical_input)		/* 0x0100 */
 472	EXCEPTION_STUB(0x040, debug_crit)		/* 0x0d00 */
 473	EXCEPTION_STUB(0x060, data_storage)		/* 0x0300 */
 474	EXCEPTION_STUB(0x080, instruction_storage)	/* 0x0400 */
 475	EXCEPTION_STUB(0x0a0, external_input)		/* 0x0500 */
 476	EXCEPTION_STUB(0x0c0, alignment)		/* 0x0600 */
 477	EXCEPTION_STUB(0x0e0, program)			/* 0x0700 */
 478	EXCEPTION_STUB(0x100, fp_unavailable)		/* 0x0800 */
 479	EXCEPTION_STUB(0x120, system_call)		/* 0x0c00 */
 480	EXCEPTION_STUB(0x140, ap_unavailable)		/* 0x0f20 */
 481	EXCEPTION_STUB(0x160, decrementer)		/* 0x0900 */
 482	EXCEPTION_STUB(0x180, fixed_interval)		/* 0x0980 */
 483	EXCEPTION_STUB(0x1a0, watchdog)			/* 0x09f0 */
 484	EXCEPTION_STUB(0x1c0, data_tlb_miss)
 485	EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
 486	EXCEPTION_STUB(0x200, altivec_unavailable)
 487	EXCEPTION_STUB(0x220, altivec_assist)
 488	EXCEPTION_STUB(0x260, perfmon)
 489	EXCEPTION_STUB(0x280, doorbell)
 490	EXCEPTION_STUB(0x2a0, doorbell_crit)
 491	EXCEPTION_STUB(0x2c0, guest_doorbell)
 492	EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
 493	EXCEPTION_STUB(0x300, hypercall)
 494	EXCEPTION_STUB(0x320, ehpriv)
 495	EXCEPTION_STUB(0x340, lrat_error)
 496
 497	.globl __end_interrupts
 498__end_interrupts:
 499
 500/* Critical Input Interrupt */
 501	START_EXCEPTION(critical_input);
 502	CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
 503			      PROLOG_ADDITION_NONE)
 504	EXCEPTION_COMMON_CRIT(0x100)
 
 505	bl	special_reg_save
 506	CHECK_NAPPING();
 507	addi	r3,r1,STACK_INT_FRAME_REGS
 508	bl	unknown_nmi_exception
 509	b	ret_from_crit_except
 510
 511/* Machine Check Interrupt */
 512	START_EXCEPTION(machine_check);
 513	MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
 514			    PROLOG_ADDITION_NONE)
 515	EXCEPTION_COMMON_MC(0x000)
 
 516	bl	special_reg_save
 517	CHECK_NAPPING();
 518	addi	r3,r1,STACK_INT_FRAME_REGS
 519	bl	machine_check_exception
 520	b	ret_from_mc_except
 521
 522/* Data Storage Interrupt */
 523	START_EXCEPTION(data_storage)
 524	NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
 525				PROLOG_ADDITION_2REGS)
 526	mfspr	r14,SPRN_DEAR
 527	mfspr	r15,SPRN_ESR
 528	std	r14,_DEAR(r1)
 529	std	r15,_ESR(r1)
 530	ld	r14,PACA_EXGEN+EX_R14(r13)
 531	ld	r15,PACA_EXGEN+EX_R15(r13)
 532	EXCEPTION_COMMON(0x300)
 
 533	b	storage_fault_common
 534
 535/* Instruction Storage Interrupt */
 536	START_EXCEPTION(instruction_storage);
 537	NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
 538				PROLOG_ADDITION_2REGS)
 539	li	r15,0
 540	mr	r14,r10
 541	std	r14,_DEAR(r1)
 542	std	r15,_ESR(r1)
 543	ld	r14,PACA_EXGEN+EX_R14(r13)
 544	ld	r15,PACA_EXGEN+EX_R15(r13)
 545	EXCEPTION_COMMON(0x400)
 
 546	b	storage_fault_common
 547
 548/* External Input Interrupt */
 549	MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
 550			   external_input, do_IRQ, ACK_NONE)
 551
 552/* Alignment */
 553	START_EXCEPTION(alignment);
 554	NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
 555				PROLOG_ADDITION_2REGS)
 556	mfspr	r14,SPRN_DEAR
 557	mfspr	r15,SPRN_ESR
 558	std	r14,_DEAR(r1)
 559	std	r15,_ESR(r1)
 560	ld	r14,PACA_EXGEN+EX_R14(r13)
 561	ld	r15,PACA_EXGEN+EX_R15(r13)
 562	EXCEPTION_COMMON(0x600)
 563	b	alignment_more	/* no room, go out of line */
 564
 565/* Program Interrupt */
 566	START_EXCEPTION(program);
 567	NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
 568				PROLOG_ADDITION_1REG)
 569	mfspr	r14,SPRN_ESR
 570	std	r14,_ESR(r1)
 571	ld	r14,PACA_EXGEN+EX_R14(r13)
 572	EXCEPTION_COMMON(0x700)
 573	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 
 
 574	bl	program_check_exception
 575	REST_NVGPRS(r1)
 576	b	interrupt_return
 577
 578/* Floating Point Unavailable Interrupt */
 579	START_EXCEPTION(fp_unavailable);
 580	NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
 581				PROLOG_ADDITION_NONE)
 582	/* we can probably do a shorter exception entry for that one... */
 583	EXCEPTION_COMMON(0x800)
 584	ld	r12,_MSR(r1)
 585	andi.	r0,r12,MSR_PR;
 586	beq-	1f
 587	bl	load_up_fpu
 588	b	fast_interrupt_return
 5891:	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 590	bl	kernel_fp_unavailable_exception
 591	b	interrupt_return
 592
 593/* Altivec Unavailable Interrupt */
 594	START_EXCEPTION(altivec_unavailable);
 595	NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
 596				PROLOG_ADDITION_NONE)
 597	/* we can probably do a shorter exception entry for that one... */
 598	EXCEPTION_COMMON(0x200)
 599#ifdef CONFIG_ALTIVEC
 600BEGIN_FTR_SECTION
 601	ld	r12,_MSR(r1)
 602	andi.	r0,r12,MSR_PR;
 603	beq-	1f
 604	bl	load_up_altivec
 605	b	fast_interrupt_return
 6061:
 607END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 608#endif
 609	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 610	bl	altivec_unavailable_exception
 611	b	interrupt_return
 612
 613/* AltiVec Assist */
 614	START_EXCEPTION(altivec_assist);
 615	NORMAL_EXCEPTION_PROLOG(0x220,
 616				BOOKE_INTERRUPT_ALTIVEC_ASSIST,
 617				PROLOG_ADDITION_NONE)
 618	EXCEPTION_COMMON(0x220)
 619	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 620#ifdef CONFIG_ALTIVEC
 621BEGIN_FTR_SECTION
 622	bl	altivec_assist_exception
 623END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 624	REST_NVGPRS(r1)
 625#else
 626	bl	unknown_exception
 627#endif
 628	b	interrupt_return
 629
 630
 631/* Decrementer Interrupt */
 632	MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
 633			   decrementer, timer_interrupt, ACK_DEC)
 634
 635/* Fixed Interval Timer Interrupt */
 636	MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
 637			   fixed_interval, unknown_exception, ACK_FIT)
 638
 639/* Watchdog Timer Interrupt */
 640	START_EXCEPTION(watchdog);
 641	CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
 642			      PROLOG_ADDITION_NONE)
 643	EXCEPTION_COMMON_CRIT(0x9f0)
 
 644	bl	special_reg_save
 645	CHECK_NAPPING();
 646	addi	r3,r1,STACK_INT_FRAME_REGS
 647#ifdef CONFIG_BOOKE_WDT
 648	bl	WatchdogException
 649#else
 650	bl	unknown_nmi_exception
 651#endif
 652	b	ret_from_crit_except
 653
 654/* System Call Interrupt */
 655	START_EXCEPTION(system_call)
 656	mr	r9,r13			/* keep a copy of userland r13 */
 657	mfspr	r11,SPRN_SRR0		/* get return address */
 658	mfspr	r12,SPRN_SRR1		/* get previous MSR */
 659	mfspr	r13,SPRN_SPRG_PACA	/* get our PACA */
 660	b	system_call_common
 661
 662/* Auxiliary Processor Unavailable Interrupt */
 663	START_EXCEPTION(ap_unavailable);
 664	NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
 665				PROLOG_ADDITION_NONE)
 666	EXCEPTION_COMMON(0xf20)
 667	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 668	bl	unknown_exception
 669	b	interrupt_return
 670
 671/* Debug exception as a critical interrupt*/
 672	START_EXCEPTION(debug_crit);
 673	CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 674			      PROLOG_ADDITION_2REGS)
 675
 676	/*
 677	 * If there is a single step or branch-taken exception in an
 678	 * exception entry sequence, it was probably meant to apply to
 679	 * the code where the exception occurred (since exception entry
 680	 * doesn't turn off DE automatically).  We simulate the effect
 681	 * of turning off DE on entry to an exception handler by turning
 682	 * off DE in the CSRR1 value and clearing the debug status.
 683	 */
 684
 685	mfspr	r14,SPRN_DBSR		/* check single-step/branch taken */
 686	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h
 687	beq+	1f
 688
 689#ifdef CONFIG_RELOCATABLE
 690	__LOAD_PACA_TOC(r15)
 691	LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e)
 692	LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts)
 693	cmpld	cr0,r10,r14
 694	cmpld	cr1,r10,r15
 695#else
 696	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 697	cmpld	cr0, r10, r14
 698	LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
 699	cmpld	cr1, r10, r14
 700#endif
 701	blt+	cr0,1f
 702	bge+	cr1,1f
 703
 704	/* here it looks like we got an inappropriate debug exception. */
 705	lis	r14,(DBSR_IC|DBSR_BT)@h		/* clear the event */
 706	rlwinm	r11,r11,0,~MSR_DE	/* clear DE in the CSRR1 value */
 707	mtspr	SPRN_DBSR,r14
 708	mtspr	SPRN_CSRR1,r11
 709	lwz	r10,PACA_EXCRIT+EX_CR(r13)	/* restore registers */
 710	ld	r1,PACA_EXCRIT+EX_R1(r13)
 711	ld	r14,PACA_EXCRIT+EX_R14(r13)
 712	ld	r15,PACA_EXCRIT+EX_R15(r13)
 713	mtcr	r10
 714	ld	r10,PACA_EXCRIT+EX_R10(r13)	/* restore registers */
 715	ld	r11,PACA_EXCRIT+EX_R11(r13)
 716	mfspr	r13,SPRN_SPRG_CRIT_SCRATCH
 717	rfci
 718
 719	/* Normal debug exception */
 720	/* XXX We only handle coming from userspace for now since we can't
 721	 *     quite save properly an interrupted kernel state yet
 722	 */
 7231:	andi.	r14,r11,MSR_PR;		/* check for userspace again */
 724	beq	kernel_dbg_exc;		/* if from kernel mode */
 725
 726	/* Now we mash up things to make it look like we are coming on a
 727	 * normal exception
 728	 */
 729	mfspr	r14,SPRN_DBSR
 
 730	std	r14,_DSISR(r1)
 
 
 731	ld	r14,PACA_EXCRIT+EX_R14(r13)
 732	ld	r15,PACA_EXCRIT+EX_R15(r13)
 733	EXCEPTION_COMMON_CRIT(0xd00)
 734	addi	r3,r1,STACK_INT_FRAME_REGS
 735	bl	DebugException
 736	REST_NVGPRS(r1)
 737	b	interrupt_return
 738
 739kernel_dbg_exc:
 740	b	.	/* NYI */
 741
 742/* Debug exception as a debug interrupt*/
 743	START_EXCEPTION(debug_debug);
 744	DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 745						 PROLOG_ADDITION_2REGS)
 746
 747	/*
 748	 * If there is a single step or branch-taken exception in an
 749	 * exception entry sequence, it was probably meant to apply to
 750	 * the code where the exception occurred (since exception entry
 751	 * doesn't turn off DE automatically).  We simulate the effect
 752	 * of turning off DE on entry to an exception handler by turning
 753	 * off DE in the DSRR1 value and clearing the debug status.
 754	 */
 755
 756	mfspr	r14,SPRN_DBSR		/* check single-step/branch taken */
 757	andis.	r15,r14,(DBSR_IC|DBSR_BT)@h
 758	beq+	1f
 759
 760#ifdef CONFIG_RELOCATABLE
 761	__LOAD_PACA_TOC(r15)
 762	LOAD_REG_ADDR_ALTTOC(r14, r15, interrupt_base_book3e)
 763	LOAD_REG_ADDR_ALTTOC(r15, r15, __end_interrupts)
 764	cmpld	cr0,r10,r14
 765	cmpld	cr1,r10,r15
 766#else
 767	LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 768	cmpld	cr0, r10, r14
 769	LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
 770	cmpld	cr1, r10, r14
 771#endif
 772	blt+	cr0,1f
 773	bge+	cr1,1f
 774
 775	/* here it looks like we got an inappropriate debug exception. */
 776	lis	r14,(DBSR_IC|DBSR_BT)@h		/* clear the event */
 777	rlwinm	r11,r11,0,~MSR_DE	/* clear DE in the DSRR1 value */
 778	mtspr	SPRN_DBSR,r14
 779	mtspr	SPRN_DSRR1,r11
 780	lwz	r10,PACA_EXDBG+EX_CR(r13)	/* restore registers */
 781	ld	r1,PACA_EXDBG+EX_R1(r13)
 782	ld	r14,PACA_EXDBG+EX_R14(r13)
 783	ld	r15,PACA_EXDBG+EX_R15(r13)
 784	mtcr	r10
 785	ld	r10,PACA_EXDBG+EX_R10(r13)	/* restore registers */
 786	ld	r11,PACA_EXDBG+EX_R11(r13)
 787	mfspr	r13,SPRN_SPRG_DBG_SCRATCH
 788	rfdi
 789
 790	/* Normal debug exception */
 791	/* XXX We only handle coming from userspace for now since we can't
 792	 *     quite save properly an interrupted kernel state yet
 793	 */
 7941:	andi.	r14,r11,MSR_PR;		/* check for userspace again */
 795	beq	kernel_dbg_exc;		/* if from kernel mode */
 796
 797	/* Now we mash up things to make it look like we are coming on a
 798	 * normal exception
 799	 */
 800	mfspr	r14,SPRN_DBSR
 
 
 801	std	r14,_DSISR(r1)
 
 
 802	ld	r14,PACA_EXDBG+EX_R14(r13)
 803	ld	r15,PACA_EXDBG+EX_R15(r13)
 804	EXCEPTION_COMMON_DBG(0xd08)
 805	addi	r3,r1,STACK_INT_FRAME_REGS
 806	bl	DebugException
 807	REST_NVGPRS(r1)
 808	b	interrupt_return
 809
 810	START_EXCEPTION(perfmon);
 811	NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
 812				PROLOG_ADDITION_NONE)
 813	EXCEPTION_COMMON(0x260)
 
 814	CHECK_NAPPING()
 815	addi	r3,r1,STACK_INT_FRAME_REGS
 816	/*
 817	 * XXX: Returning from performance_monitor_exception taken as a
 818	 * soft-NMI (Linux irqs disabled) may be risky to use interrupt_return
 819	 * and could cause bugs in return or elsewhere. That case should just
 820	 * restore registers and return. There is a workaround for one known
 821	 * problem in interrupt_exit_kernel_prepare().
 822	 */
 823	bl	performance_monitor_exception
 824	b	interrupt_return
 825
 826/* Doorbell interrupt */
 827	MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
 828			   doorbell, doorbell_exception, ACK_NONE)
 829
 830/* Doorbell critical Interrupt */
 831	START_EXCEPTION(doorbell_crit);
 832	CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
 833			      PROLOG_ADDITION_NONE)
 834	EXCEPTION_COMMON_CRIT(0x2a0)
 
 835	bl	special_reg_save
 836	CHECK_NAPPING();
 837	addi	r3,r1,STACK_INT_FRAME_REGS
 838	bl	unknown_nmi_exception
 839	b	ret_from_crit_except
 840
 841/*
 842 *	Guest doorbell interrupt
 843 *	This general exception use GSRRx save/restore registers
 844 */
 845	START_EXCEPTION(guest_doorbell);
 846	GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
 847			        PROLOG_ADDITION_NONE)
 848	EXCEPTION_COMMON(0x2c0)
 849	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 850	bl	unknown_exception
 851	b	interrupt_return
 852
 853/* Guest Doorbell critical Interrupt */
 854	START_EXCEPTION(guest_doorbell_crit);
 855	CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
 856			      PROLOG_ADDITION_NONE)
 857	EXCEPTION_COMMON_CRIT(0x2e0)
 
 858	bl	special_reg_save
 859	CHECK_NAPPING();
 860	addi	r3,r1,STACK_INT_FRAME_REGS
 861	bl	unknown_nmi_exception
 862	b	ret_from_crit_except
 863
 864/* Hypervisor call */
 865	START_EXCEPTION(hypercall);
 866	NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
 867			        PROLOG_ADDITION_NONE)
 868	EXCEPTION_COMMON(0x310)
 869	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 870	bl	unknown_exception
 871	b	interrupt_return
 872
 873/* Embedded Hypervisor priviledged  */
 874	START_EXCEPTION(ehpriv);
 875	NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
 876			        PROLOG_ADDITION_NONE)
 877	EXCEPTION_COMMON(0x320)
 878	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 879	bl	unknown_exception
 880	b	interrupt_return
 881
 882/* LRAT Error interrupt */
 883	START_EXCEPTION(lrat_error);
 884	NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
 885			        PROLOG_ADDITION_NONE)
 886	EXCEPTION_COMMON(0x340)
 887	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 888	bl	unknown_exception
 889	b	interrupt_return
 890
 891.macro SEARCH_RESTART_TABLE
 892#ifdef CONFIG_RELOCATABLE
 893	__LOAD_PACA_TOC(r11)
 894	LOAD_REG_ADDR_ALTTOC(r14, r11, __start___restart_table)
 895	LOAD_REG_ADDR_ALTTOC(r15, r11, __stop___restart_table)
 896#else
 897	LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table)
 898	LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table)
 899#endif
 900300:
 901	cmpd	r14,r15
 902	beq	302f
 903	ld	r11,0(r14)
 904	cmpld	r10,r11
 905	blt	301f
 906	ld	r11,8(r14)
 907	cmpld	r10,r11
 908	bge	301f
 909	ld	r11,16(r14)
 910	b	303f
 911301:
 912	addi	r14,r14,24
 913	b	300b
 914302:
 915	li	r11,0
 916303:
 917.endm
 918
 919/*
 920 * An interrupt came in while soft-disabled; We mark paca->irq_happened
 921 * accordingly and if the interrupt is level sensitive, we hard disable
 922 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
 923 * keep these in synch.
 924 */
 925
 926.macro masked_interrupt_book3e paca_irq full_mask
 927	std	r14,PACA_EXGEN+EX_R14(r13)
 928	std	r15,PACA_EXGEN+EX_R15(r13)
 929
 930	lbz	r10,PACAIRQHAPPENED(r13)
 931	.if \full_mask == 1
 932	ori	r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
 933	.else
 934	ori	r10,r10,\paca_irq
 935	.endif
 936	stb	r10,PACAIRQHAPPENED(r13)
 937
 938	.if \full_mask == 1
 939	xori	r11,r11,MSR_EE		/* clear MSR_EE */
 
 940	mtspr	SPRN_SRR1,r11
 941	.endif
 942
 943	mfspr	r10,SPRN_SRR0
 944	SEARCH_RESTART_TABLE
 945	cmpdi	r11,0
 946	beq	1f
 947	mtspr	SPRN_SRR0,r11		/* return to restart address */
 9481:
 949
 950	lwz	r11,PACA_EXGEN+EX_CR(r13)
 951	mtcr	r11
 952	ld	r10,PACA_EXGEN+EX_R10(r13)
 953	ld	r11,PACA_EXGEN+EX_R11(r13)
 954	ld	r14,PACA_EXGEN+EX_R14(r13)
 955	ld	r15,PACA_EXGEN+EX_R15(r13)
 956	mfspr	r13,SPRN_SPRG_GEN_SCRATCH
 957	rfi
 958	b	.
 959.endm
 960
 961masked_interrupt_book3e_0x500:
 
 962	masked_interrupt_book3e PACA_IRQ_EE 1
 963
 964masked_interrupt_book3e_0x900:
 965	ACK_DEC(r10);
 966	masked_interrupt_book3e PACA_IRQ_DEC 0
 967
 968masked_interrupt_book3e_0x980:
 969	ACK_FIT(r10);
 970	masked_interrupt_book3e PACA_IRQ_DEC 0
 971
 972masked_interrupt_book3e_0x280:
 973masked_interrupt_book3e_0x2c0:
 974	masked_interrupt_book3e PACA_IRQ_DBELL 0
 975
 976/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 977 * This is called from 0x300 and 0x400 handlers after the prologs with
 978 * r14 and r15 containing the fault address and error code, with the
 979 * original values stashed away in the PACA
 980 */
 981storage_fault_common:
 982	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 
 
 
 
 983	bl	do_page_fault
 984	b	interrupt_return
 
 
 
 
 
 
 
 
 985
 986/*
 987 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
 988 * continues here.
 989 */
 990alignment_more:
 991	addi	r3,r1,STACK_INT_FRAME_REGS
 
 
 
 
 
 
 992	bl	alignment_exception
 993	REST_NVGPRS(r1)
 994	b	interrupt_return
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 995
 996/*
 997 * Trampolines used when spotting a bad kernel stack pointer in
 998 * the exception entry code.
 999 *
1000 * TODO: move some bits like SRR0 read to trampoline, pass PACA
1001 * index around, etc... to handle crit & mcheck
1002 */
1003BAD_STACK_TRAMPOLINE(0x000)
1004BAD_STACK_TRAMPOLINE(0x100)
1005BAD_STACK_TRAMPOLINE(0x200)
1006BAD_STACK_TRAMPOLINE(0x220)
1007BAD_STACK_TRAMPOLINE(0x260)
1008BAD_STACK_TRAMPOLINE(0x280)
1009BAD_STACK_TRAMPOLINE(0x2a0)
1010BAD_STACK_TRAMPOLINE(0x2c0)
1011BAD_STACK_TRAMPOLINE(0x2e0)
1012BAD_STACK_TRAMPOLINE(0x300)
1013BAD_STACK_TRAMPOLINE(0x310)
1014BAD_STACK_TRAMPOLINE(0x320)
1015BAD_STACK_TRAMPOLINE(0x340)
1016BAD_STACK_TRAMPOLINE(0x400)
1017BAD_STACK_TRAMPOLINE(0x500)
1018BAD_STACK_TRAMPOLINE(0x600)
1019BAD_STACK_TRAMPOLINE(0x700)
1020BAD_STACK_TRAMPOLINE(0x800)
1021BAD_STACK_TRAMPOLINE(0x900)
1022BAD_STACK_TRAMPOLINE(0x980)
1023BAD_STACK_TRAMPOLINE(0x9f0)
1024BAD_STACK_TRAMPOLINE(0xa00)
1025BAD_STACK_TRAMPOLINE(0xb00)
1026BAD_STACK_TRAMPOLINE(0xc00)
1027BAD_STACK_TRAMPOLINE(0xd00)
1028BAD_STACK_TRAMPOLINE(0xd08)
1029BAD_STACK_TRAMPOLINE(0xe00)
1030BAD_STACK_TRAMPOLINE(0xf00)
1031BAD_STACK_TRAMPOLINE(0xf20)
1032
1033	.globl	bad_stack_book3e
1034bad_stack_book3e:
1035	/* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1036	mfspr	r10,SPRN_SRR0;		  /* read SRR0 before touching stack */
1037	ld	r1,PACAEMERGSP(r13)
1038	subi	r1,r1,64+INT_FRAME_SIZE
1039	std	r10,_NIP(r1)
1040	std	r11,_MSR(r1)
1041	ld	r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1042	lwz	r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1043	std	r10,GPR1(r1)
1044	std	r11,_CCR(r1)
1045	mfspr	r10,SPRN_DEAR
1046	mfspr	r11,SPRN_ESR
1047	std	r10,_DEAR(r1)
1048	std	r11,_ESR(r1)
1049	SAVE_GPR(0, r1);		/* save r0 in stackframe */	    \
1050	SAVE_GPRS(2, 9, r1);		/* save r2 - r9 in stackframe */    \
 
 
 
1051	ld	r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */		    \
1052	ld	r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */		    \
1053	mfspr	r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1054	std	r3,GPR10(r1);		/* save r10 to stackframe */	    \
1055	std	r4,GPR11(r1);		/* save r11 to stackframe */	    \
1056	SAVE_GPR(12, r1);		/* save r12 in stackframe */	    \
1057	std	r5,GPR13(r1);		/* save it to stackframe */	    \
1058	mflr	r10
1059	mfctr	r11
1060	mfxer	r12
1061	std	r10,_LINK(r1)
1062	std	r11,_CTR(r1)
1063	std	r12,_XER(r1)
1064	SAVE_NVGPRS(r1)
 
1065	lhz	r12,PACA_TRAP_SAVE(r13)
1066	std	r12,_TRAP(r1)
1067	addi	r11,r1,INT_FRAME_SIZE
1068	std	r11,0(r1)
1069	ZEROIZE_GPR(12)
1070	std	r12,0(r11)
1071	LOAD_PACA_TOC()
10721:	addi	r3,r1,STACK_INT_FRAME_REGS
1073	bl	kernel_bad_stack
1074	b	1b
1075
1076/*
1077 * Setup the initial TLB for a core. This current implementation
1078 * assume that whatever we are running off will not conflict with
1079 * the new mapping at PAGE_OFFSET.
1080 */
1081_GLOBAL(initial_tlb_book3e)
1082
1083	/* Look for the first TLB with IPROT set */
1084	mfspr	r4,SPRN_TLB0CFG
1085	andi.	r3,r4,TLBnCFG_IPROT
1086	lis	r3,MAS0_TLBSEL(0)@h
1087	bne	found_iprot
1088
1089	mfspr	r4,SPRN_TLB1CFG
1090	andi.	r3,r4,TLBnCFG_IPROT
1091	lis	r3,MAS0_TLBSEL(1)@h
1092	bne	found_iprot
1093
1094	mfspr	r4,SPRN_TLB2CFG
1095	andi.	r3,r4,TLBnCFG_IPROT
1096	lis	r3,MAS0_TLBSEL(2)@h
1097	bne	found_iprot
1098
1099	lis	r3,MAS0_TLBSEL(3)@h
1100	mfspr	r4,SPRN_TLB3CFG
1101	/* fall through */
1102
1103found_iprot:
1104	andi.	r5,r4,TLBnCFG_HES
1105	bne	have_hes
1106
1107	mflr	r8				/* save LR */
1108/* 1. Find the index of the entry we're executing in
1109 *
1110 * r3 = MAS0_TLBSEL (for the iprot array)
1111 * r4 = SPRN_TLBnCFG
1112 */
1113	bcl	20,31,$+4			/* Find our address */
1114invstr:	mflr	r6				/* Make it accessible */
1115	mfmsr	r7
1116	rlwinm	r5,r7,27,31,31			/* extract MSR[IS] */
1117	mfspr	r7,SPRN_PID
1118	slwi	r7,r7,16
1119	or	r7,r7,r5
1120	mtspr	SPRN_MAS6,r7
1121	tlbsx	0,r6				/* search MSR[IS], SPID=PID */
1122
1123	mfspr	r3,SPRN_MAS0
1124	rlwinm	r5,r3,16,20,31			/* Extract MAS0(Entry) */
1125
1126	mfspr	r7,SPRN_MAS1			/* Insure IPROT set */
1127	oris	r7,r7,MAS1_IPROT@h
1128	mtspr	SPRN_MAS1,r7
1129	tlbwe
1130
1131/* 2. Invalidate all entries except the entry we're executing in
1132 *
1133 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1134 * r4 = SPRN_TLBnCFG
1135 * r5 = ESEL of entry we are running in
1136 */
1137	andi.	r4,r4,TLBnCFG_N_ENTRY		/* Extract # entries */
1138	li	r6,0				/* Set Entry counter to 0 */
11391:	mr	r7,r3				/* Set MAS0(TLBSEL) */
1140	rlwimi	r7,r6,16,4,15			/* Setup MAS0 = TLBSEL | ESEL(r6) */
1141	mtspr	SPRN_MAS0,r7
1142	tlbre
1143	mfspr	r7,SPRN_MAS1
1144	rlwinm	r7,r7,0,2,31			/* Clear MAS1 Valid and IPROT */
1145	cmpw	r5,r6
1146	beq	skpinv				/* Dont update the current execution TLB */
1147	mtspr	SPRN_MAS1,r7
1148	tlbwe
1149	isync
1150skpinv:	addi	r6,r6,1				/* Increment */
1151	cmpw	r6,r4				/* Are we done? */
1152	bne	1b				/* If not, repeat */
1153
1154	/* Invalidate all TLBs */
1155	PPC_TLBILX_ALL(0,R0)
1156	sync
1157	isync
1158
1159/* 3. Setup a temp mapping and jump to it
1160 *
1161 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1162 * r5 = ESEL of entry we are running in
1163 */
1164	andi.	r7,r5,0x1	/* Find an entry not used and is non-zero */
1165	addi	r7,r7,0x1
1166	mr	r4,r3		/* Set MAS0(TLBSEL) = 1 */
1167	mtspr	SPRN_MAS0,r4
1168	tlbre
1169
1170	rlwimi	r4,r7,16,4,15	/* Setup MAS0 = TLBSEL | ESEL(r7) */
1171	mtspr	SPRN_MAS0,r4
1172
1173	mfspr	r7,SPRN_MAS1
1174	xori	r6,r7,MAS1_TS		/* Setup TMP mapping in the other Address space */
1175	mtspr	SPRN_MAS1,r6
1176
1177	tlbwe
1178
1179	mfmsr	r6
1180	xori	r6,r6,MSR_IS
1181	mtspr	SPRN_SRR1,r6
1182	bcl	20,31,$+4	/* Find our address */
11831:	mflr	r6
1184	addi	r6,r6,(2f - 1b)
1185	mtspr	SPRN_SRR0,r6
1186	rfi
11872:
1188
1189/* 4. Clear out PIDs & Search info
1190 *
1191 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1192 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1193 * r5 = MAS3
1194 */
1195	li	r6,0
1196	mtspr   SPRN_MAS6,r6
1197	mtspr	SPRN_PID,r6
1198
1199/* 5. Invalidate mapping we started in
1200 *
1201 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1202 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1203 * r5 = MAS3
1204 */
1205	mtspr	SPRN_MAS0,r3
1206	tlbre
1207	mfspr	r6,SPRN_MAS1
1208	rlwinm	r6,r6,0,2,31	/* clear IPROT and VALID */
1209	mtspr	SPRN_MAS1,r6
1210	tlbwe
1211	sync
1212	isync
1213
 
 
 
 
 
 
 
 
 
 
1214/* 6. Setup KERNELBASE mapping in TLB[0]
1215 *
1216 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1217 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1218 * r5 = MAS3
1219 */
1220	rlwinm	r3,r3,0,16,3	/* clear ESEL */
1221	mtspr	SPRN_MAS0,r3
1222	lis	r6,(MAS1_VALID|MAS1_IPROT)@h
1223	ori	r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1224	mtspr	SPRN_MAS1,r6
1225
1226	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
1227	mtspr	SPRN_MAS2,r6
1228
1229	rlwinm	r5,r5,0,0,25
1230	ori	r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1231	mtspr	SPRN_MAS3,r5
1232	li	r5,-1
1233	rlwinm	r5,r5,0,0,25
1234
1235	tlbwe
1236
1237/* 7. Jump to KERNELBASE mapping
1238 *
1239 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1240 */
1241	/* Now we branch the new virtual address mapped by this entry */
1242	bcl	20,31,$+4	/* Find our address */
12431:	mflr	r6
1244	addi	r6,r6,(2f - 1b)
1245	tovirt(r6,r6)
1246	lis	r7,MSR_KERNEL@h
1247	ori	r7,r7,MSR_KERNEL@l
1248	mtspr	SPRN_SRR0,r6
1249	mtspr	SPRN_SRR1,r7
1250	rfi				/* start execution out of TLB1[0] entry */
12512:
1252
1253/* 8. Clear out the temp mapping
1254 *
1255 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1256 */
1257	mtspr	SPRN_MAS0,r4
1258	tlbre
1259	mfspr	r5,SPRN_MAS1
1260	rlwinm	r5,r5,0,2,31	/* clear IPROT and VALID */
1261	mtspr	SPRN_MAS1,r5
1262	tlbwe
1263	sync
1264	isync
1265
1266	/* We translate LR and return */
1267	tovirt(r8,r8)
1268	mtlr	r8
1269	blr
1270
1271have_hes:
1272	/* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1273	 * kernel linear mapping. We also set MAS8 once for all here though
1274	 * that will have to be made dependent on whether we are running under
1275	 * a hypervisor I suppose.
1276	 */
1277
1278	/* BEWARE, MAGIC
1279	 * This code is called as an ordinary function on the boot CPU. But to
1280	 * avoid duplication, this code is also used in SCOM bringup of
1281	 * secondary CPUs. We read the code between the initial_tlb_code_start
1282	 * and initial_tlb_code_end labels one instruction at a time and RAM it
1283	 * into the new core via SCOM. That doesn't process branches, so there
1284	 * must be none between those two labels. It also means if this code
1285	 * ever takes any parameters, the SCOM code must also be updated to
1286	 * provide them.
1287	 */
1288	.globl a2_tlbinit_code_start
1289a2_tlbinit_code_start:
1290
1291	ori	r11,r3,MAS0_WQ_ALLWAYS
1292	oris	r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1293	mtspr	SPRN_MAS0,r11
1294	lis	r3,(MAS1_VALID | MAS1_IPROT)@h
1295	ori	r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1296	mtspr	SPRN_MAS1,r3
1297	LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1298	mtspr	SPRN_MAS2,r3
1299	li	r3,MAS3_SR | MAS3_SW | MAS3_SX
1300	mtspr	SPRN_MAS7_MAS3,r3
1301	li	r3,0
1302	mtspr	SPRN_MAS8,r3
1303
1304	/* Write the TLB entry */
1305	tlbwe
1306
1307	.globl a2_tlbinit_after_linear_map
1308a2_tlbinit_after_linear_map:
1309
1310	/* Now we branch the new virtual address mapped by this entry */
1311#ifdef CONFIG_RELOCATABLE
1312	__LOAD_PACA_TOC(r5)
1313	LOAD_REG_ADDR_ALTTOC(r3, r5, 1f)
1314#else
1315	LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1316#endif
1317	mtctr	r3
1318	bctr
1319
13201:	/* We are now running at PAGE_OFFSET, clean the TLB of everything
1321	 * else (including IPROTed things left by firmware)
1322	 * r4 = TLBnCFG
1323	 * r3 = current address (more or less)
1324	 */
1325
1326	li	r5,0
1327	mtspr	SPRN_MAS6,r5
1328	tlbsx	0,r3
1329
1330	rlwinm	r9,r4,0,TLBnCFG_N_ENTRY
1331	rlwinm	r10,r4,8,0xff
1332	addi	r10,r10,-1	/* Get inner loop mask */
1333
1334	li	r3,1
1335
1336	mfspr	r5,SPRN_MAS1
1337	rlwinm	r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1338
1339	mfspr	r6,SPRN_MAS2
1340	rldicr	r6,r6,0,51		/* Extract EPN */
1341
1342	mfspr	r7,SPRN_MAS0
1343	rlwinm	r7,r7,0,0xffff0fff	/* Clear HES and WQ */
1344
1345	rlwinm	r8,r7,16,0xfff		/* Extract ESEL */
1346
13472:	add	r4,r3,r8
1348	and	r4,r4,r10
1349
1350	rlwimi	r7,r4,16,MAS0_ESEL_MASK
1351
1352	mtspr	SPRN_MAS0,r7
1353	mtspr	SPRN_MAS1,r5
1354	mtspr	SPRN_MAS2,r6
1355	tlbwe
1356
1357	addi	r3,r3,1
1358	and.	r4,r3,r10
1359
1360	bne	3f
1361	addis	r6,r6,(1<<30)@h
13623:
1363	cmpw	r3,r9
1364	blt	2b
1365
1366	.globl  a2_tlbinit_after_iprot_flush
1367a2_tlbinit_after_iprot_flush:
1368
1369	PPC_TLBILX(0,0,R0)
1370	sync
1371	isync
1372
1373	.globl a2_tlbinit_code_end
1374a2_tlbinit_code_end:
1375
1376	/* We translate LR and return */
1377	mflr	r3
1378	tovirt(r3,r3)
1379	mtlr	r3
1380	blr
1381
1382/*
1383 * Main entry (boot CPU, thread 0)
1384 *
1385 * We enter here from head_64.S, possibly after the prom_init trampoline
1386 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1387 * mode. Anything else is as it was left by the bootloader
1388 *
1389 * Initial requirements of this port:
1390 *
1391 * - Kernel loaded at 0 physical
1392 * - A good lump of memory mapped 0:0 by UTLB entry 0
1393 * - MSR:IS & MSR:DS set to 0
1394 *
1395 * Note that some of the above requirements will be relaxed in the future
1396 * as the kernel becomes smarter at dealing with different initial conditions
1397 * but for now you have to be careful
1398 */
1399_GLOBAL(start_initialization_book3e)
1400	mflr	r28
1401
1402	/* First, we need to setup some initial TLBs to map the kernel
1403	 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1404	 * and always use AS 0, so we just set it up to match our link
1405	 * address and never use 0 based addresses.
1406	 */
1407	bl	initial_tlb_book3e
1408
1409	/* Init global core bits */
1410	bl	init_core_book3e
1411
1412	/* Init per-thread bits */
1413	bl	init_thread_book3e
1414
1415	/* Return to common init code */
1416	tovirt(r28,r28)
1417	mtlr	r28
1418	blr
1419
1420
1421/*
1422 * Secondary core/processor entry
1423 *
1424 * This is entered for thread 0 of a secondary core, all other threads
1425 * are expected to be stopped. It's similar to start_initialization_book3e
1426 * except that it's generally entered from the holding loop in head_64.S
1427 * after CPUs have been gathered by Open Firmware.
1428 *
1429 * We assume we are in 32 bits mode running with whatever TLB entry was
1430 * set for us by the firmware or POR engine.
1431 */
1432_GLOBAL(book3e_secondary_core_init_tlb_set)
1433	li	r4,1
1434	b	generic_secondary_smp_init
1435
1436_GLOBAL(book3e_secondary_core_init)
1437	mflr	r28
1438
1439	/* Do we need to setup initial TLB entry ? */
1440	cmplwi	r4,0
1441	bne	2f
1442
1443	/* Setup TLB for this core */
1444	bl	initial_tlb_book3e
1445
1446	/* We can return from the above running at a different
1447	 * address, so recalculate r2 (TOC)
1448	 */
1449	bl	relative_toc
1450
1451	/* Init global core bits */
14522:	bl	init_core_book3e
1453
1454	/* Init per-thread bits */
14553:	bl	init_thread_book3e
1456
1457	/* Return to common init code at proper virtual address.
1458	 *
1459	 * Due to various previous assumptions, we know we entered this
1460	 * function at either the final PAGE_OFFSET mapping or using a
1461	 * 1:1 mapping at 0, so we don't bother doing a complicated check
1462	 * here, we just ensure the return address has the right top bits.
1463	 *
1464	 * Note that if we ever want to be smarter about where we can be
1465	 * started from, we have to be careful that by the time we reach
1466	 * the code below we may already be running at a different location
1467	 * than the one we were called from since initial_tlb_book3e can
1468	 * have moved us already.
1469	 */
1470	cmpdi	cr0,r28,0
1471	blt	1f
1472	lis	r3,PAGE_OFFSET@highest
1473	sldi	r3,r3,32
1474	or	r28,r28,r3
14751:	mtlr	r28
1476	blr
1477
1478_GLOBAL(book3e_secondary_thread_init)
1479	mflr	r28
1480	b	3b
1481
1482	.globl init_core_book3e
1483init_core_book3e:
1484	/* Establish the interrupt vector base */
1485	tovirt(r2,r2)
1486	LOAD_REG_ADDR(r3, interrupt_base_book3e)
1487	mtspr	SPRN_IVPR,r3
1488	sync
1489	blr
1490
1491init_thread_book3e:
1492	lis	r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1493	mtspr	SPRN_EPCR,r3
1494
1495	/* Make sure interrupts are off */
1496	wrteei	0
1497
1498	/* disable all timers and clear out status */
1499	li	r3,0
1500	mtspr	SPRN_TCR,r3
1501	mfspr	r3,SPRN_TSR
1502	mtspr	SPRN_TSR,r3
1503
1504	blr
1505
1506_GLOBAL(__setup_base_ivors)
1507	SET_IVOR(0, 0x020) /* Critical Input */
1508	SET_IVOR(1, 0x000) /* Machine Check */
1509	SET_IVOR(2, 0x060) /* Data Storage */ 
1510	SET_IVOR(3, 0x080) /* Instruction Storage */
1511	SET_IVOR(4, 0x0a0) /* External Input */ 
1512	SET_IVOR(5, 0x0c0) /* Alignment */ 
1513	SET_IVOR(6, 0x0e0) /* Program */ 
1514	SET_IVOR(7, 0x100) /* FP Unavailable */ 
1515	SET_IVOR(8, 0x120) /* System Call */ 
1516	SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 
1517	SET_IVOR(10, 0x160) /* Decrementer */ 
1518	SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 
1519	SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 
1520	SET_IVOR(13, 0x1c0) /* Data TLB Error */ 
1521	SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1522	SET_IVOR(15, 0x040) /* Debug */
1523
1524	sync
1525
1526	blr
1527
1528_GLOBAL(setup_altivec_ivors)
1529	SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1530	SET_IVOR(33, 0x220) /* AltiVec Assist */
1531	blr
1532
1533_GLOBAL(setup_perfmon_ivor)
1534	SET_IVOR(35, 0x260) /* Performance Monitor */
1535	blr
1536
1537_GLOBAL(setup_doorbell_ivors)
1538	SET_IVOR(36, 0x280) /* Processor Doorbell */
1539	SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1540	blr
1541
1542_GLOBAL(setup_ehv_ivors)
1543	SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1544	SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1545	SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1546	SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1547	blr
1548
1549_GLOBAL(setup_lrat_ivor)
1550	SET_IVOR(42, 0x340) /* LRAT Error */
1551	blr