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1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40 compatible = "fsl,T4240";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 crypto = &crypto;
54
55 pci0 = &pci0;
56 pci1 = &pci1;
57 pci2 = &pci2;
58 pci3 = &pci3;
59 usb0 = &usb0;
60 usb1 = &usb1;
61 dma0 = &dma0;
62 dma1 = &dma1;
63 dma2 = &dma2;
64 sdhc = &sdhc;
65
66 fman0 = &fman0;
67 fman1 = &fman1;
68 ethernet0 = &enet0;
69 ethernet1 = &enet1;
70 ethernet2 = &enet2;
71 ethernet3 = &enet3;
72 ethernet4 = &enet4;
73 ethernet5 = &enet5;
74 ethernet6 = &enet6;
75 ethernet7 = &enet7;
76 ethernet8 = &enet8;
77 ethernet9 = &enet9;
78 ethernet10 = &enet10;
79 ethernet11 = &enet11;
80 ethernet12 = &enet12;
81 ethernet13 = &enet13;
82 ethernet14 = &enet14;
83 ethernet15 = &enet15;
84 };
85
86 cpus {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 cpu0: PowerPC,e6500@0 {
91 device_type = "cpu";
92 reg = <0 1>;
93 clocks = <&clockgen 1 0>;
94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>;
96 };
97 cpu1: PowerPC,e6500@2 {
98 device_type = "cpu";
99 reg = <2 3>;
100 clocks = <&clockgen 1 0>;
101 next-level-cache = <&L2_1>;
102 fsl,portid-mapping = <0x80000000>;
103 };
104 cpu2: PowerPC,e6500@4 {
105 device_type = "cpu";
106 reg = <4 5>;
107 clocks = <&clockgen 1 0>;
108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x80000000>;
110 };
111 cpu3: PowerPC,e6500@6 {
112 device_type = "cpu";
113 reg = <6 7>;
114 clocks = <&clockgen 1 0>;
115 next-level-cache = <&L2_1>;
116 fsl,portid-mapping = <0x80000000>;
117 };
118 cpu4: PowerPC,e6500@8 {
119 device_type = "cpu";
120 reg = <8 9>;
121 clocks = <&clockgen 1 1>;
122 next-level-cache = <&L2_2>;
123 fsl,portid-mapping = <0x40000000>;
124 };
125 cpu5: PowerPC,e6500@10 {
126 device_type = "cpu";
127 reg = <10 11>;
128 clocks = <&clockgen 1 1>;
129 next-level-cache = <&L2_2>;
130 fsl,portid-mapping = <0x40000000>;
131 };
132 cpu6: PowerPC,e6500@12 {
133 device_type = "cpu";
134 reg = <12 13>;
135 clocks = <&clockgen 1 1>;
136 next-level-cache = <&L2_2>;
137 fsl,portid-mapping = <0x40000000>;
138 };
139 cpu7: PowerPC,e6500@14 {
140 device_type = "cpu";
141 reg = <14 15>;
142 clocks = <&clockgen 1 1>;
143 next-level-cache = <&L2_2>;
144 fsl,portid-mapping = <0x40000000>;
145 };
146 cpu8: PowerPC,e6500@16 {
147 device_type = "cpu";
148 reg = <16 17>;
149 clocks = <&clockgen 1 2>;
150 next-level-cache = <&L2_3>;
151 fsl,portid-mapping = <0x20000000>;
152 };
153 cpu9: PowerPC,e6500@18 {
154 device_type = "cpu";
155 reg = <18 19>;
156 clocks = <&clockgen 1 2>;
157 next-level-cache = <&L2_3>;
158 fsl,portid-mapping = <0x20000000>;
159 };
160 cpu10: PowerPC,e6500@20 {
161 device_type = "cpu";
162 reg = <20 21>;
163 clocks = <&clockgen 1 2>;
164 next-level-cache = <&L2_3>;
165 fsl,portid-mapping = <0x20000000>;
166 };
167 cpu11: PowerPC,e6500@22 {
168 device_type = "cpu";
169 reg = <22 23>;
170 clocks = <&clockgen 1 2>;
171 next-level-cache = <&L2_3>;
172 fsl,portid-mapping = <0x20000000>;
173 };
174 };
175};
1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40 compatible = "fsl,T4240";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 crypto = &crypto;
54
55 pci0 = &pci0;
56 pci1 = &pci1;
57 pci2 = &pci2;
58 pci3 = &pci3;
59 usb0 = &usb0;
60 usb1 = &usb1;
61 dma0 = &dma0;
62 dma1 = &dma1;
63 dma2 = &dma2;
64 sdhc = &sdhc;
65
66 fman0 = &fman0;
67 fman1 = &fman1;
68 ethernet0 = &enet0;
69 ethernet1 = &enet1;
70 ethernet2 = &enet2;
71 ethernet3 = &enet3;
72 ethernet4 = &enet4;
73 ethernet5 = &enet5;
74 ethernet6 = &enet6;
75 ethernet7 = &enet7;
76 ethernet8 = &enet8;
77 ethernet9 = &enet9;
78 ethernet10 = &enet10;
79 ethernet11 = &enet11;
80 ethernet12 = &enet12;
81 ethernet13 = &enet13;
82 ethernet14 = &enet14;
83 ethernet15 = &enet15;
84 };
85
86 cpus {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 cpu0: PowerPC,e6500@0 {
91 device_type = "cpu";
92 reg = <0 1>;
93 clocks = <&clockgen 1 0>;
94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>;
96 };
97 cpu1: PowerPC,e6500@2 {
98 device_type = "cpu";
99 reg = <2 3>;
100 clocks = <&clockgen 1 0>;
101 next-level-cache = <&L2_1>;
102 fsl,portid-mapping = <0x80000000>;
103 };
104 cpu2: PowerPC,e6500@4 {
105 device_type = "cpu";
106 reg = <4 5>;
107 clocks = <&clockgen 1 0>;
108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x80000000>;
110 };
111 cpu3: PowerPC,e6500@6 {
112 device_type = "cpu";
113 reg = <6 7>;
114 clocks = <&clockgen 1 0>;
115 next-level-cache = <&L2_1>;
116 fsl,portid-mapping = <0x80000000>;
117 };
118 cpu4: PowerPC,e6500@8 {
119 device_type = "cpu";
120 reg = <8 9>;
121 clocks = <&clockgen 1 1>;
122 next-level-cache = <&L2_2>;
123 fsl,portid-mapping = <0x40000000>;
124 };
125 cpu5: PowerPC,e6500@10 {
126 device_type = "cpu";
127 reg = <10 11>;
128 clocks = <&clockgen 1 1>;
129 next-level-cache = <&L2_2>;
130 fsl,portid-mapping = <0x40000000>;
131 };
132 cpu6: PowerPC,e6500@12 {
133 device_type = "cpu";
134 reg = <12 13>;
135 clocks = <&clockgen 1 1>;
136 next-level-cache = <&L2_2>;
137 fsl,portid-mapping = <0x40000000>;
138 };
139 cpu7: PowerPC,e6500@14 {
140 device_type = "cpu";
141 reg = <14 15>;
142 clocks = <&clockgen 1 1>;
143 next-level-cache = <&L2_2>;
144 fsl,portid-mapping = <0x40000000>;
145 };
146 cpu8: PowerPC,e6500@16 {
147 device_type = "cpu";
148 reg = <16 17>;
149 clocks = <&clockgen 1 2>;
150 next-level-cache = <&L2_3>;
151 fsl,portid-mapping = <0x20000000>;
152 };
153 cpu9: PowerPC,e6500@18 {
154 device_type = "cpu";
155 reg = <18 19>;
156 clocks = <&clockgen 1 2>;
157 next-level-cache = <&L2_3>;
158 fsl,portid-mapping = <0x20000000>;
159 };
160 cpu10: PowerPC,e6500@20 {
161 device_type = "cpu";
162 reg = <20 21>;
163 clocks = <&clockgen 1 2>;
164 next-level-cache = <&L2_3>;
165 fsl,portid-mapping = <0x20000000>;
166 };
167 cpu11: PowerPC,e6500@22 {
168 device_type = "cpu";
169 reg = <22 23>;
170 clocks = <&clockgen 1 2>;
171 next-level-cache = <&L2_3>;
172 fsl,portid-mapping = <0x20000000>;
173 };
174 };
175};