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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PPA8548 Device Tree Source (36-bit address map)
4 * Copyright 2013 Prodrive B.V.
5 *
6 * Based on:
7 * MPC8548 CDS Device Tree Source (36-bit address map)
8 * Copyright 2012 Freescale Semiconductor Inc.
9 */
10
11/include/ "mpc8548si-pre.dtsi"
12
13/ {
14 model = "ppa8548";
15 compatible = "ppa8548";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
19
20 memory {
21 device_type = "memory";
22 reg = <0 0 0x0 0x40000000>;
23 };
24
25 lbc: localbus@fe0005000 {
26 reg = <0xf 0xe0005000 0 0x1000>;
27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
28 };
29
30 soc: soc8548@fe0000000 {
31 ranges = <0 0xf 0xe0000000 0x100000>;
32 };
33
34 pci0: pci@fe0008000 {
35 /* ppa8548 board doesn't support PCI */
36 status = "disabled";
37 };
38
39 pci1: pci@fe0009000 {
40 /* ppa8548 board doesn't support PCI */
41 status = "disabled";
42 };
43
44 pci2: pcie@fe000a000 {
45 /* ppa8548 board doesn't support PCI */
46 status = "disabled";
47 };
48
49 rio: rapidio@fe00c0000 {
50 reg = <0xf 0xe00c0000 0x0 0x11000>;
51 port1 {
52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
53 };
54 };
55};
56
57&lbc {
58 nor@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "cfi-flash";
62 reg = <0x0 0x0 0x00800000>;
63 bank-width = <2>;
64 device-width = <2>;
65
66 partition@0 {
67 reg = <0x0 0x7A0000>;
68 label = "user";
69 };
70
71 partition@7A0000 {
72 reg = <0x7A0000 0x20000>;
73 label = "env";
74 read-only;
75 };
76
77 partition@7C0000 {
78 reg = <0x7C0000 0x40000>;
79 label = "u-boot";
80 read-only;
81 };
82 };
83};
84
85&soc {
86 i2c@3000 {
87 rtc@6f {
88 compatible = "intersil,isl1208";
89 reg = <0x6f>;
90 };
91 };
92
93 i2c@3100 {
94 };
95
96 /*
97 * Only ethernet controller @25000 and @26000 are used.
98 * Use alias enet2 and enet3 for the remainig controllers,
99 * to stay compatible with mpc8548si-pre.dtsi.
100 */
101 enet2: ethernet@24000 {
102 status = "disabled";
103 };
104
105 mdio@24520 {
106 phy0: ethernet-phy@0 {
107 interrupts = <7 1 0 0>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupts = <8 1 0 0>;
112 reg = <0x1>;
113 };
114 tbi0: tbi-phy@11 {
115 reg = <0x11>;
116 device_type = "tbi-phy";
117 };
118 };
119
120 enet0: ethernet@25000 {
121 tbi-handle = <&tbi1>;
122 phy-handle = <&phy0>;
123 };
124
125 mdio@25520 {
126 tbi1: tbi-phy@11 {
127 reg = <0x11>;
128 device_type = "tbi-phy";
129 };
130 };
131
132 enet1: ethernet@26000 {
133 tbi-handle = <&tbi2>;
134 phy-handle = <&phy1>;
135 };
136
137 mdio@26520 {
138 tbi2: tbi-phy@11 {
139 reg = <0x11>;
140 device_type = "tbi-phy";
141 };
142 };
143
144 enet3: ethernet@27000 {
145 status = "disabled";
146 };
147
148 mdio@27520 {
149 tbi3: tbi-phy@11 {
150 reg = <0x11>;
151 device_type = "tbi-phy";
152 };
153 };
154
155 crypto@30000 {
156 status = "disabled";
157 };
158};
159
160/include/ "mpc8548si-post.dtsi"
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PPA8548 Device Tree Source (36-bit address map)
4 * Copyright 2013 Prodrive B.V.
5 *
6 * Based on:
7 * MPC8548 CDS Device Tree Source (36-bit address map)
8 * Copyright 2012 Freescale Semiconductor Inc.
9 */
10
11/include/ "mpc8548si-pre.dtsi"
12
13/ {
14 model = "ppa8548";
15 compatible = "ppa8548";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
19
20 memory {
21 device_type = "memory";
22 reg = <0 0 0x0 0x40000000>;
23 };
24
25 lbc: localbus@fe0005000 {
26 reg = <0xf 0xe0005000 0 0x1000>;
27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
28 };
29
30 soc: soc8548@fe0000000 {
31 ranges = <0 0xf 0xe0000000 0x100000>;
32 };
33
34 pci0: pci@fe0008000 {
35 /* ppa8548 board doesn't support PCI */
36 status = "disabled";
37 };
38
39 pci1: pci@fe0009000 {
40 /* ppa8548 board doesn't support PCI */
41 status = "disabled";
42 };
43
44 pci2: pcie@fe000a000 {
45 /* ppa8548 board doesn't support PCI */
46 status = "disabled";
47 };
48
49 rio: rapidio@fe00c0000 {
50 reg = <0xf 0xe00c0000 0x0 0x11000>;
51 port1 {
52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
53 };
54 };
55};
56
57&lbc {
58 nor@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "cfi-flash";
62 reg = <0x0 0x0 0x00800000>;
63 bank-width = <2>;
64 device-width = <2>;
65
66 partition@0 {
67 reg = <0x0 0x7A0000>;
68 label = "user";
69 };
70
71 partition@7A0000 {
72 reg = <0x7A0000 0x20000>;
73 label = "env";
74 read-only;
75 };
76
77 partition@7C0000 {
78 reg = <0x7C0000 0x40000>;
79 label = "u-boot";
80 read-only;
81 };
82 };
83};
84
85&soc {
86 i2c@3000 {
87 rtc@6f {
88 compatible = "intersil,isl1208";
89 reg = <0x6f>;
90 };
91 };
92
93 i2c@3100 {
94 };
95
96 /*
97 * Only ethernet controller @25000 and @26000 are used.
98 * Use alias enet2 and enet3 for the remainig controllers,
99 * to stay compatible with mpc8548si-pre.dtsi.
100 */
101 enet2: ethernet@24000 {
102 status = "disabled";
103 };
104
105 mdio@24520 {
106 phy0: ethernet-phy@0 {
107 interrupts = <7 1 0 0>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupts = <8 1 0 0>;
112 reg = <0x1>;
113 };
114 tbi0: tbi-phy@11 {
115 reg = <0x11>;
116 device_type = "tbi-phy";
117 };
118 };
119
120 enet0: ethernet@25000 {
121 tbi-handle = <&tbi1>;
122 phy-handle = <&phy0>;
123 };
124
125 mdio@25520 {
126 tbi1: tbi-phy@11 {
127 reg = <0x11>;
128 device_type = "tbi-phy";
129 };
130 };
131
132 enet1: ethernet@26000 {
133 tbi-handle = <&tbi2>;
134 phy-handle = <&phy1>;
135 };
136
137 mdio@26520 {
138 tbi2: tbi-phy@11 {
139 reg = <0x11>;
140 device_type = "tbi-phy";
141 };
142 };
143
144 enet3: ethernet@27000 {
145 status = "disabled";
146 };
147
148 mdio@27520 {
149 tbi3: tbi-phy@11 {
150 reg = <0x11>;
151 device_type = "tbi-phy";
152 };
153 };
154
155 crypto@30000 {
156 status = "disabled";
157 };
158};
159
160/include/ "mpc8548si-post.dtsi"