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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Analogue & Micro ASP8347 Device Tree Source
4 *
5 * Copyright 2008 Codehermit
6 */
7
8/dts-v1/;
9
10/ {
11 model = "Analogue & Micro ASP8347E";
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,8347@0 {
28 device_type = "cpu";
29 reg = <0x0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x8000000>; // 128MB at 0
43 };
44
45 localbus@ff005000 {
46 #address-cells = <2>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc8347e-localbus",
49 "fsl,pq2pro-localbus",
50 "simple-bus";
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>;
54
55 ranges = <
56 0 0 0xf0000000 0x02000000
57 >;
58
59 flash@0,0 {
60 compatible = "cfi-flash";
61 reg = <0 0 0x02000000>;
62 bank-width = <2>;
63 device-width = <2>;
64 };
65 };
66
67 soc8349@ff000000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 device_type = "soc";
71 ranges = <0x0 0xff000000 0x00100000>;
72 reg = <0xff000000 0x00000200>;
73 bus-frequency = <0>;
74
75 wdt@200 {
76 device_type = "watchdog";
77 compatible = "mpc83xx_wdt";
78 reg = <0x200 0x100>;
79 };
80
81 i2c@3000 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
85 compatible = "fsl-i2c";
86 reg = <0x3000 0x100>;
87 interrupts = <14 0x8>;
88 interrupt-parent = <&ipic>;
89 dfsrr;
90
91 rtc@68 {
92 compatible = "dallas,ds1374";
93 reg = <0x68>;
94 };
95 };
96
97 i2c@3100 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 cell-index = <1>;
101 compatible = "fsl-i2c";
102 reg = <0x3100 0x100>;
103 interrupts = <15 0x8>;
104 interrupt-parent = <&ipic>;
105 dfsrr;
106 };
107
108 spi@7000 {
109 cell-index = <0>;
110 compatible = "fsl,spi";
111 reg = <0x7000 0x1000>;
112 interrupts = <16 0x8>;
113 interrupt-parent = <&ipic>;
114 mode = "cpu";
115 };
116
117 dma@82a8 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
121 reg = <0x82a8 4>;
122 ranges = <0 0x8100 0x1a8>;
123 interrupt-parent = <&ipic>;
124 interrupts = <71 8>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
128 reg = <0 0x80>;
129 cell-index = <0>;
130 interrupt-parent = <&ipic>;
131 interrupts = <71 8>;
132 };
133 dma-channel@80 {
134 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
135 reg = <0x80 0x80>;
136 cell-index = <1>;
137 interrupt-parent = <&ipic>;
138 interrupts = <71 8>;
139 };
140 dma-channel@100 {
141 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
142 reg = <0x100 0x80>;
143 cell-index = <2>;
144 interrupt-parent = <&ipic>;
145 interrupts = <71 8>;
146 };
147 dma-channel@180 {
148 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
149 reg = <0x180 0x28>;
150 cell-index = <3>;
151 interrupt-parent = <&ipic>;
152 interrupts = <71 8>;
153 };
154 };
155
156 /* phy type (ULPI or SERIAL) are only types supported for MPH */
157 /* port = 0 or 1 */
158 usb@22000 {
159 compatible = "fsl-usb2-mph";
160 reg = <0x22000 0x1000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupt-parent = <&ipic>;
164 interrupts = <39 0x8>;
165 phy_type = "ulpi";
166 port0;
167 };
168 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
169 usb@23000 {
170 compatible = "fsl-usb2-dr";
171 reg = <0x23000 0x1000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupt-parent = <&ipic>;
175 interrupts = <38 0x8>;
176 dr_mode = "otg";
177 phy_type = "ulpi";
178 };
179
180 enet0: ethernet@24000 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 cell-index = <0>;
184 device_type = "network";
185 model = "TSEC";
186 compatible = "gianfar";
187 reg = <0x24000 0x1000>;
188 ranges = <0x0 0x24000 0x1000>;
189 local-mac-address = [ 00 08 e5 11 32 33 ];
190 interrupts = <32 0x8 33 0x8 34 0x8>;
191 interrupt-parent = <&ipic>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
194 linux,network-index = <0>;
195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-mdio";
200 reg = <0x520 0x20>;
201
202 phy0: ethernet-phy@0 {
203 interrupt-parent = <&ipic>;
204 interrupts = <17 0x8>;
205 reg = <0x1>;
206 };
207
208 phy1: ethernet-phy@1 {
209 interrupt-parent = <&ipic>;
210 interrupts = <18 0x8>;
211 reg = <0x2>;
212 };
213
214 tbi0: tbi-phy@11 {
215 reg = <0x11>;
216 device_type = "tbi-phy";
217 };
218 };
219 };
220
221 enet1: ethernet@25000 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 cell-index = <1>;
225 device_type = "network";
226 model = "TSEC";
227 compatible = "gianfar";
228 reg = <0x25000 0x1000>;
229 ranges = <0x0 0x25000 0x1000>;
230 local-mac-address = [ 00 08 e5 11 32 34 ];
231 interrupts = <35 0x8 36 0x8 37 0x8>;
232 interrupt-parent = <&ipic>;
233 tbi-handle = <&tbi1>;
234 phy-handle = <&phy1>;
235 linux,network-index = <1>;
236
237 mdio@520 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 compatible = "fsl,gianfar-tbi";
241 reg = <0x520 0x20>;
242
243 tbi1: tbi-phy@11 {
244 reg = <0x11>;
245 device_type = "tbi-phy";
246 };
247 };
248 };
249
250 serial0: serial@4500 {
251 cell-index = <0>;
252 device_type = "serial";
253 compatible = "fsl,ns16550", "ns16550";
254 reg = <0x4500 0x100>;
255 clock-frequency = <400000000>;
256 interrupts = <9 0x8>;
257 interrupt-parent = <&ipic>;
258 };
259
260 serial1: serial@4600 {
261 cell-index = <1>;
262 device_type = "serial";
263 compatible = "fsl,ns16550", "ns16550";
264 reg = <0x4600 0x100>;
265 clock-frequency = <400000000>;
266 interrupts = <10 0x8>;
267 interrupt-parent = <&ipic>;
268 };
269
270 /* May need to remove if on a part without crypto engine */
271 crypto@30000 {
272 device_type = "crypto";
273 model = "SEC2";
274 compatible = "talitos";
275 reg = <0x30000 0x10000>;
276 interrupts = <11 0x8>;
277 interrupt-parent = <&ipic>;
278 num-channels = <4>;
279 channel-fifo-len = <24>;
280 exec-units-mask = <0x0000007e>;
281 /* desc mask is for rev2.0,
282 * we need runtime fixup for >2.0 */
283 descriptor-types-mask = <0x01010ebf>;
284 };
285
286 /* IPIC
287 * interrupts cell = <intr #, sense>
288 * sense values match linux IORESOURCE_IRQ_* defines:
289 * sense == 8: Level, low assertion
290 * sense == 2: Edge, high-to-low change
291 */
292 ipic: pic@700 {
293 interrupt-controller;
294 #address-cells = <0>;
295 #interrupt-cells = <2>;
296 reg = <0x700 0x100>;
297 device_type = "ipic";
298 };
299 };
300
301 chosen {
302 bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
303 stdout-path = &serial0;
304 };
305
306};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Analogue & Micro ASP8347 Device Tree Source
4 *
5 * Copyright 2008 Codehermit
6 */
7
8/dts-v1/;
9
10/ {
11 model = "Analogue & Micro ASP8347E";
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,8347@0 {
28 device_type = "cpu";
29 reg = <0x0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x8000000>; // 128MB at 0
43 };
44
45 localbus@ff005000 {
46 #address-cells = <2>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc8347e-localbus",
49 "fsl,pq2pro-localbus",
50 "simple-bus";
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>;
54
55 ranges = <
56 0 0 0xf0000000 0x02000000
57 >;
58
59 flash@0,0 {
60 compatible = "cfi-flash";
61 reg = <0 0 0x02000000>;
62 bank-width = <2>;
63 device-width = <2>;
64 };
65 };
66
67 soc8349@ff000000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 device_type = "soc";
71 ranges = <0x0 0xff000000 0x00100000>;
72 reg = <0xff000000 0x00000200>;
73 bus-frequency = <0>;
74
75 wdt@200 {
76 device_type = "watchdog";
77 compatible = "mpc83xx_wdt";
78 reg = <0x200 0x100>;
79 };
80
81 i2c@3000 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
85 compatible = "fsl-i2c";
86 reg = <0x3000 0x100>;
87 interrupts = <14 0x8>;
88 interrupt-parent = <&ipic>;
89 dfsrr;
90
91 rtc@68 {
92 compatible = "dallas,ds1374";
93 reg = <0x68>;
94 };
95 };
96
97 i2c@3100 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 cell-index = <1>;
101 compatible = "fsl-i2c";
102 reg = <0x3100 0x100>;
103 interrupts = <15 0x8>;
104 interrupt-parent = <&ipic>;
105 dfsrr;
106 };
107
108 spi@7000 {
109 cell-index = <0>;
110 compatible = "fsl,spi";
111 reg = <0x7000 0x1000>;
112 interrupts = <16 0x8>;
113 interrupt-parent = <&ipic>;
114 mode = "cpu";
115 };
116
117 dma@82a8 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
121 reg = <0x82a8 4>;
122 ranges = <0 0x8100 0x1a8>;
123 interrupt-parent = <&ipic>;
124 interrupts = <71 8>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
128 reg = <0 0x80>;
129 cell-index = <0>;
130 interrupt-parent = <&ipic>;
131 interrupts = <71 8>;
132 };
133 dma-channel@80 {
134 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
135 reg = <0x80 0x80>;
136 cell-index = <1>;
137 interrupt-parent = <&ipic>;
138 interrupts = <71 8>;
139 };
140 dma-channel@100 {
141 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
142 reg = <0x100 0x80>;
143 cell-index = <2>;
144 interrupt-parent = <&ipic>;
145 interrupts = <71 8>;
146 };
147 dma-channel@180 {
148 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
149 reg = <0x180 0x28>;
150 cell-index = <3>;
151 interrupt-parent = <&ipic>;
152 interrupts = <71 8>;
153 };
154 };
155
156 /* phy type (ULPI or SERIAL) are only types supported for MPH */
157 /* port = 0 or 1 */
158 usb@22000 {
159 compatible = "fsl-usb2-mph";
160 reg = <0x22000 0x1000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupt-parent = <&ipic>;
164 interrupts = <39 0x8>;
165 phy_type = "ulpi";
166 port0;
167 };
168 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
169 usb@23000 {
170 compatible = "fsl-usb2-dr";
171 reg = <0x23000 0x1000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupt-parent = <&ipic>;
175 interrupts = <38 0x8>;
176 dr_mode = "otg";
177 phy_type = "ulpi";
178 };
179
180 enet0: ethernet@24000 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 cell-index = <0>;
184 device_type = "network";
185 model = "TSEC";
186 compatible = "gianfar";
187 reg = <0x24000 0x1000>;
188 ranges = <0x0 0x24000 0x1000>;
189 local-mac-address = [ 00 08 e5 11 32 33 ];
190 interrupts = <32 0x8 33 0x8 34 0x8>;
191 interrupt-parent = <&ipic>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
194 linux,network-index = <0>;
195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-mdio";
200 reg = <0x520 0x20>;
201
202 phy0: ethernet-phy@0 {
203 interrupt-parent = <&ipic>;
204 interrupts = <17 0x8>;
205 reg = <0x1>;
206 };
207
208 phy1: ethernet-phy@1 {
209 interrupt-parent = <&ipic>;
210 interrupts = <18 0x8>;
211 reg = <0x2>;
212 };
213
214 tbi0: tbi-phy@11 {
215 reg = <0x11>;
216 device_type = "tbi-phy";
217 };
218 };
219 };
220
221 enet1: ethernet@25000 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 cell-index = <1>;
225 device_type = "network";
226 model = "TSEC";
227 compatible = "gianfar";
228 reg = <0x25000 0x1000>;
229 ranges = <0x0 0x25000 0x1000>;
230 local-mac-address = [ 00 08 e5 11 32 34 ];
231 interrupts = <35 0x8 36 0x8 37 0x8>;
232 interrupt-parent = <&ipic>;
233 tbi-handle = <&tbi1>;
234 phy-handle = <&phy1>;
235 linux,network-index = <1>;
236
237 mdio@520 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 compatible = "fsl,gianfar-tbi";
241 reg = <0x520 0x20>;
242
243 tbi1: tbi-phy@11 {
244 reg = <0x11>;
245 device_type = "tbi-phy";
246 };
247 };
248 };
249
250 serial0: serial@4500 {
251 cell-index = <0>;
252 device_type = "serial";
253 compatible = "fsl,ns16550", "ns16550";
254 reg = <0x4500 0x100>;
255 clock-frequency = <400000000>;
256 interrupts = <9 0x8>;
257 interrupt-parent = <&ipic>;
258 };
259
260 serial1: serial@4600 {
261 cell-index = <1>;
262 device_type = "serial";
263 compatible = "fsl,ns16550", "ns16550";
264 reg = <0x4600 0x100>;
265 clock-frequency = <400000000>;
266 interrupts = <10 0x8>;
267 interrupt-parent = <&ipic>;
268 };
269
270 /* May need to remove if on a part without crypto engine */
271 crypto@30000 {
272 device_type = "crypto";
273 model = "SEC2";
274 compatible = "talitos";
275 reg = <0x30000 0x10000>;
276 interrupts = <11 0x8>;
277 interrupt-parent = <&ipic>;
278 num-channels = <4>;
279 channel-fifo-len = <24>;
280 exec-units-mask = <0x0000007e>;
281 /* desc mask is for rev2.0,
282 * we need runtime fixup for >2.0 */
283 descriptor-types-mask = <0x01010ebf>;
284 };
285
286 /* IPIC
287 * interrupts cell = <intr #, sense>
288 * sense values match linux IORESOURCE_IRQ_* defines:
289 * sense == 8: Level, low assertion
290 * sense == 2: Edge, high-to-low change
291 */
292 ipic: pic@700 {
293 interrupt-controller;
294 #address-cells = <0>;
295 #interrupt-cells = <2>;
296 reg = <0x700 0x100>;
297 device_type = "ipic";
298 };
299 };
300
301 chosen {
302 bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
303 stdout-path = &serial0;
304 };
305
306};