1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (c) 2003-2012 Cavium Networks
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28#ifndef __CVMX_FPA_DEFS_H__
  29#define __CVMX_FPA_DEFS_H__
  30
  31#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
  32#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
  33#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
  34#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
  35#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
  36#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
  37#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
  38#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
  39#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
  40#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
  41#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
  42#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
  43#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
  44#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
  45#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
  46#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
  47#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
  48#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
  49#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
  50#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
  51#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
  52#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
  53#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
  54#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
  55#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
  56#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
  57#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
  58#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
  59#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
  60#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
  61#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
  62#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
  63#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
  64#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
  65#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
  66#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
  67#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
  68#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
  69#define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull))
  70
  71union cvmx_fpa_addr_range_error {
  72	uint64_t u64;
  73	struct cvmx_fpa_addr_range_error_s {
  74#ifdef __BIG_ENDIAN_BITFIELD
  75		uint64_t reserved_38_63:26;
  76		uint64_t pool:5;
  77		uint64_t addr:33;
  78#else
  79		uint64_t addr:33;
  80		uint64_t pool:5;
  81		uint64_t reserved_38_63:26;
  82#endif
  83	} s;
  84};
  85
  86union cvmx_fpa_bist_status {
  87	uint64_t u64;
  88	struct cvmx_fpa_bist_status_s {
  89#ifdef __BIG_ENDIAN_BITFIELD
  90		uint64_t reserved_5_63:59;
  91		uint64_t frd:1;
  92		uint64_t fpf0:1;
  93		uint64_t fpf1:1;
  94		uint64_t ffr:1;
  95		uint64_t fdr:1;
  96#else
  97		uint64_t fdr:1;
  98		uint64_t ffr:1;
  99		uint64_t fpf1:1;
 100		uint64_t fpf0:1;
 101		uint64_t frd:1;
 102		uint64_t reserved_5_63:59;
 103#endif
 104	} s;
 105};
 106
 107union cvmx_fpa_ctl_status {
 108	uint64_t u64;
 109	struct cvmx_fpa_ctl_status_s {
 110#ifdef __BIG_ENDIAN_BITFIELD
 111		uint64_t reserved_21_63:43;
 112		uint64_t free_en:1;
 113		uint64_t ret_off:1;
 114		uint64_t req_off:1;
 115		uint64_t reset:1;
 116		uint64_t use_ldt:1;
 117		uint64_t use_stt:1;
 118		uint64_t enb:1;
 119		uint64_t mem1_err:7;
 120		uint64_t mem0_err:7;
 121#else
 122		uint64_t mem0_err:7;
 123		uint64_t mem1_err:7;
 124		uint64_t enb:1;
 125		uint64_t use_stt:1;
 126		uint64_t use_ldt:1;
 127		uint64_t reset:1;
 128		uint64_t req_off:1;
 129		uint64_t ret_off:1;
 130		uint64_t free_en:1;
 131		uint64_t reserved_21_63:43;
 132#endif
 133	} s;
 134	struct cvmx_fpa_ctl_status_cn30xx {
 135#ifdef __BIG_ENDIAN_BITFIELD
 136		uint64_t reserved_18_63:46;
 137		uint64_t reset:1;
 138		uint64_t use_ldt:1;
 139		uint64_t use_stt:1;
 140		uint64_t enb:1;
 141		uint64_t mem1_err:7;
 142		uint64_t mem0_err:7;
 143#else
 144		uint64_t mem0_err:7;
 145		uint64_t mem1_err:7;
 146		uint64_t enb:1;
 147		uint64_t use_stt:1;
 148		uint64_t use_ldt:1;
 149		uint64_t reset:1;
 150		uint64_t reserved_18_63:46;
 151#endif
 152	} cn30xx;
 153};
 154
 155union cvmx_fpa_fpfx_marks {
 156	uint64_t u64;
 157	struct cvmx_fpa_fpfx_marks_s {
 158#ifdef __BIG_ENDIAN_BITFIELD
 159		uint64_t reserved_22_63:42;
 160		uint64_t fpf_wr:11;
 161		uint64_t fpf_rd:11;
 162#else
 163		uint64_t fpf_rd:11;
 164		uint64_t fpf_wr:11;
 165		uint64_t reserved_22_63:42;
 166#endif
 167	} s;
 168};
 169
 170union cvmx_fpa_fpfx_size {
 171	uint64_t u64;
 172	struct cvmx_fpa_fpfx_size_s {
 173#ifdef __BIG_ENDIAN_BITFIELD
 174		uint64_t reserved_11_63:53;
 175		uint64_t fpf_siz:11;
 176#else
 177		uint64_t fpf_siz:11;
 178		uint64_t reserved_11_63:53;
 179#endif
 180	} s;
 181};
 182
 183union cvmx_fpa_fpf0_marks {
 184	uint64_t u64;
 185	struct cvmx_fpa_fpf0_marks_s {
 186#ifdef __BIG_ENDIAN_BITFIELD
 187		uint64_t reserved_24_63:40;
 188		uint64_t fpf_wr:12;
 189		uint64_t fpf_rd:12;
 190#else
 191		uint64_t fpf_rd:12;
 192		uint64_t fpf_wr:12;
 193		uint64_t reserved_24_63:40;
 194#endif
 195	} s;
 196};
 197
 198union cvmx_fpa_fpf0_size {
 199	uint64_t u64;
 200	struct cvmx_fpa_fpf0_size_s {
 201#ifdef __BIG_ENDIAN_BITFIELD
 202		uint64_t reserved_12_63:52;
 203		uint64_t fpf_siz:12;
 204#else
 205		uint64_t fpf_siz:12;
 206		uint64_t reserved_12_63:52;
 207#endif
 208	} s;
 209};
 210
 211union cvmx_fpa_fpf8_marks {
 212	uint64_t u64;
 213	struct cvmx_fpa_fpf8_marks_s {
 214#ifdef __BIG_ENDIAN_BITFIELD
 215		uint64_t reserved_22_63:42;
 216		uint64_t fpf_wr:11;
 217		uint64_t fpf_rd:11;
 218#else
 219		uint64_t fpf_rd:11;
 220		uint64_t fpf_wr:11;
 221		uint64_t reserved_22_63:42;
 222#endif
 223	} s;
 224};
 225
 226union cvmx_fpa_fpf8_size {
 227	uint64_t u64;
 228	struct cvmx_fpa_fpf8_size_s {
 229#ifdef __BIG_ENDIAN_BITFIELD
 230		uint64_t reserved_12_63:52;
 231		uint64_t fpf_siz:12;
 232#else
 233		uint64_t fpf_siz:12;
 234		uint64_t reserved_12_63:52;
 235#endif
 236	} s;
 237};
 238
 239union cvmx_fpa_int_enb {
 240	uint64_t u64;
 241	struct cvmx_fpa_int_enb_s {
 242#ifdef __BIG_ENDIAN_BITFIELD
 243		uint64_t reserved_50_63:14;
 244		uint64_t paddr_e:1;
 245		uint64_t reserved_44_48:5;
 246		uint64_t free7:1;
 247		uint64_t free6:1;
 248		uint64_t free5:1;
 249		uint64_t free4:1;
 250		uint64_t free3:1;
 251		uint64_t free2:1;
 252		uint64_t free1:1;
 253		uint64_t free0:1;
 254		uint64_t pool7th:1;
 255		uint64_t pool6th:1;
 256		uint64_t pool5th:1;
 257		uint64_t pool4th:1;
 258		uint64_t pool3th:1;
 259		uint64_t pool2th:1;
 260		uint64_t pool1th:1;
 261		uint64_t pool0th:1;
 262		uint64_t q7_perr:1;
 263		uint64_t q7_coff:1;
 264		uint64_t q7_und:1;
 265		uint64_t q6_perr:1;
 266		uint64_t q6_coff:1;
 267		uint64_t q6_und:1;
 268		uint64_t q5_perr:1;
 269		uint64_t q5_coff:1;
 270		uint64_t q5_und:1;
 271		uint64_t q4_perr:1;
 272		uint64_t q4_coff:1;
 273		uint64_t q4_und:1;
 274		uint64_t q3_perr:1;
 275		uint64_t q3_coff:1;
 276		uint64_t q3_und:1;
 277		uint64_t q2_perr:1;
 278		uint64_t q2_coff:1;
 279		uint64_t q2_und:1;
 280		uint64_t q1_perr:1;
 281		uint64_t q1_coff:1;
 282		uint64_t q1_und:1;
 283		uint64_t q0_perr:1;
 284		uint64_t q0_coff:1;
 285		uint64_t q0_und:1;
 286		uint64_t fed1_dbe:1;
 287		uint64_t fed1_sbe:1;
 288		uint64_t fed0_dbe:1;
 289		uint64_t fed0_sbe:1;
 290#else
 291		uint64_t fed0_sbe:1;
 292		uint64_t fed0_dbe:1;
 293		uint64_t fed1_sbe:1;
 294		uint64_t fed1_dbe:1;
 295		uint64_t q0_und:1;
 296		uint64_t q0_coff:1;
 297		uint64_t q0_perr:1;
 298		uint64_t q1_und:1;
 299		uint64_t q1_coff:1;
 300		uint64_t q1_perr:1;
 301		uint64_t q2_und:1;
 302		uint64_t q2_coff:1;
 303		uint64_t q2_perr:1;
 304		uint64_t q3_und:1;
 305		uint64_t q3_coff:1;
 306		uint64_t q3_perr:1;
 307		uint64_t q4_und:1;
 308		uint64_t q4_coff:1;
 309		uint64_t q4_perr:1;
 310		uint64_t q5_und:1;
 311		uint64_t q5_coff:1;
 312		uint64_t q5_perr:1;
 313		uint64_t q6_und:1;
 314		uint64_t q6_coff:1;
 315		uint64_t q6_perr:1;
 316		uint64_t q7_und:1;
 317		uint64_t q7_coff:1;
 318		uint64_t q7_perr:1;
 319		uint64_t pool0th:1;
 320		uint64_t pool1th:1;
 321		uint64_t pool2th:1;
 322		uint64_t pool3th:1;
 323		uint64_t pool4th:1;
 324		uint64_t pool5th:1;
 325		uint64_t pool6th:1;
 326		uint64_t pool7th:1;
 327		uint64_t free0:1;
 328		uint64_t free1:1;
 329		uint64_t free2:1;
 330		uint64_t free3:1;
 331		uint64_t free4:1;
 332		uint64_t free5:1;
 333		uint64_t free6:1;
 334		uint64_t free7:1;
 335		uint64_t reserved_44_48:5;
 336		uint64_t paddr_e:1;
 337		uint64_t reserved_50_63:14;
 338#endif
 339	} s;
 340	struct cvmx_fpa_int_enb_cn30xx {
 341#ifdef __BIG_ENDIAN_BITFIELD
 342		uint64_t reserved_28_63:36;
 343		uint64_t q7_perr:1;
 344		uint64_t q7_coff:1;
 345		uint64_t q7_und:1;
 346		uint64_t q6_perr:1;
 347		uint64_t q6_coff:1;
 348		uint64_t q6_und:1;
 349		uint64_t q5_perr:1;
 350		uint64_t q5_coff:1;
 351		uint64_t q5_und:1;
 352		uint64_t q4_perr:1;
 353		uint64_t q4_coff:1;
 354		uint64_t q4_und:1;
 355		uint64_t q3_perr:1;
 356		uint64_t q3_coff:1;
 357		uint64_t q3_und:1;
 358		uint64_t q2_perr:1;
 359		uint64_t q2_coff:1;
 360		uint64_t q2_und:1;
 361		uint64_t q1_perr:1;
 362		uint64_t q1_coff:1;
 363		uint64_t q1_und:1;
 364		uint64_t q0_perr:1;
 365		uint64_t q0_coff:1;
 366		uint64_t q0_und:1;
 367		uint64_t fed1_dbe:1;
 368		uint64_t fed1_sbe:1;
 369		uint64_t fed0_dbe:1;
 370		uint64_t fed0_sbe:1;
 371#else
 372		uint64_t fed0_sbe:1;
 373		uint64_t fed0_dbe:1;
 374		uint64_t fed1_sbe:1;
 375		uint64_t fed1_dbe:1;
 376		uint64_t q0_und:1;
 377		uint64_t q0_coff:1;
 378		uint64_t q0_perr:1;
 379		uint64_t q1_und:1;
 380		uint64_t q1_coff:1;
 381		uint64_t q1_perr:1;
 382		uint64_t q2_und:1;
 383		uint64_t q2_coff:1;
 384		uint64_t q2_perr:1;
 385		uint64_t q3_und:1;
 386		uint64_t q3_coff:1;
 387		uint64_t q3_perr:1;
 388		uint64_t q4_und:1;
 389		uint64_t q4_coff:1;
 390		uint64_t q4_perr:1;
 391		uint64_t q5_und:1;
 392		uint64_t q5_coff:1;
 393		uint64_t q5_perr:1;
 394		uint64_t q6_und:1;
 395		uint64_t q6_coff:1;
 396		uint64_t q6_perr:1;
 397		uint64_t q7_und:1;
 398		uint64_t q7_coff:1;
 399		uint64_t q7_perr:1;
 400		uint64_t reserved_28_63:36;
 401#endif
 402	} cn30xx;
 403	struct cvmx_fpa_int_enb_cn61xx {
 404#ifdef __BIG_ENDIAN_BITFIELD
 405		uint64_t reserved_50_63:14;
 406		uint64_t paddr_e:1;
 407		uint64_t res_44:5;
 408		uint64_t free7:1;
 409		uint64_t free6:1;
 410		uint64_t free5:1;
 411		uint64_t free4:1;
 412		uint64_t free3:1;
 413		uint64_t free2:1;
 414		uint64_t free1:1;
 415		uint64_t free0:1;
 416		uint64_t pool7th:1;
 417		uint64_t pool6th:1;
 418		uint64_t pool5th:1;
 419		uint64_t pool4th:1;
 420		uint64_t pool3th:1;
 421		uint64_t pool2th:1;
 422		uint64_t pool1th:1;
 423		uint64_t pool0th:1;
 424		uint64_t q7_perr:1;
 425		uint64_t q7_coff:1;
 426		uint64_t q7_und:1;
 427		uint64_t q6_perr:1;
 428		uint64_t q6_coff:1;
 429		uint64_t q6_und:1;
 430		uint64_t q5_perr:1;
 431		uint64_t q5_coff:1;
 432		uint64_t q5_und:1;
 433		uint64_t q4_perr:1;
 434		uint64_t q4_coff:1;
 435		uint64_t q4_und:1;
 436		uint64_t q3_perr:1;
 437		uint64_t q3_coff:1;
 438		uint64_t q3_und:1;
 439		uint64_t q2_perr:1;
 440		uint64_t q2_coff:1;
 441		uint64_t q2_und:1;
 442		uint64_t q1_perr:1;
 443		uint64_t q1_coff:1;
 444		uint64_t q1_und:1;
 445		uint64_t q0_perr:1;
 446		uint64_t q0_coff:1;
 447		uint64_t q0_und:1;
 448		uint64_t fed1_dbe:1;
 449		uint64_t fed1_sbe:1;
 450		uint64_t fed0_dbe:1;
 451		uint64_t fed0_sbe:1;
 452#else
 453		uint64_t fed0_sbe:1;
 454		uint64_t fed0_dbe:1;
 455		uint64_t fed1_sbe:1;
 456		uint64_t fed1_dbe:1;
 457		uint64_t q0_und:1;
 458		uint64_t q0_coff:1;
 459		uint64_t q0_perr:1;
 460		uint64_t q1_und:1;
 461		uint64_t q1_coff:1;
 462		uint64_t q1_perr:1;
 463		uint64_t q2_und:1;
 464		uint64_t q2_coff:1;
 465		uint64_t q2_perr:1;
 466		uint64_t q3_und:1;
 467		uint64_t q3_coff:1;
 468		uint64_t q3_perr:1;
 469		uint64_t q4_und:1;
 470		uint64_t q4_coff:1;
 471		uint64_t q4_perr:1;
 472		uint64_t q5_und:1;
 473		uint64_t q5_coff:1;
 474		uint64_t q5_perr:1;
 475		uint64_t q6_und:1;
 476		uint64_t q6_coff:1;
 477		uint64_t q6_perr:1;
 478		uint64_t q7_und:1;
 479		uint64_t q7_coff:1;
 480		uint64_t q7_perr:1;
 481		uint64_t pool0th:1;
 482		uint64_t pool1th:1;
 483		uint64_t pool2th:1;
 484		uint64_t pool3th:1;
 485		uint64_t pool4th:1;
 486		uint64_t pool5th:1;
 487		uint64_t pool6th:1;
 488		uint64_t pool7th:1;
 489		uint64_t free0:1;
 490		uint64_t free1:1;
 491		uint64_t free2:1;
 492		uint64_t free3:1;
 493		uint64_t free4:1;
 494		uint64_t free5:1;
 495		uint64_t free6:1;
 496		uint64_t free7:1;
 497		uint64_t res_44:5;
 498		uint64_t paddr_e:1;
 499		uint64_t reserved_50_63:14;
 500#endif
 501	} cn61xx;
 502	struct cvmx_fpa_int_enb_cn63xx {
 503#ifdef __BIG_ENDIAN_BITFIELD
 504		uint64_t reserved_44_63:20;
 505		uint64_t free7:1;
 506		uint64_t free6:1;
 507		uint64_t free5:1;
 508		uint64_t free4:1;
 509		uint64_t free3:1;
 510		uint64_t free2:1;
 511		uint64_t free1:1;
 512		uint64_t free0:1;
 513		uint64_t pool7th:1;
 514		uint64_t pool6th:1;
 515		uint64_t pool5th:1;
 516		uint64_t pool4th:1;
 517		uint64_t pool3th:1;
 518		uint64_t pool2th:1;
 519		uint64_t pool1th:1;
 520		uint64_t pool0th:1;
 521		uint64_t q7_perr:1;
 522		uint64_t q7_coff:1;
 523		uint64_t q7_und:1;
 524		uint64_t q6_perr:1;
 525		uint64_t q6_coff:1;
 526		uint64_t q6_und:1;
 527		uint64_t q5_perr:1;
 528		uint64_t q5_coff:1;
 529		uint64_t q5_und:1;
 530		uint64_t q4_perr:1;
 531		uint64_t q4_coff:1;
 532		uint64_t q4_und:1;
 533		uint64_t q3_perr:1;
 534		uint64_t q3_coff:1;
 535		uint64_t q3_und:1;
 536		uint64_t q2_perr:1;
 537		uint64_t q2_coff:1;
 538		uint64_t q2_und:1;
 539		uint64_t q1_perr:1;
 540		uint64_t q1_coff:1;
 541		uint64_t q1_und:1;
 542		uint64_t q0_perr:1;
 543		uint64_t q0_coff:1;
 544		uint64_t q0_und:1;
 545		uint64_t fed1_dbe:1;
 546		uint64_t fed1_sbe:1;
 547		uint64_t fed0_dbe:1;
 548		uint64_t fed0_sbe:1;
 549#else
 550		uint64_t fed0_sbe:1;
 551		uint64_t fed0_dbe:1;
 552		uint64_t fed1_sbe:1;
 553		uint64_t fed1_dbe:1;
 554		uint64_t q0_und:1;
 555		uint64_t q0_coff:1;
 556		uint64_t q0_perr:1;
 557		uint64_t q1_und:1;
 558		uint64_t q1_coff:1;
 559		uint64_t q1_perr:1;
 560		uint64_t q2_und:1;
 561		uint64_t q2_coff:1;
 562		uint64_t q2_perr:1;
 563		uint64_t q3_und:1;
 564		uint64_t q3_coff:1;
 565		uint64_t q3_perr:1;
 566		uint64_t q4_und:1;
 567		uint64_t q4_coff:1;
 568		uint64_t q4_perr:1;
 569		uint64_t q5_und:1;
 570		uint64_t q5_coff:1;
 571		uint64_t q5_perr:1;
 572		uint64_t q6_und:1;
 573		uint64_t q6_coff:1;
 574		uint64_t q6_perr:1;
 575		uint64_t q7_und:1;
 576		uint64_t q7_coff:1;
 577		uint64_t q7_perr:1;
 578		uint64_t pool0th:1;
 579		uint64_t pool1th:1;
 580		uint64_t pool2th:1;
 581		uint64_t pool3th:1;
 582		uint64_t pool4th:1;
 583		uint64_t pool5th:1;
 584		uint64_t pool6th:1;
 585		uint64_t pool7th:1;
 586		uint64_t free0:1;
 587		uint64_t free1:1;
 588		uint64_t free2:1;
 589		uint64_t free3:1;
 590		uint64_t free4:1;
 591		uint64_t free5:1;
 592		uint64_t free6:1;
 593		uint64_t free7:1;
 594		uint64_t reserved_44_63:20;
 595#endif
 596	} cn63xx;
 597	struct cvmx_fpa_int_enb_cn68xx {
 598#ifdef __BIG_ENDIAN_BITFIELD
 599		uint64_t reserved_50_63:14;
 600		uint64_t paddr_e:1;
 601		uint64_t pool8th:1;
 602		uint64_t q8_perr:1;
 603		uint64_t q8_coff:1;
 604		uint64_t q8_und:1;
 605		uint64_t free8:1;
 606		uint64_t free7:1;
 607		uint64_t free6:1;
 608		uint64_t free5:1;
 609		uint64_t free4:1;
 610		uint64_t free3:1;
 611		uint64_t free2:1;
 612		uint64_t free1:1;
 613		uint64_t free0:1;
 614		uint64_t pool7th:1;
 615		uint64_t pool6th:1;
 616		uint64_t pool5th:1;
 617		uint64_t pool4th:1;
 618		uint64_t pool3th:1;
 619		uint64_t pool2th:1;
 620		uint64_t pool1th:1;
 621		uint64_t pool0th:1;
 622		uint64_t q7_perr:1;
 623		uint64_t q7_coff:1;
 624		uint64_t q7_und:1;
 625		uint64_t q6_perr:1;
 626		uint64_t q6_coff:1;
 627		uint64_t q6_und:1;
 628		uint64_t q5_perr:1;
 629		uint64_t q5_coff:1;
 630		uint64_t q5_und:1;
 631		uint64_t q4_perr:1;
 632		uint64_t q4_coff:1;
 633		uint64_t q4_und:1;
 634		uint64_t q3_perr:1;
 635		uint64_t q3_coff:1;
 636		uint64_t q3_und:1;
 637		uint64_t q2_perr:1;
 638		uint64_t q2_coff:1;
 639		uint64_t q2_und:1;
 640		uint64_t q1_perr:1;
 641		uint64_t q1_coff:1;
 642		uint64_t q1_und:1;
 643		uint64_t q0_perr:1;
 644		uint64_t q0_coff:1;
 645		uint64_t q0_und:1;
 646		uint64_t fed1_dbe:1;
 647		uint64_t fed1_sbe:1;
 648		uint64_t fed0_dbe:1;
 649		uint64_t fed0_sbe:1;
 650#else
 651		uint64_t fed0_sbe:1;
 652		uint64_t fed0_dbe:1;
 653		uint64_t fed1_sbe:1;
 654		uint64_t fed1_dbe:1;
 655		uint64_t q0_und:1;
 656		uint64_t q0_coff:1;
 657		uint64_t q0_perr:1;
 658		uint64_t q1_und:1;
 659		uint64_t q1_coff:1;
 660		uint64_t q1_perr:1;
 661		uint64_t q2_und:1;
 662		uint64_t q2_coff:1;
 663		uint64_t q2_perr:1;
 664		uint64_t q3_und:1;
 665		uint64_t q3_coff:1;
 666		uint64_t q3_perr:1;
 667		uint64_t q4_und:1;
 668		uint64_t q4_coff:1;
 669		uint64_t q4_perr:1;
 670		uint64_t q5_und:1;
 671		uint64_t q5_coff:1;
 672		uint64_t q5_perr:1;
 673		uint64_t q6_und:1;
 674		uint64_t q6_coff:1;
 675		uint64_t q6_perr:1;
 676		uint64_t q7_und:1;
 677		uint64_t q7_coff:1;
 678		uint64_t q7_perr:1;
 679		uint64_t pool0th:1;
 680		uint64_t pool1th:1;
 681		uint64_t pool2th:1;
 682		uint64_t pool3th:1;
 683		uint64_t pool4th:1;
 684		uint64_t pool5th:1;
 685		uint64_t pool6th:1;
 686		uint64_t pool7th:1;
 687		uint64_t free0:1;
 688		uint64_t free1:1;
 689		uint64_t free2:1;
 690		uint64_t free3:1;
 691		uint64_t free4:1;
 692		uint64_t free5:1;
 693		uint64_t free6:1;
 694		uint64_t free7:1;
 695		uint64_t free8:1;
 696		uint64_t q8_und:1;
 697		uint64_t q8_coff:1;
 698		uint64_t q8_perr:1;
 699		uint64_t pool8th:1;
 700		uint64_t paddr_e:1;
 701		uint64_t reserved_50_63:14;
 702#endif
 703	} cn68xx;
 704};
 705
 706union cvmx_fpa_int_sum {
 707	uint64_t u64;
 708	struct cvmx_fpa_int_sum_s {
 709#ifdef __BIG_ENDIAN_BITFIELD
 710		uint64_t reserved_50_63:14;
 711		uint64_t paddr_e:1;
 712		uint64_t pool8th:1;
 713		uint64_t q8_perr:1;
 714		uint64_t q8_coff:1;
 715		uint64_t q8_und:1;
 716		uint64_t free8:1;
 717		uint64_t free7:1;
 718		uint64_t free6:1;
 719		uint64_t free5:1;
 720		uint64_t free4:1;
 721		uint64_t free3:1;
 722		uint64_t free2:1;
 723		uint64_t free1:1;
 724		uint64_t free0:1;
 725		uint64_t pool7th:1;
 726		uint64_t pool6th:1;
 727		uint64_t pool5th:1;
 728		uint64_t pool4th:1;
 729		uint64_t pool3th:1;
 730		uint64_t pool2th:1;
 731		uint64_t pool1th:1;
 732		uint64_t pool0th:1;
 733		uint64_t q7_perr:1;
 734		uint64_t q7_coff:1;
 735		uint64_t q7_und:1;
 736		uint64_t q6_perr:1;
 737		uint64_t q6_coff:1;
 738		uint64_t q6_und:1;
 739		uint64_t q5_perr:1;
 740		uint64_t q5_coff:1;
 741		uint64_t q5_und:1;
 742		uint64_t q4_perr:1;
 743		uint64_t q4_coff:1;
 744		uint64_t q4_und:1;
 745		uint64_t q3_perr:1;
 746		uint64_t q3_coff:1;
 747		uint64_t q3_und:1;
 748		uint64_t q2_perr:1;
 749		uint64_t q2_coff:1;
 750		uint64_t q2_und:1;
 751		uint64_t q1_perr:1;
 752		uint64_t q1_coff:1;
 753		uint64_t q1_und:1;
 754		uint64_t q0_perr:1;
 755		uint64_t q0_coff:1;
 756		uint64_t q0_und:1;
 757		uint64_t fed1_dbe:1;
 758		uint64_t fed1_sbe:1;
 759		uint64_t fed0_dbe:1;
 760		uint64_t fed0_sbe:1;
 761#else
 762		uint64_t fed0_sbe:1;
 763		uint64_t fed0_dbe:1;
 764		uint64_t fed1_sbe:1;
 765		uint64_t fed1_dbe:1;
 766		uint64_t q0_und:1;
 767		uint64_t q0_coff:1;
 768		uint64_t q0_perr:1;
 769		uint64_t q1_und:1;
 770		uint64_t q1_coff:1;
 771		uint64_t q1_perr:1;
 772		uint64_t q2_und:1;
 773		uint64_t q2_coff:1;
 774		uint64_t q2_perr:1;
 775		uint64_t q3_und:1;
 776		uint64_t q3_coff:1;
 777		uint64_t q3_perr:1;
 778		uint64_t q4_und:1;
 779		uint64_t q4_coff:1;
 780		uint64_t q4_perr:1;
 781		uint64_t q5_und:1;
 782		uint64_t q5_coff:1;
 783		uint64_t q5_perr:1;
 784		uint64_t q6_und:1;
 785		uint64_t q6_coff:1;
 786		uint64_t q6_perr:1;
 787		uint64_t q7_und:1;
 788		uint64_t q7_coff:1;
 789		uint64_t q7_perr:1;
 790		uint64_t pool0th:1;
 791		uint64_t pool1th:1;
 792		uint64_t pool2th:1;
 793		uint64_t pool3th:1;
 794		uint64_t pool4th:1;
 795		uint64_t pool5th:1;
 796		uint64_t pool6th:1;
 797		uint64_t pool7th:1;
 798		uint64_t free0:1;
 799		uint64_t free1:1;
 800		uint64_t free2:1;
 801		uint64_t free3:1;
 802		uint64_t free4:1;
 803		uint64_t free5:1;
 804		uint64_t free6:1;
 805		uint64_t free7:1;
 806		uint64_t free8:1;
 807		uint64_t q8_und:1;
 808		uint64_t q8_coff:1;
 809		uint64_t q8_perr:1;
 810		uint64_t pool8th:1;
 811		uint64_t paddr_e:1;
 812		uint64_t reserved_50_63:14;
 813#endif
 814	} s;
 815	struct cvmx_fpa_int_sum_cn30xx {
 816#ifdef __BIG_ENDIAN_BITFIELD
 817		uint64_t reserved_28_63:36;
 818		uint64_t q7_perr:1;
 819		uint64_t q7_coff:1;
 820		uint64_t q7_und:1;
 821		uint64_t q6_perr:1;
 822		uint64_t q6_coff:1;
 823		uint64_t q6_und:1;
 824		uint64_t q5_perr:1;
 825		uint64_t q5_coff:1;
 826		uint64_t q5_und:1;
 827		uint64_t q4_perr:1;
 828		uint64_t q4_coff:1;
 829		uint64_t q4_und:1;
 830		uint64_t q3_perr:1;
 831		uint64_t q3_coff:1;
 832		uint64_t q3_und:1;
 833		uint64_t q2_perr:1;
 834		uint64_t q2_coff:1;
 835		uint64_t q2_und:1;
 836		uint64_t q1_perr:1;
 837		uint64_t q1_coff:1;
 838		uint64_t q1_und:1;
 839		uint64_t q0_perr:1;
 840		uint64_t q0_coff:1;
 841		uint64_t q0_und:1;
 842		uint64_t fed1_dbe:1;
 843		uint64_t fed1_sbe:1;
 844		uint64_t fed0_dbe:1;
 845		uint64_t fed0_sbe:1;
 846#else
 847		uint64_t fed0_sbe:1;
 848		uint64_t fed0_dbe:1;
 849		uint64_t fed1_sbe:1;
 850		uint64_t fed1_dbe:1;
 851		uint64_t q0_und:1;
 852		uint64_t q0_coff:1;
 853		uint64_t q0_perr:1;
 854		uint64_t q1_und:1;
 855		uint64_t q1_coff:1;
 856		uint64_t q1_perr:1;
 857		uint64_t q2_und:1;
 858		uint64_t q2_coff:1;
 859		uint64_t q2_perr:1;
 860		uint64_t q3_und:1;
 861		uint64_t q3_coff:1;
 862		uint64_t q3_perr:1;
 863		uint64_t q4_und:1;
 864		uint64_t q4_coff:1;
 865		uint64_t q4_perr:1;
 866		uint64_t q5_und:1;
 867		uint64_t q5_coff:1;
 868		uint64_t q5_perr:1;
 869		uint64_t q6_und:1;
 870		uint64_t q6_coff:1;
 871		uint64_t q6_perr:1;
 872		uint64_t q7_und:1;
 873		uint64_t q7_coff:1;
 874		uint64_t q7_perr:1;
 875		uint64_t reserved_28_63:36;
 876#endif
 877	} cn30xx;
 878	struct cvmx_fpa_int_sum_cn61xx {
 879#ifdef __BIG_ENDIAN_BITFIELD
 880		uint64_t reserved_50_63:14;
 881		uint64_t paddr_e:1;
 882		uint64_t reserved_44_48:5;
 883		uint64_t free7:1;
 884		uint64_t free6:1;
 885		uint64_t free5:1;
 886		uint64_t free4:1;
 887		uint64_t free3:1;
 888		uint64_t free2:1;
 889		uint64_t free1:1;
 890		uint64_t free0:1;
 891		uint64_t pool7th:1;
 892		uint64_t pool6th:1;
 893		uint64_t pool5th:1;
 894		uint64_t pool4th:1;
 895		uint64_t pool3th:1;
 896		uint64_t pool2th:1;
 897		uint64_t pool1th:1;
 898		uint64_t pool0th:1;
 899		uint64_t q7_perr:1;
 900		uint64_t q7_coff:1;
 901		uint64_t q7_und:1;
 902		uint64_t q6_perr:1;
 903		uint64_t q6_coff:1;
 904		uint64_t q6_und:1;
 905		uint64_t q5_perr:1;
 906		uint64_t q5_coff:1;
 907		uint64_t q5_und:1;
 908		uint64_t q4_perr:1;
 909		uint64_t q4_coff:1;
 910		uint64_t q4_und:1;
 911		uint64_t q3_perr:1;
 912		uint64_t q3_coff:1;
 913		uint64_t q3_und:1;
 914		uint64_t q2_perr:1;
 915		uint64_t q2_coff:1;
 916		uint64_t q2_und:1;
 917		uint64_t q1_perr:1;
 918		uint64_t q1_coff:1;
 919		uint64_t q1_und:1;
 920		uint64_t q0_perr:1;
 921		uint64_t q0_coff:1;
 922		uint64_t q0_und:1;
 923		uint64_t fed1_dbe:1;
 924		uint64_t fed1_sbe:1;
 925		uint64_t fed0_dbe:1;
 926		uint64_t fed0_sbe:1;
 927#else
 928		uint64_t fed0_sbe:1;
 929		uint64_t fed0_dbe:1;
 930		uint64_t fed1_sbe:1;
 931		uint64_t fed1_dbe:1;
 932		uint64_t q0_und:1;
 933		uint64_t q0_coff:1;
 934		uint64_t q0_perr:1;
 935		uint64_t q1_und:1;
 936		uint64_t q1_coff:1;
 937		uint64_t q1_perr:1;
 938		uint64_t q2_und:1;
 939		uint64_t q2_coff:1;
 940		uint64_t q2_perr:1;
 941		uint64_t q3_und:1;
 942		uint64_t q3_coff:1;
 943		uint64_t q3_perr:1;
 944		uint64_t q4_und:1;
 945		uint64_t q4_coff:1;
 946		uint64_t q4_perr:1;
 947		uint64_t q5_und:1;
 948		uint64_t q5_coff:1;
 949		uint64_t q5_perr:1;
 950		uint64_t q6_und:1;
 951		uint64_t q6_coff:1;
 952		uint64_t q6_perr:1;
 953		uint64_t q7_und:1;
 954		uint64_t q7_coff:1;
 955		uint64_t q7_perr:1;
 956		uint64_t pool0th:1;
 957		uint64_t pool1th:1;
 958		uint64_t pool2th:1;
 959		uint64_t pool3th:1;
 960		uint64_t pool4th:1;
 961		uint64_t pool5th:1;
 962		uint64_t pool6th:1;
 963		uint64_t pool7th:1;
 964		uint64_t free0:1;
 965		uint64_t free1:1;
 966		uint64_t free2:1;
 967		uint64_t free3:1;
 968		uint64_t free4:1;
 969		uint64_t free5:1;
 970		uint64_t free6:1;
 971		uint64_t free7:1;
 972		uint64_t reserved_44_48:5;
 973		uint64_t paddr_e:1;
 974		uint64_t reserved_50_63:14;
 975#endif
 976	} cn61xx;
 977	struct cvmx_fpa_int_sum_cn63xx {
 978#ifdef __BIG_ENDIAN_BITFIELD
 979		uint64_t reserved_44_63:20;
 980		uint64_t free7:1;
 981		uint64_t free6:1;
 982		uint64_t free5:1;
 983		uint64_t free4:1;
 984		uint64_t free3:1;
 985		uint64_t free2:1;
 986		uint64_t free1:1;
 987		uint64_t free0:1;
 988		uint64_t pool7th:1;
 989		uint64_t pool6th:1;
 990		uint64_t pool5th:1;
 991		uint64_t pool4th:1;
 992		uint64_t pool3th:1;
 993		uint64_t pool2th:1;
 994		uint64_t pool1th:1;
 995		uint64_t pool0th:1;
 996		uint64_t q7_perr:1;
 997		uint64_t q7_coff:1;
 998		uint64_t q7_und:1;
 999		uint64_t q6_perr:1;
1000		uint64_t q6_coff:1;
1001		uint64_t q6_und:1;
1002		uint64_t q5_perr:1;
1003		uint64_t q5_coff:1;
1004		uint64_t q5_und:1;
1005		uint64_t q4_perr:1;
1006		uint64_t q4_coff:1;
1007		uint64_t q4_und:1;
1008		uint64_t q3_perr:1;
1009		uint64_t q3_coff:1;
1010		uint64_t q3_und:1;
1011		uint64_t q2_perr:1;
1012		uint64_t q2_coff:1;
1013		uint64_t q2_und:1;
1014		uint64_t q1_perr:1;
1015		uint64_t q1_coff:1;
1016		uint64_t q1_und:1;
1017		uint64_t q0_perr:1;
1018		uint64_t q0_coff:1;
1019		uint64_t q0_und:1;
1020		uint64_t fed1_dbe:1;
1021		uint64_t fed1_sbe:1;
1022		uint64_t fed0_dbe:1;
1023		uint64_t fed0_sbe:1;
1024#else
1025		uint64_t fed0_sbe:1;
1026		uint64_t fed0_dbe:1;
1027		uint64_t fed1_sbe:1;
1028		uint64_t fed1_dbe:1;
1029		uint64_t q0_und:1;
1030		uint64_t q0_coff:1;
1031		uint64_t q0_perr:1;
1032		uint64_t q1_und:1;
1033		uint64_t q1_coff:1;
1034		uint64_t q1_perr:1;
1035		uint64_t q2_und:1;
1036		uint64_t q2_coff:1;
1037		uint64_t q2_perr:1;
1038		uint64_t q3_und:1;
1039		uint64_t q3_coff:1;
1040		uint64_t q3_perr:1;
1041		uint64_t q4_und:1;
1042		uint64_t q4_coff:1;
1043		uint64_t q4_perr:1;
1044		uint64_t q5_und:1;
1045		uint64_t q5_coff:1;
1046		uint64_t q5_perr:1;
1047		uint64_t q6_und:1;
1048		uint64_t q6_coff:1;
1049		uint64_t q6_perr:1;
1050		uint64_t q7_und:1;
1051		uint64_t q7_coff:1;
1052		uint64_t q7_perr:1;
1053		uint64_t pool0th:1;
1054		uint64_t pool1th:1;
1055		uint64_t pool2th:1;
1056		uint64_t pool3th:1;
1057		uint64_t pool4th:1;
1058		uint64_t pool5th:1;
1059		uint64_t pool6th:1;
1060		uint64_t pool7th:1;
1061		uint64_t free0:1;
1062		uint64_t free1:1;
1063		uint64_t free2:1;
1064		uint64_t free3:1;
1065		uint64_t free4:1;
1066		uint64_t free5:1;
1067		uint64_t free6:1;
1068		uint64_t free7:1;
1069		uint64_t reserved_44_63:20;
1070#endif
1071	} cn63xx;
1072};
1073
1074union cvmx_fpa_packet_threshold {
1075	uint64_t u64;
1076	struct cvmx_fpa_packet_threshold_s {
1077#ifdef __BIG_ENDIAN_BITFIELD
1078		uint64_t reserved_32_63:32;
1079		uint64_t thresh:32;
1080#else
1081		uint64_t thresh:32;
1082		uint64_t reserved_32_63:32;
1083#endif
1084	} s;
1085};
1086
1087union cvmx_fpa_poolx_end_addr {
1088	uint64_t u64;
1089	struct cvmx_fpa_poolx_end_addr_s {
1090#ifdef __BIG_ENDIAN_BITFIELD
1091		uint64_t reserved_33_63:31;
1092		uint64_t addr:33;
1093#else
1094		uint64_t addr:33;
1095		uint64_t reserved_33_63:31;
1096#endif
1097	} s;
1098};
1099
1100union cvmx_fpa_poolx_start_addr {
1101	uint64_t u64;
1102	struct cvmx_fpa_poolx_start_addr_s {
1103#ifdef __BIG_ENDIAN_BITFIELD
1104		uint64_t reserved_33_63:31;
1105		uint64_t addr:33;
1106#else
1107		uint64_t addr:33;
1108		uint64_t reserved_33_63:31;
1109#endif
1110	} s;
1111};
1112
1113union cvmx_fpa_poolx_threshold {
1114	uint64_t u64;
1115	struct cvmx_fpa_poolx_threshold_s {
1116#ifdef __BIG_ENDIAN_BITFIELD
1117		uint64_t reserved_32_63:32;
1118		uint64_t thresh:32;
1119#else
1120		uint64_t thresh:32;
1121		uint64_t reserved_32_63:32;
1122#endif
1123	} s;
1124	struct cvmx_fpa_poolx_threshold_cn61xx {
1125#ifdef __BIG_ENDIAN_BITFIELD
1126		uint64_t reserved_29_63:35;
1127		uint64_t thresh:29;
1128#else
1129		uint64_t thresh:29;
1130		uint64_t reserved_29_63:35;
1131#endif
1132	} cn61xx;
1133};
1134
1135union cvmx_fpa_quex_available {
1136	uint64_t u64;
1137	struct cvmx_fpa_quex_available_s {
1138#ifdef __BIG_ENDIAN_BITFIELD
1139		uint64_t reserved_32_63:32;
1140		uint64_t que_siz:32;
1141#else
1142		uint64_t que_siz:32;
1143		uint64_t reserved_32_63:32;
1144#endif
1145	} s;
1146	struct cvmx_fpa_quex_available_cn30xx {
1147#ifdef __BIG_ENDIAN_BITFIELD
1148		uint64_t reserved_29_63:35;
1149		uint64_t que_siz:29;
1150#else
1151		uint64_t que_siz:29;
1152		uint64_t reserved_29_63:35;
1153#endif
1154	} cn30xx;
1155};
1156
1157union cvmx_fpa_quex_page_index {
1158	uint64_t u64;
1159	struct cvmx_fpa_quex_page_index_s {
1160#ifdef __BIG_ENDIAN_BITFIELD
1161		uint64_t reserved_25_63:39;
1162		uint64_t pg_num:25;
1163#else
1164		uint64_t pg_num:25;
1165		uint64_t reserved_25_63:39;
1166#endif
1167	} s;
1168};
1169
1170union cvmx_fpa_que8_page_index {
1171	uint64_t u64;
1172	struct cvmx_fpa_que8_page_index_s {
1173#ifdef __BIG_ENDIAN_BITFIELD
1174		uint64_t reserved_25_63:39;
1175		uint64_t pg_num:25;
1176#else
1177		uint64_t pg_num:25;
1178		uint64_t reserved_25_63:39;
1179#endif
1180	} s;
1181};
1182
1183union cvmx_fpa_que_act {
1184	uint64_t u64;
1185	struct cvmx_fpa_que_act_s {
1186#ifdef __BIG_ENDIAN_BITFIELD
1187		uint64_t reserved_29_63:35;
1188		uint64_t act_que:3;
1189		uint64_t act_indx:26;
1190#else
1191		uint64_t act_indx:26;
1192		uint64_t act_que:3;
1193		uint64_t reserved_29_63:35;
1194#endif
1195	} s;
1196};
1197
1198union cvmx_fpa_que_exp {
1199	uint64_t u64;
1200	struct cvmx_fpa_que_exp_s {
1201#ifdef __BIG_ENDIAN_BITFIELD
1202		uint64_t reserved_29_63:35;
1203		uint64_t exp_que:3;
1204		uint64_t exp_indx:26;
1205#else
1206		uint64_t exp_indx:26;
1207		uint64_t exp_que:3;
1208		uint64_t reserved_29_63:35;
1209#endif
1210	} s;
1211};
1212
1213union cvmx_fpa_wart_ctl {
1214	uint64_t u64;
1215	struct cvmx_fpa_wart_ctl_s {
1216#ifdef __BIG_ENDIAN_BITFIELD
1217		uint64_t reserved_16_63:48;
1218		uint64_t ctl:16;
1219#else
1220		uint64_t ctl:16;
1221		uint64_t reserved_16_63:48;
1222#endif
1223	} s;
1224};
1225
1226union cvmx_fpa_wart_status {
1227	uint64_t u64;
1228	struct cvmx_fpa_wart_status_s {
1229#ifdef __BIG_ENDIAN_BITFIELD
1230		uint64_t reserved_32_63:32;
1231		uint64_t status:32;
1232#else
1233		uint64_t status:32;
1234		uint64_t reserved_32_63:32;
1235#endif
1236	} s;
1237};
1238
1239union cvmx_fpa_wqe_threshold {
1240	uint64_t u64;
1241	struct cvmx_fpa_wqe_threshold_s {
1242#ifdef __BIG_ENDIAN_BITFIELD
1243		uint64_t reserved_32_63:32;
1244		uint64_t thresh:32;
1245#else
1246		uint64_t thresh:32;
1247		uint64_t reserved_32_63:32;
1248#endif
1249	} s;
1250};
1251
1252#endif