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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2000-2006 PMC-Sierra INC.
4 *
5 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
6 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
7 * SOFTWARE.
8 */
9
10#ifndef _MSP_PCI_H_
11#define _MSP_PCI_H_
12
13#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
14
15/*
16 * It is convenient to program the OATRAN register so that
17 * Athena virtual address space and PCI address space are
18 * the same. This is not a requirement, just a convenience.
19 *
20 * The only hard restrictions on the value of OATRAN is that
21 * OATRAN must not be programmed to allow translated memory
22 * addresses to fall within the lowest 512MB of
23 * PCI address space. This region is hardcoded
24 * for use as Athena PCI Host Controller target
25 * access memory space to the Athena's SDRAM.
26 *
27 * Note that OATRAN applies only to memory accesses, not
28 * to I/O accesses.
29 *
30 * To program OATRAN to make Athena virtual address space
31 * and PCI address space have the same values, OATRAN
32 * is to be programmed to 0xB8000000. The top seven
33 * bits of the value mimic the seven bits clipped off
34 * by the PCI Host controller.
35 *
36 * With OATRAN at the said value, when the CPU does
37 * an access to its virtual address at, say 0xB900_5000,
38 * the address appearing on the PCI bus will be
39 * 0xB900_5000.
40 * - Michael Penner
41 */
42#define MSP_PCI_OATRAN 0xB8000000UL
43
44#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
45#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
46#define MSP_PCI_SPACE_END \
47 (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
48#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
49#define MSP_PCI_IOSPACE_SIZE 0x1000
50#define MSP_PCI_IOSPACE_END \
51 (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
52
53/* IRQ for PCI status interrupts */
54#define PCI_STAT_IRQ 20
55
56#define QFLUSH_REG_1 0xB7F40000
57
58typedef volatile unsigned int pcireg;
59typedef void * volatile ppcireg;
60
61struct pci_block_copy
62{
63 pcireg unused1; /* +0x00 */
64 pcireg unused2; /* +0x04 */
65 ppcireg unused3; /* +0x08 */
66 ppcireg unused4; /* +0x0C */
67 pcireg unused5; /* +0x10 */
68 pcireg unused6; /* +0x14 */
69 pcireg unused7; /* +0x18 */
70 ppcireg unused8; /* +0x1C */
71 ppcireg unused9; /* +0x20 */
72 pcireg unusedA; /* +0x24 */
73 ppcireg unusedB; /* +0x28 */
74 ppcireg unusedC; /* +0x2C */
75};
76
77enum
78{
79 config_device_vendor, /* 0 */
80 config_status_command, /* 1 */
81 config_class_revision, /* 2 */
82 config_BIST_header_latency_cache, /* 3 */
83 config_BAR0, /* 4 */
84 config_BAR1, /* 5 */
85 config_BAR2, /* 6 */
86 config_not_used7, /* 7 */
87 config_not_used8, /* 8 */
88 config_not_used9, /* 9 */
89 config_CIS, /* 10 */
90 config_subsystem, /* 11 */
91 config_not_used12, /* 12 */
92 config_capabilities, /* 13 */
93 config_not_used14, /* 14 */
94 config_lat_grant_irq, /* 15 */
95 config_message_control,/* 16 */
96 config_message_addr, /* 17 */
97 config_message_data, /* 18 */
98 config_VPD_addr, /* 19 */
99 config_VPD_data, /* 20 */
100 config_maxregs /* 21 - number of registers */
101};
102
103struct msp_pci_regs
104{
105 pcireg hop_unused_00; /* +0x00 */
106 pcireg hop_unused_04; /* +0x04 */
107 pcireg hop_unused_08; /* +0x08 */
108 pcireg hop_unused_0C; /* +0x0C */
109 pcireg hop_unused_10; /* +0x10 */
110 pcireg hop_unused_14; /* +0x14 */
111 pcireg hop_unused_18; /* +0x18 */
112 pcireg hop_unused_1C; /* +0x1C */
113 pcireg hop_unused_20; /* +0x20 */
114 pcireg hop_unused_24; /* +0x24 */
115 pcireg hop_unused_28; /* +0x28 */
116 pcireg hop_unused_2C; /* +0x2C */
117 pcireg hop_unused_30; /* +0x30 */
118 pcireg hop_unused_34; /* +0x34 */
119 pcireg if_control; /* +0x38 */
120 pcireg oatran; /* +0x3C */
121 pcireg reset_ctl; /* +0x40 */
122 pcireg config_addr; /* +0x44 */
123 pcireg hop_unused_48; /* +0x48 */
124 pcireg msg_signaled_int_status; /* +0x4C */
125 pcireg msg_signaled_int_mask; /* +0x50 */
126 pcireg if_status; /* +0x54 */
127 pcireg if_mask; /* +0x58 */
128 pcireg hop_unused_5C; /* +0x5C */
129 pcireg hop_unused_60; /* +0x60 */
130 pcireg hop_unused_64; /* +0x64 */
131 pcireg hop_unused_68; /* +0x68 */
132 pcireg hop_unused_6C; /* +0x6C */
133 pcireg hop_unused_70; /* +0x70 */
134
135 struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
136
137 pcireg error_hdr1; /* +0xE0 */
138 pcireg error_hdr2; /* +0xE4 */
139
140 pcireg config[config_maxregs] __attribute__((aligned(256)));
141
142};
143
144#define BPCI_CFGADDR_BUSNUM_SHF 16
145#define BPCI_CFGADDR_FUNCTNUM_SHF 8
146#define BPCI_CFGADDR_REGNUM_SHF 2
147#define BPCI_CFGADDR_ENABLE (1<<31)
148
149#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
150#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
151#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
152#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
153#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
154#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
155#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
156
157#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
158#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
159#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
160#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
161#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
162#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
163#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
164#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
165#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
166#define BPCI_IFSTATUS_SER (1<<19) /* System error */
167#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
168#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
169#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
170#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
171#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
172#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
173#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
174#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
175#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
176
177#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
178#define BPCI_RESETCTL_RT (1<<4) /* Release time */
179#define BPCI_RESETCTL_CT (1<<8) /* Config time */
180#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
181#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
182#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
183
184extern struct msp_pci_regs msp_pci_regs
185 __attribute__((section(".register")));
186extern unsigned long msp_pci_config_space
187 __attribute__((section(".register")));
188
189#endif /* !_MSP_PCI_H_ */