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1// SPDX-License-Identifier: GPL-2.0
2
3/dts-v1/;
4/include/ "zynq-zturn-common.dtsi"
5
6/ {
7 model = "Zynq Z-Turn MYIR Board";
8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
9};
10
11&gem0 {
12 ethernet_phy: ethernet-phy@0 {
13 reg = <0x0>;
14 };
15};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
4 * Copyright (C) 2017 Alexander Graf <agraf@suse.de>
5 *
6 * Based on zynq-zed.dts which is:
7 * Copyright (C) 2011 - 2014 Xilinx
8 * Copyright (C) 2012 National Instruments Corp.
9 *
10 */
11
12/dts-v1/;
13/include/ "zynq-7000.dtsi"
14
15/ {
16 model = "Zynq Z-Turn MYIR Board";
17 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
18
19 aliases {
20 ethernet0 = &gem0;
21 serial0 = &uart1;
22 serial1 = &uart0;
23 mmc0 = &sdhci0;
24 };
25
26 memory@0 {
27 device_type = "memory";
28 reg = <0x0 0x40000000>;
29 };
30
31 chosen {
32 stdout-path = "serial0:115200n8";
33 };
34
35 gpio-leds {
36 compatible = "gpio-leds";
37 usr-led1 {
38 label = "usr-led1";
39 gpios = <&gpio0 0x0 0x1>;
40 default-state = "off";
41 };
42
43 usr-led2 {
44 label = "usr-led2";
45 gpios = <&gpio0 0x9 0x1>;
46 default-state = "off";
47 };
48 };
49
50 gpio-keys {
51 compatible = "gpio-keys";
52 autorepeat;
53 K1 {
54 label = "K1";
55 gpios = <&gpio0 0x32 0x1>;
56 linux,code = <0x66>;
57 wakeup-source;
58 autorepeat;
59 };
60 };
61};
62
63&clkc {
64 ps-clk-frequency = <33333333>;
65};
66
67&gem0 {
68 status = "okay";
69 phy-mode = "rgmii-id";
70 phy-handle = <ðernet_phy>;
71
72 ethernet_phy: ethernet-phy@0 {
73 reg = <0x0>;
74 };
75};
76
77&sdhci0 {
78 status = "okay";
79};
80
81&uart0 {
82 status = "okay";
83};
84
85&uart1 {
86 status = "okay";
87};
88
89&usb0 {
90 status = "okay";
91 dr_mode = "host";
92};
93
94&can0 {
95 status = "okay";
96};
97
98&i2c0 {
99 status = "okay";
100 clock-frequency = <400000>;
101
102 stlm75@49 {
103 status = "okay";
104 compatible = "lm75";
105 reg = <0x49>;
106 };
107
108 accelerometer@53 {
109 compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
110 reg = <0x53>;
111 interrupt-parent = <&intc>;
112 interrupts = <0x0 0x1e 0x4>;
113 };
114};