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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Linaro Ltd
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
9#include <dt-bindings/mfd/dbx500-prcmu.h>
10#include <dt-bindings/arm/ux500_pm_domains.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 /* This stablilizes the device enumeration */
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 spi0 = &spi0;
26 spi1 = &spi1;
27 spi2 = &spi2;
28 spi3 = &spi3;
29 serial0 = &serial0;
30 serial1 = &serial1;
31 serial2 = &serial2;
32 };
33
34 chosen {
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "ste,dbx500-smp";
41
42 cpu-map {
43 cluster0 {
44 core0 {
45 cpu = <&CPU0>;
46 };
47 core1 {
48 cpu = <&CPU1>;
49 };
50 };
51 };
52 CPU0: cpu@300 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <0x300>;
56 clocks = <&prcmu_clk PRCMU_ARMSS>;
57 clock-names = "cpu";
58 clock-latency = <20000>;
59 #cooling-cells = <2>;
60 };
61 CPU1: cpu@301 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a9";
64 reg = <0x301>;
65 };
66 };
67
68 thermal-zones {
69 /*
70 * Thermal zone for the SoC, using the thermal sensor in the
71 * PRCMU for temperature and the cpufreq driver for passive
72 * cooling.
73 */
74 cpu_thermal: cpu-thermal {
75 polling-delay-passive = <250>;
76 /*
77 * This sensor fires interrupts to update the thermal
78 * zone, so no polling is needed.
79 */
80 polling-delay = <0>;
81
82 thermal-sensors = <&thermal>;
83
84 trips {
85 cpu_alert: cpu-alert {
86 temperature = <70000>;
87 hysteresis = <2000>;
88 type = "passive";
89 };
90 cpu-crit {
91 temperature = <85000>;
92 hysteresis = <0>;
93 type = "critical";
94 };
95 };
96
97 cooling-maps {
98 trip = <&cpu_alert>;
99 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
100 contribution = <100>;
101 };
102 };
103 };
104
105 soc {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "stericsson,db8500", "simple-bus";
109 interrupt-parent = <&intc>;
110 ranges;
111
112 ptm@801ae000 {
113 compatible = "arm,coresight-etm3x", "arm,primecell";
114 reg = <0x801ae000 0x1000>;
115
116 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
117 clock-names = "apb_pclk", "atclk";
118 cpu = <&CPU0>;
119 out-ports {
120 port {
121 ptm0_out_port: endpoint {
122 remote-endpoint = <&funnel_in_port0>;
123 };
124 };
125 };
126 };
127
128 ptm@801af000 {
129 compatible = "arm,coresight-etm3x", "arm,primecell";
130 reg = <0x801af000 0x1000>;
131
132 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
133 clock-names = "apb_pclk", "atclk";
134 cpu = <&CPU1>;
135 out-ports {
136 port {
137 ptm1_out_port: endpoint {
138 remote-endpoint = <&funnel_in_port1>;
139 };
140 };
141 };
142 };
143
144 funnel@801a6000 {
145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
146 reg = <0x801a6000 0x1000>;
147
148 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
149 clock-names = "apb_pclk", "atclk";
150 out-ports {
151 port {
152 funnel_out_port: endpoint {
153 remote-endpoint =
154 <&replicator_in_port0>;
155 };
156 };
157 };
158
159 in-ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 port@0 {
164 reg = <0>;
165 funnel_in_port0: endpoint {
166 remote-endpoint = <&ptm0_out_port>;
167 };
168 };
169
170 port@1 {
171 reg = <1>;
172 funnel_in_port1: endpoint {
173 remote-endpoint = <&ptm1_out_port>;
174 };
175 };
176 };
177 };
178
179 replicator {
180 compatible = "arm,coresight-static-replicator";
181 clocks = <&prcmu_clk PRCMU_APEATCLK>;
182 clock-names = "atclk";
183
184 out-ports {
185 #address-cells = <1>;
186 #size-cells = <0>;
187
188 port@0 {
189 reg = <0>;
190 replicator_out_port0: endpoint {
191 remote-endpoint = <&tpiu_in_port>;
192 };
193 };
194 port@1 {
195 reg = <1>;
196 replicator_out_port1: endpoint {
197 remote-endpoint = <&etb_in_port>;
198 };
199 };
200 };
201
202 in-ports {
203 port {
204 replicator_in_port0: endpoint {
205 remote-endpoint = <&funnel_out_port>;
206 };
207 };
208 };
209 };
210
211 tpiu@80190000 {
212 compatible = "arm,coresight-tpiu", "arm,primecell";
213 reg = <0x80190000 0x1000>;
214
215 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
216 clock-names = "apb_pclk", "atclk";
217 in-ports {
218 port {
219 tpiu_in_port: endpoint {
220 remote-endpoint = <&replicator_out_port0>;
221 };
222 };
223 };
224 };
225
226 etb@801a4000 {
227 compatible = "arm,coresight-etb10", "arm,primecell";
228 reg = <0x801a4000 0x1000>;
229
230 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
231 clock-names = "apb_pclk", "atclk";
232 in-ports {
233 port {
234 etb_in_port: endpoint {
235 remote-endpoint = <&replicator_out_port1>;
236 };
237 };
238 };
239 };
240
241 intc: interrupt-controller@a0411000 {
242 compatible = "arm,cortex-a9-gic";
243 #interrupt-cells = <3>;
244 #address-cells = <1>;
245 interrupt-controller;
246 reg = <0xa0411000 0x1000>,
247 <0xa0410100 0x100>;
248 };
249
250 scu@a0410000 {
251 compatible = "arm,cortex-a9-scu";
252 reg = <0xa0410000 0x100>;
253 };
254
255 /*
256 * The backup RAM is used for retention during sleep
257 * and various things like spin tables
258 */
259 backupram@80150000 {
260 compatible = "ste,dbx500-backupram";
261 reg = <0x80150000 0x2000>;
262 };
263
264 L2: cache-controller {
265 compatible = "arm,pl310-cache";
266 reg = <0xa0412000 0x1000>;
267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
268 cache-unified;
269 cache-level = <2>;
270 };
271
272 pmu {
273 compatible = "arm,cortex-a9-pmu";
274 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
275 };
276
277 pm_domains: pm_domains0 {
278 compatible = "stericsson,ux500-pm-domains";
279 #power-domain-cells = <1>;
280 };
281
282 clocks {
283 compatible = "stericsson,u8500-clks";
284 /*
285 * Registers for the CLKRST block on peripheral
286 * groups 1, 2, 3, 5, 6,
287 */
288 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
289 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
290 <0xa03cf000 0x1000>;
291
292 prcmu_clk: prcmu-clock {
293 #clock-cells = <1>;
294 };
295
296 prcc_pclk: prcc-periph-clock {
297 #clock-cells = <2>;
298 };
299
300 prcc_kclk: prcc-kernel-clock {
301 #clock-cells = <2>;
302 };
303
304 prcc_reset: prcc-reset-controller {
305 #reset-cells = <2>;
306 };
307
308 rtc_clk: rtc32k-clock {
309 #clock-cells = <0>;
310 };
311
312 smp_twd_clk: smp-twd-clock {
313 #clock-cells = <0>;
314 };
315 };
316
317 mtu@a03c6000 {
318 /* Nomadik System Timer */
319 compatible = "st,nomadik-mtu";
320 reg = <0xa03c6000 0x1000>;
321 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
322
323 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
324 clock-names = "timclk", "apb_pclk";
325 };
326
327 timer@a0410600 {
328 compatible = "arm,cortex-a9-twd-timer";
329 reg = <0xa0410600 0x20>;
330 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
331
332 clocks = <&smp_twd_clk>;
333 };
334
335 watchdog@a0410620 {
336 compatible = "arm,cortex-a9-twd-wdt";
337 reg = <0xa0410620 0x20>;
338 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
339 clocks = <&smp_twd_clk>;
340 };
341
342 rtc@80154000 {
343 compatible = "arm,pl031", "arm,primecell";
344 reg = <0x80154000 0x1000>;
345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
346
347 clocks = <&rtc_clk>;
348 clock-names = "apb_pclk";
349 };
350
351 gpio0: gpio@8012e000 {
352 compatible = "stericsson,db8500-gpio",
353 "st,nomadik-gpio";
354 reg = <0x8012e000 0x80>;
355 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 st,supports-sleepmode;
359 gpio-controller;
360 #gpio-cells = <2>;
361 gpio-bank = <0>;
362 gpio-ranges = <&pinctrl 0 0 32>;
363 clocks = <&prcc_pclk 1 9>;
364 };
365
366 gpio1: gpio@8012e080 {
367 compatible = "stericsson,db8500-gpio",
368 "st,nomadik-gpio";
369 reg = <0x8012e080 0x80>;
370 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 st,supports-sleepmode;
374 gpio-controller;
375 #gpio-cells = <2>;
376 gpio-bank = <1>;
377 gpio-ranges = <&pinctrl 0 32 5>;
378 clocks = <&prcc_pclk 1 9>;
379 };
380
381 gpio2: gpio@8000e000 {
382 compatible = "stericsson,db8500-gpio",
383 "st,nomadik-gpio";
384 reg = <0x8000e000 0x80>;
385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 st,supports-sleepmode;
389 gpio-controller;
390 #gpio-cells = <2>;
391 gpio-bank = <2>;
392 gpio-ranges = <&pinctrl 0 64 32>;
393 clocks = <&prcc_pclk 3 8>;
394 };
395
396 gpio3: gpio@8000e080 {
397 compatible = "stericsson,db8500-gpio",
398 "st,nomadik-gpio";
399 reg = <0x8000e080 0x80>;
400 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 st,supports-sleepmode;
404 gpio-controller;
405 #gpio-cells = <2>;
406 gpio-bank = <3>;
407 gpio-ranges = <&pinctrl 0 96 2>;
408 clocks = <&prcc_pclk 3 8>;
409 };
410
411 gpio4: gpio@8000e100 {
412 compatible = "stericsson,db8500-gpio",
413 "st,nomadik-gpio";
414 reg = <0x8000e100 0x80>;
415 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 st,supports-sleepmode;
419 gpio-controller;
420 #gpio-cells = <2>;
421 gpio-bank = <4>;
422 gpio-ranges = <&pinctrl 0 128 32>;
423 clocks = <&prcc_pclk 3 8>;
424 };
425
426 gpio5: gpio@8000e180 {
427 compatible = "stericsson,db8500-gpio",
428 "st,nomadik-gpio";
429 reg = <0x8000e180 0x80>;
430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 st,supports-sleepmode;
434 gpio-controller;
435 #gpio-cells = <2>;
436 gpio-bank = <5>;
437 gpio-ranges = <&pinctrl 0 160 12>;
438 clocks = <&prcc_pclk 3 8>;
439 };
440
441 gpio6: gpio@8011e000 {
442 compatible = "stericsson,db8500-gpio",
443 "st,nomadik-gpio";
444 reg = <0x8011e000 0x80>;
445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 st,supports-sleepmode;
449 gpio-controller;
450 #gpio-cells = <2>;
451 gpio-bank = <6>;
452 gpio-ranges = <&pinctrl 0 192 32>;
453 clocks = <&prcc_pclk 2 11>;
454 };
455
456 gpio7: gpio@8011e080 {
457 compatible = "stericsson,db8500-gpio",
458 "st,nomadik-gpio";
459 reg = <0x8011e080 0x80>;
460 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 st,supports-sleepmode;
464 gpio-controller;
465 #gpio-cells = <2>;
466 gpio-bank = <7>;
467 gpio-ranges = <&pinctrl 0 224 7>;
468 clocks = <&prcc_pclk 2 11>;
469 };
470
471 gpio8: gpio@a03fe000 {
472 compatible = "stericsson,db8500-gpio",
473 "st,nomadik-gpio";
474 reg = <0xa03fe000 0x80>;
475 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 st,supports-sleepmode;
479 gpio-controller;
480 #gpio-cells = <2>;
481 gpio-bank = <8>;
482 gpio-ranges = <&pinctrl 0 256 12>;
483 clocks = <&prcc_pclk 5 1>;
484 };
485
486 pinctrl: pinctrl {
487 compatible = "stericsson,db8500-pinctrl";
488 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
489 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
490 <&gpio8>;
491 prcm = <&prcmu>;
492 };
493
494 usb_per5@a03e0000 {
495 compatible = "stericsson,db8500-musb";
496 reg = <0xa03e0000 0x10000>;
497 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "mc";
499
500 dr_mode = "otg";
501
502 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
503 <&dma 38 0 0x0>, /* Logical - MemToDev */
504 <&dma 37 0 0x2>, /* Logical - DevToMem */
505 <&dma 37 0 0x0>, /* Logical - MemToDev */
506 <&dma 36 0 0x2>, /* Logical - DevToMem */
507 <&dma 36 0 0x0>, /* Logical - MemToDev */
508 <&dma 19 0 0x2>, /* Logical - DevToMem */
509 <&dma 19 0 0x0>, /* Logical - MemToDev */
510 <&dma 18 0 0x2>, /* Logical - DevToMem */
511 <&dma 18 0 0x0>, /* Logical - MemToDev */
512 <&dma 17 0 0x2>, /* Logical - DevToMem */
513 <&dma 17 0 0x0>, /* Logical - MemToDev */
514 <&dma 16 0 0x2>, /* Logical - DevToMem */
515 <&dma 16 0 0x0>, /* Logical - MemToDev */
516 <&dma 39 0 0x2>, /* Logical - DevToMem */
517 <&dma 39 0 0x0>; /* Logical - MemToDev */
518
519 dma-names = "iep_1_9", "oep_1_9",
520 "iep_2_10", "oep_2_10",
521 "iep_3_11", "oep_3_11",
522 "iep_4_12", "oep_4_12",
523 "iep_5_13", "oep_5_13",
524 "iep_6_14", "oep_6_14",
525 "iep_7_15", "oep_7_15",
526 "iep_8", "oep_8";
527
528 clocks = <&prcc_pclk 5 0>;
529 };
530
531 dma: dma-controller@801C0000 {
532 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
533 reg = <0x801C0000 0x1000 0x40010000 0x800>;
534 reg-names = "base", "lcpa";
535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
536
537 #dma-cells = <3>;
538 memcpy-channels = <56 57 58 59 60>;
539
540 clocks = <&prcmu_clk PRCMU_DMACLK>;
541 };
542
543 prcmu: prcmu@80157000 {
544 compatible = "stericsson,db8500-prcmu", "syscon";
545 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
546 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
547 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
549 #size-cells = <1>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
552 ranges;
553
554 prcmu-timer-4@80157450 {
555 compatible = "stericsson,db8500-prcmu-timer-4";
556 reg = <0x80157450 0xC>;
557 };
558
559 thermal: thermal@801573c0 {
560 compatible = "stericsson,db8500-thermal";
561 reg = <0x801573c0 0x40>;
562 interrupt-parent = <&prcmu>;
563 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
564 <22 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
566 #thermal-sensor-cells = <0>;
567 };
568
569 db8500-prcmu-regulators {
570 compatible = "stericsson,db8500-prcmu-regulator";
571
572 // DB8500_REGULATOR_VAPE
573 db8500_vape_reg: db8500_vape {
574 regulator-always-on;
575 };
576
577 // DB8500_REGULATOR_VARM
578 db8500_varm_reg: db8500_varm {
579 };
580
581 // DB8500_REGULATOR_VMODEM
582 db8500_vmodem_reg: db8500_vmodem {
583 };
584
585 // DB8500_REGULATOR_VPLL
586 db8500_vpll_reg: db8500_vpll {
587 };
588
589 // DB8500_REGULATOR_VSMPS1
590 db8500_vsmps1_reg: db8500_vsmps1 {
591 };
592
593 // DB8500_REGULATOR_VSMPS2
594 db8500_vsmps2_reg: db8500_vsmps2 {
595 };
596
597 // DB8500_REGULATOR_VSMPS3
598 db8500_vsmps3_reg: db8500_vsmps3 {
599 };
600
601 // DB8500_REGULATOR_VRF1
602 db8500_vrf1_reg: db8500_vrf1 {
603 };
604
605 // DB8500_REGULATOR_SWITCH_SVAMMDSP
606 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
607 };
608
609 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
610 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
611 };
612
613 // DB8500_REGULATOR_SWITCH_SVAPIPE
614 db8500_sva_pipe_reg: db8500_sva_pipe {
615 };
616
617 // DB8500_REGULATOR_SWITCH_SIAMMDSP
618 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
619 };
620
621 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
622 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
623 };
624
625 // DB8500_REGULATOR_SWITCH_SIAPIPE
626 db8500_sia_pipe_reg: db8500_sia_pipe {
627 };
628
629 // DB8500_REGULATOR_SWITCH_SGA
630 db8500_sga_reg: db8500_sga {
631 vin-supply = <&db8500_vape_reg>;
632 };
633
634 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
635 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
636 vin-supply = <&db8500_vape_reg>;
637 };
638
639 // DB8500_REGULATOR_SWITCH_ESRAM12
640 db8500_esram12_reg: db8500_esram12 {
641 };
642
643 // DB8500_REGULATOR_SWITCH_ESRAM12RET
644 db8500_esram12_ret_reg: db8500_esram12_ret {
645 };
646
647 // DB8500_REGULATOR_SWITCH_ESRAM34
648 db8500_esram34_reg: db8500_esram34 {
649 };
650
651 // DB8500_REGULATOR_SWITCH_ESRAM34RET
652 db8500_esram34_ret_reg: db8500_esram34_ret {
653 };
654 };
655 };
656
657 i2c0: i2c@80004000 {
658 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
659 reg = <0x80004000 0x1000>;
660 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
661
662 #address-cells = <1>;
663 #size-cells = <0>;
664
665 clock-frequency = <400000>;
666 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
667 clock-names = "i2cclk", "apb_pclk";
668 power-domains = <&pm_domains DOMAIN_VAPE>;
669 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
670
671 status = "disabled";
672 };
673
674 i2c1: i2c@80122000 {
675 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
676 reg = <0x80122000 0x1000>;
677 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
678
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 clock-frequency = <400000>;
683
684 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
685 clock-names = "i2cclk", "apb_pclk";
686 power-domains = <&pm_domains DOMAIN_VAPE>;
687 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>;
688
689 status = "disabled";
690 };
691
692 i2c2: i2c@80128000 {
693 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
694 reg = <0x80128000 0x1000>;
695 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
696
697 #address-cells = <1>;
698 #size-cells = <0>;
699
700 clock-frequency = <400000>;
701
702 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
703 clock-names = "i2cclk", "apb_pclk";
704 power-domains = <&pm_domains DOMAIN_VAPE>;
705 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>;
706
707 status = "disabled";
708 };
709
710 i2c3: i2c@80110000 {
711 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
712 reg = <0x80110000 0x1000>;
713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
714
715 #address-cells = <1>;
716 #size-cells = <0>;
717
718 clock-frequency = <400000>;
719
720 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
721 clock-names = "i2cclk", "apb_pclk";
722 power-domains = <&pm_domains DOMAIN_VAPE>;
723 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>;
724
725 status = "disabled";
726 };
727
728 i2c4: i2c@8012a000 {
729 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
730 reg = <0x8012a000 0x1000>;
731 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
732
733 #address-cells = <1>;
734 #size-cells = <0>;
735
736 clock-frequency = <400000>;
737
738 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
739 clock-names = "i2cclk", "apb_pclk";
740 power-domains = <&pm_domains DOMAIN_VAPE>;
741 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>;
742
743 status = "disabled";
744 };
745
746 ssp0: spi@80002000 {
747 compatible = "arm,pl022", "arm,primecell";
748 reg = <0x80002000 0x1000>;
749 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
750 #address-cells = <1>;
751 #size-cells = <0>;
752 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
753 clock-names = "sspclk", "apb_pclk";
754 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
755 <&dma 8 0 0x0>; /* Logical - MemToDev */
756 dma-names = "rx", "tx";
757 power-domains = <&pm_domains DOMAIN_VAPE>;
758 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>;
759
760 status = "disabled";
761 };
762
763 ssp1: spi@80003000 {
764 compatible = "arm,pl022", "arm,primecell";
765 reg = <0x80003000 0x1000>;
766 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
770 clock-names = "sspclk", "apb_pclk";
771 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
772 <&dma 9 0 0x0>; /* Logical - MemToDev */
773 dma-names = "rx", "tx";
774 power-domains = <&pm_domains DOMAIN_VAPE>;
775 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>;
776
777 status = "disabled";
778 };
779
780 spi0: spi@8011a000 {
781 compatible = "arm,pl022", "arm,primecell";
782 reg = <0x8011a000 0x1000>;
783 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
784 #address-cells = <1>;
785 #size-cells = <0>;
786 /* Same clock wired to kernel and pclk */
787 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
788 clock-names = "sspclk", "apb_pclk";
789 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
790 <&dma 0 0 0x0>; /* Logical - MemToDev */
791 dma-names = "rx", "tx";
792 power-domains = <&pm_domains DOMAIN_VAPE>;
793
794 status = "disabled";
795 };
796
797 spi1: spi@80112000 {
798 compatible = "arm,pl022", "arm,primecell";
799 reg = <0x80112000 0x1000>;
800 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
801 #address-cells = <1>;
802 #size-cells = <0>;
803 /* Same clock wired to kernel and pclk */
804 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
805 clock-names = "sspclk", "apb_pclk";
806 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
807 <&dma 35 0 0x0>; /* Logical - MemToDev */
808 dma-names = "rx", "tx";
809 power-domains = <&pm_domains DOMAIN_VAPE>;
810
811 status = "disabled";
812 };
813
814 spi2: spi@80111000 {
815 compatible = "arm,pl022", "arm,primecell";
816 reg = <0x80111000 0x1000>;
817 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>;
819 #size-cells = <0>;
820 /* Same clock wired to kernel and pclk */
821 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
822 clock-names = "sspclk", "apb_pclk";
823 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
824 <&dma 33 0 0x0>; /* Logical - MemToDev */
825 dma-names = "rx", "tx";
826 power-domains = <&pm_domains DOMAIN_VAPE>;
827
828 status = "disabled";
829 };
830
831 spi3: spi@80129000 {
832 compatible = "arm,pl022", "arm,primecell";
833 reg = <0x80129000 0x1000>;
834 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
835 #address-cells = <1>;
836 #size-cells = <0>;
837 /* Same clock wired to kernel and pclk */
838 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
839 clock-names = "sspclk", "apb_pclk";
840 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
841 <&dma 40 0 0x0>; /* Logical - MemToDev */
842 dma-names = "rx", "tx";
843 power-domains = <&pm_domains DOMAIN_VAPE>;
844 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>;
845
846 status = "disabled";
847 };
848
849 serial0: uart@80120000 {
850 compatible = "arm,pl011", "arm,primecell";
851 reg = <0x80120000 0x1000>;
852 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
853
854 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
855 <&dma 13 0 0x0>; /* Logical - MemToDev */
856 dma-names = "rx", "tx";
857
858 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
859 clock-names = "uart", "apb_pclk";
860 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>;
861
862 status = "disabled";
863 };
864
865 serial1: uart@80121000 {
866 compatible = "arm,pl011", "arm,primecell";
867 reg = <0x80121000 0x1000>;
868 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
869
870 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
871 <&dma 12 0 0x0>; /* Logical - MemToDev */
872 dma-names = "rx", "tx";
873
874 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
875 clock-names = "uart", "apb_pclk";
876 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>;
877
878 status = "disabled";
879 };
880
881 serial2: uart@80007000 {
882 compatible = "arm,pl011", "arm,primecell";
883 reg = <0x80007000 0x1000>;
884 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
885
886 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
887 <&dma 11 0 0x0>; /* Logical - MemToDev */
888 dma-names = "rx", "tx";
889
890 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
891 clock-names = "uart", "apb_pclk";
892 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>;
893
894 status = "disabled";
895 };
896
897 mmc@80126000 {
898 compatible = "arm,pl18x", "arm,primecell";
899 reg = <0x80126000 0x1000>;
900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
901
902 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
903 <&dma 29 0 0x0>; /* Logical - MemToDev */
904 dma-names = "rx", "tx";
905
906 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
907 clock-names = "sdi", "apb_pclk";
908 power-domains = <&pm_domains DOMAIN_VAPE>;
909 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>;
910
911 status = "disabled";
912 };
913
914 mmc@80118000 {
915 compatible = "arm,pl18x", "arm,primecell";
916 reg = <0x80118000 0x1000>;
917 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
918
919 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
920 <&dma 32 0 0x0>; /* Logical - MemToDev */
921 dma-names = "rx", "tx";
922
923 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
924 clock-names = "sdi", "apb_pclk";
925 power-domains = <&pm_domains DOMAIN_VAPE>;
926 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>;
927
928 status = "disabled";
929 };
930
931 mmc@80005000 {
932 compatible = "arm,pl18x", "arm,primecell";
933 reg = <0x80005000 0x1000>;
934 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
935
936 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
937 <&dma 28 0 0x0>; /* Logical - MemToDev */
938 dma-names = "rx", "tx";
939
940 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
941 clock-names = "sdi", "apb_pclk";
942 power-domains = <&pm_domains DOMAIN_VAPE>;
943 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>;
944
945 status = "disabled";
946 };
947
948 mmc@80119000 {
949 compatible = "arm,pl18x", "arm,primecell";
950 reg = <0x80119000 0x1000>;
951 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
952
953 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
954 <&dma 41 0 0x0>; /* Logical - MemToDev */
955 dma-names = "rx", "tx";
956
957 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
958 clock-names = "sdi", "apb_pclk";
959 power-domains = <&pm_domains DOMAIN_VAPE>;
960 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>;
961
962 status = "disabled";
963 };
964
965 mmc@80114000 {
966 compatible = "arm,pl18x", "arm,primecell";
967 reg = <0x80114000 0x1000>;
968 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
969
970 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
971 <&dma 42 0 0x0>; /* Logical - MemToDev */
972 dma-names = "rx", "tx";
973
974 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
975 clock-names = "sdi", "apb_pclk";
976 power-domains = <&pm_domains DOMAIN_VAPE>;
977 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>;
978
979 status = "disabled";
980 };
981
982 mmc@80008000 {
983 compatible = "arm,pl18x", "arm,primecell";
984 reg = <0x80008000 0x1000>;
985 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
986
987 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
988 <&dma 43 0 0x0>; /* Logical - MemToDev */
989 dma-names = "rx", "tx";
990
991 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
992 clock-names = "sdi", "apb_pclk";
993 power-domains = <&pm_domains DOMAIN_VAPE>;
994 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>;
995
996 status = "disabled";
997 };
998
999 sound {
1000 compatible = "stericsson,snd-soc-mop500";
1001 stericsson,cpu-dai = <&msp1 &msp3>;
1002 };
1003
1004 msp0: msp@80123000 {
1005 compatible = "stericsson,ux500-msp-i2s";
1006 reg = <0x80123000 0x1000>;
1007 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1008 v-ape-supply = <&db8500_vape_reg>;
1009
1010 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1011 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1012 dma-names = "rx", "tx";
1013
1014 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1015 clock-names = "msp", "apb_pclk";
1016 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>;
1017
1018 status = "disabled";
1019 };
1020
1021 msp1: msp@80124000 {
1022 compatible = "stericsson,ux500-msp-i2s";
1023 reg = <0x80124000 0x1000>;
1024 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1025 v-ape-supply = <&db8500_vape_reg>;
1026
1027 /* This DMA channel only exist on DB8500 v1 */
1028 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1029 dma-names = "tx";
1030
1031 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1032 clock-names = "msp", "apb_pclk";
1033 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>;
1034
1035 status = "disabled";
1036 };
1037
1038 // HDMI sound
1039 msp2: msp@80117000 {
1040 compatible = "stericsson,ux500-msp-i2s";
1041 reg = <0x80117000 0x1000>;
1042 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1043 v-ape-supply = <&db8500_vape_reg>;
1044
1045 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1046 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1047 HighPrio - Fixed */
1048 dma-names = "rx", "tx";
1049
1050 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1051 clock-names = "msp", "apb_pclk";
1052 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>;
1053
1054 status = "disabled";
1055 };
1056
1057 msp3: msp@80125000 {
1058 compatible = "stericsson,ux500-msp-i2s";
1059 reg = <0x80125000 0x1000>;
1060 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1061 v-ape-supply = <&db8500_vape_reg>;
1062
1063 /* This DMA channel only exist on DB8500 v2 */
1064 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1065 dma-names = "rx";
1066
1067 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1068 clock-names = "msp", "apb_pclk";
1069 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>;
1070
1071 status = "disabled";
1072 };
1073
1074 external-bus@50000000 {
1075 compatible = "simple-bus";
1076 reg = <0x50000000 0x4000000>;
1077 #address-cells = <1>;
1078 #size-cells = <1>;
1079 ranges = <0 0x50000000 0x4000000>;
1080 status = "disabled";
1081 };
1082
1083 gpu@a0300000 {
1084 /*
1085 * This block is referred to as "Smart Graphics Adapter SGA500"
1086 * in documentation but is in practice a pretty straight-forward
1087 * MALI-400 GPU block.
1088 */
1089 compatible = "stericsson,db8500-mali", "arm,mali-400";
1090 reg = <0xa0300000 0x10000>;
1091 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1096 interrupt-names = "gp",
1097 "gpmmu",
1098 "pp0",
1099 "ppmmu0",
1100 "combined";
1101 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1102 clock-names = "bus", "core";
1103 mali-supply = <&db8500_sga_reg>;
1104 power-domains = <&pm_domains DOMAIN_VAPE>;
1105 };
1106
1107 mcde@a0350000 {
1108 compatible = "ste,mcde";
1109 reg = <0xa0350000 0x1000>;
1110 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1111 epod-supply = <&db8500_b2r2_mcde_reg>;
1112 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1113 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1114 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1115 clock-names = "mcde", "lcd", "hdmi";
1116 #address-cells = <1>;
1117 #size-cells = <1>;
1118 ranges;
1119 status = "disabled";
1120
1121 dsi0: dsi@a0351000 {
1122 compatible = "ste,mcde-dsi";
1123 reg = <0xa0351000 0x1000>;
1124 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1125 clock-names = "hs", "lp";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 };
1129 dsi1: dsi@a0352000 {
1130 compatible = "ste,mcde-dsi";
1131 reg = <0xa0352000 0x1000>;
1132 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1133 clock-names = "hs", "lp";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 };
1137 dsi2: dsi@a0353000 {
1138 compatible = "ste,mcde-dsi";
1139 reg = <0xa0353000 0x1000>;
1140 /* This DSI port only has the Low Power / Energy Save clock */
1141 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1142 clock-names = "lp";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 };
1146 };
1147
1148 cryp@a03cb000 {
1149 compatible = "stericsson,ux500-cryp";
1150 reg = <0xa03cb000 0x1000>;
1151 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&prcc_pclk 6 1>;
1153 power-domains = <&pm_domains DOMAIN_VAPE>;
1154 };
1155
1156 hash@a03c2000 {
1157 compatible = "stericsson,ux500-hash";
1158 reg = <0xa03c2000 0x1000>;
1159 clocks = <&prcc_pclk 6 2>;
1160 power-domains = <&pm_domains DOMAIN_VAPE>;
1161 };
1162 };
1163};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Linaro Ltd
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/mfd/dbx500-prcmu.h>
9#include <dt-bindings/arm/ux500_pm_domains.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 chosen {
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "ste,dbx500-smp";
24
25 cpu-map {
26 cluster0 {
27 core0 {
28 cpu = <&CPU0>;
29 };
30 core1 {
31 cpu = <&CPU1>;
32 };
33 };
34 };
35 CPU0: cpu@300 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0x300>;
39 /* cpufreq controls */
40 operating-points = <998400 0
41 800000 0
42 400000 0
43 200000 0>;
44 clocks = <&prcmu_clk PRCMU_ARMSS>;
45 clock-names = "cpu";
46 clock-latency = <20000>;
47 #cooling-cells = <2>;
48 };
49 CPU1: cpu@301 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a9";
52 reg = <0x301>;
53 };
54 };
55
56 thermal-zones {
57 /*
58 * Thermal zone for the SoC, using the thermal sensor in the
59 * PRCMU for temperature and the cpufreq driver for passive
60 * cooling.
61 */
62 cpu_thermal: cpu-thermal {
63 polling-delay-passive = <250>;
64 /*
65 * This sensor fires interrupts to update the thermal
66 * zone, so no polling is needed.
67 */
68 polling-delay = <0>;
69
70 thermal-sensors = <&thermal>;
71
72 trips {
73 cpu_alert: cpu-alert {
74 temperature = <70000>;
75 hysteresis = <2000>;
76 type = "passive";
77 };
78 cpu-crit {
79 temperature = <85000>;
80 hysteresis = <0>;
81 type = "critical";
82 };
83 };
84
85 cooling-maps {
86 trip = <&cpu_alert>;
87 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
88 contribution = <100>;
89 };
90 };
91 };
92
93 soc {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "stericsson,db8500";
97 interrupt-parent = <&intc>;
98 ranges;
99
100 ptm@801ae000 {
101 compatible = "arm,coresight-etm3x", "arm,primecell";
102 reg = <0x801ae000 0x1000>;
103
104 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
105 clock-names = "apb_pclk", "atclk";
106 cpu = <&CPU0>;
107 out-ports {
108 port {
109 ptm0_out_port: endpoint {
110 remote-endpoint = <&funnel_in_port0>;
111 };
112 };
113 };
114 };
115
116 ptm@801af000 {
117 compatible = "arm,coresight-etm3x", "arm,primecell";
118 reg = <0x801af000 0x1000>;
119
120 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
121 clock-names = "apb_pclk", "atclk";
122 cpu = <&CPU1>;
123 out-ports {
124 port {
125 ptm1_out_port: endpoint {
126 remote-endpoint = <&funnel_in_port1>;
127 };
128 };
129 };
130 };
131
132 funnel@801a6000 {
133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
134 reg = <0x801a6000 0x1000>;
135
136 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
137 clock-names = "apb_pclk", "atclk";
138 out-ports {
139 port {
140 funnel_out_port: endpoint {
141 remote-endpoint =
142 <&replicator_in_port0>;
143 };
144 };
145 };
146
147 in-ports {
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 port@0 {
152 reg = <0>;
153 funnel_in_port0: endpoint {
154 remote-endpoint = <&ptm0_out_port>;
155 };
156 };
157
158 port@1 {
159 reg = <1>;
160 funnel_in_port1: endpoint {
161 remote-endpoint = <&ptm1_out_port>;
162 };
163 };
164 };
165 };
166
167 replicator {
168 compatible = "arm,coresight-static-replicator";
169 clocks = <&prcmu_clk PRCMU_APEATCLK>;
170 clock-names = "atclk";
171
172 out-ports {
173 #address-cells = <1>;
174 #size-cells = <0>;
175
176 port@0 {
177 reg = <0>;
178 replicator_out_port0: endpoint {
179 remote-endpoint = <&tpiu_in_port>;
180 };
181 };
182 port@1 {
183 reg = <1>;
184 replicator_out_port1: endpoint {
185 remote-endpoint = <&etb_in_port>;
186 };
187 };
188 };
189
190 in-ports {
191 port {
192 replicator_in_port0: endpoint {
193 remote-endpoint = <&funnel_out_port>;
194 };
195 };
196 };
197 };
198
199 tpiu@80190000 {
200 compatible = "arm,coresight-tpiu", "arm,primecell";
201 reg = <0x80190000 0x1000>;
202
203 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
204 clock-names = "apb_pclk", "atclk";
205 in-ports {
206 port {
207 tpiu_in_port: endpoint {
208 remote-endpoint = <&replicator_out_port0>;
209 };
210 };
211 };
212 };
213
214 etb@801a4000 {
215 compatible = "arm,coresight-etb10", "arm,primecell";
216 reg = <0x801a4000 0x1000>;
217
218 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
219 clock-names = "apb_pclk", "atclk";
220 in-ports {
221 port {
222 etb_in_port: endpoint {
223 remote-endpoint = <&replicator_out_port1>;
224 };
225 };
226 };
227 };
228
229 intc: interrupt-controller@a0411000 {
230 compatible = "arm,cortex-a9-gic";
231 #interrupt-cells = <3>;
232 #address-cells = <1>;
233 interrupt-controller;
234 reg = <0xa0411000 0x1000>,
235 <0xa0410100 0x100>;
236 };
237
238 scu@a0410000 {
239 compatible = "arm,cortex-a9-scu";
240 reg = <0xa0410000 0x100>;
241 };
242
243 /*
244 * The backup RAM is used for retention during sleep
245 * and various things like spin tables
246 */
247 backupram@80150000 {
248 compatible = "ste,dbx500-backupram";
249 reg = <0x80150000 0x2000>;
250 };
251
252 L2: l2-cache {
253 compatible = "arm,pl310-cache";
254 reg = <0xa0412000 0x1000>;
255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
256 cache-unified;
257 cache-level = <2>;
258 };
259
260 pmu {
261 compatible = "arm,cortex-a9-pmu";
262 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
263 };
264
265 pm_domains: pm_domains0 {
266 compatible = "stericsson,ux500-pm-domains";
267 #power-domain-cells = <1>;
268 };
269
270 clocks {
271 compatible = "stericsson,u8500-clks";
272 /*
273 * Registers for the CLKRST block on peripheral
274 * groups 1, 2, 3, 5, 6,
275 */
276 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
277 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
278 <0xa03cf000 0x1000>;
279
280 prcmu_clk: prcmu-clock {
281 #clock-cells = <1>;
282 };
283
284 prcc_pclk: prcc-periph-clock {
285 #clock-cells = <2>;
286 };
287
288 prcc_kclk: prcc-kernel-clock {
289 #clock-cells = <2>;
290 };
291
292 rtc_clk: rtc32k-clock {
293 #clock-cells = <0>;
294 };
295
296 smp_twd_clk: smp-twd-clock {
297 #clock-cells = <0>;
298 };
299 };
300
301 mtu@a03c6000 {
302 /* Nomadik System Timer */
303 compatible = "st,nomadik-mtu";
304 reg = <0xa03c6000 0x1000>;
305 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
306
307 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
308 clock-names = "timclk", "apb_pclk";
309 };
310
311 timer@a0410600 {
312 compatible = "arm,cortex-a9-twd-timer";
313 reg = <0xa0410600 0x20>;
314 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
315
316 clocks = <&smp_twd_clk>;
317 };
318
319 watchdog@a0410620 {
320 compatible = "arm,cortex-a9-twd-wdt";
321 reg = <0xa0410620 0x20>;
322 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
323 clocks = <&smp_twd_clk>;
324 };
325
326 rtc@80154000 {
327 compatible = "arm,rtc-pl031", "arm,primecell";
328 reg = <0x80154000 0x1000>;
329 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
330
331 clocks = <&rtc_clk>;
332 clock-names = "apb_pclk";
333 };
334
335 gpio0: gpio@8012e000 {
336 compatible = "stericsson,db8500-gpio",
337 "st,nomadik-gpio";
338 reg = <0x8012e000 0x80>;
339 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 st,supports-sleepmode;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-bank = <0>;
346 gpio-ranges = <&pinctrl 0 0 32>;
347 clocks = <&prcc_pclk 1 9>;
348 };
349
350 gpio1: gpio@8012e080 {
351 compatible = "stericsson,db8500-gpio",
352 "st,nomadik-gpio";
353 reg = <0x8012e080 0x80>;
354 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 st,supports-sleepmode;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-bank = <1>;
361 gpio-ranges = <&pinctrl 0 32 5>;
362 clocks = <&prcc_pclk 1 9>;
363 };
364
365 gpio2: gpio@8000e000 {
366 compatible = "stericsson,db8500-gpio",
367 "st,nomadik-gpio";
368 reg = <0x8000e000 0x80>;
369 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 st,supports-sleepmode;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-bank = <2>;
376 gpio-ranges = <&pinctrl 0 64 32>;
377 clocks = <&prcc_pclk 3 8>;
378 };
379
380 gpio3: gpio@8000e080 {
381 compatible = "stericsson,db8500-gpio",
382 "st,nomadik-gpio";
383 reg = <0x8000e080 0x80>;
384 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 st,supports-sleepmode;
388 gpio-controller;
389 #gpio-cells = <2>;
390 gpio-bank = <3>;
391 gpio-ranges = <&pinctrl 0 96 2>;
392 clocks = <&prcc_pclk 3 8>;
393 };
394
395 gpio4: gpio@8000e100 {
396 compatible = "stericsson,db8500-gpio",
397 "st,nomadik-gpio";
398 reg = <0x8000e100 0x80>;
399 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 st,supports-sleepmode;
403 gpio-controller;
404 #gpio-cells = <2>;
405 gpio-bank = <4>;
406 gpio-ranges = <&pinctrl 0 128 32>;
407 clocks = <&prcc_pclk 3 8>;
408 };
409
410 gpio5: gpio@8000e180 {
411 compatible = "stericsson,db8500-gpio",
412 "st,nomadik-gpio";
413 reg = <0x8000e180 0x80>;
414 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 st,supports-sleepmode;
418 gpio-controller;
419 #gpio-cells = <2>;
420 gpio-bank = <5>;
421 gpio-ranges = <&pinctrl 0 160 12>;
422 clocks = <&prcc_pclk 3 8>;
423 };
424
425 gpio6: gpio@8011e000 {
426 compatible = "stericsson,db8500-gpio",
427 "st,nomadik-gpio";
428 reg = <0x8011e000 0x80>;
429 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 st,supports-sleepmode;
433 gpio-controller;
434 #gpio-cells = <2>;
435 gpio-bank = <6>;
436 gpio-ranges = <&pinctrl 0 192 32>;
437 clocks = <&prcc_pclk 2 11>;
438 };
439
440 gpio7: gpio@8011e080 {
441 compatible = "stericsson,db8500-gpio",
442 "st,nomadik-gpio";
443 reg = <0x8011e080 0x80>;
444 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 st,supports-sleepmode;
448 gpio-controller;
449 #gpio-cells = <2>;
450 gpio-bank = <7>;
451 gpio-ranges = <&pinctrl 0 224 7>;
452 clocks = <&prcc_pclk 2 11>;
453 };
454
455 gpio8: gpio@a03fe000 {
456 compatible = "stericsson,db8500-gpio",
457 "st,nomadik-gpio";
458 reg = <0xa03fe000 0x80>;
459 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 st,supports-sleepmode;
463 gpio-controller;
464 #gpio-cells = <2>;
465 gpio-bank = <8>;
466 gpio-ranges = <&pinctrl 0 256 12>;
467 clocks = <&prcc_pclk 5 1>;
468 };
469
470 pinctrl: pinctrl {
471 compatible = "stericsson,db8500-pinctrl";
472 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
473 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
474 <&gpio8>;
475 prcm = <&prcmu>;
476 };
477
478 usb_per5@a03e0000 {
479 compatible = "stericsson,db8500-musb";
480 reg = <0xa03e0000 0x10000>;
481 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "mc";
483
484 dr_mode = "otg";
485
486 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
487 <&dma 38 0 0x0>, /* Logical - MemToDev */
488 <&dma 37 0 0x2>, /* Logical - DevToMem */
489 <&dma 37 0 0x0>, /* Logical - MemToDev */
490 <&dma 36 0 0x2>, /* Logical - DevToMem */
491 <&dma 36 0 0x0>, /* Logical - MemToDev */
492 <&dma 19 0 0x2>, /* Logical - DevToMem */
493 <&dma 19 0 0x0>, /* Logical - MemToDev */
494 <&dma 18 0 0x2>, /* Logical - DevToMem */
495 <&dma 18 0 0x0>, /* Logical - MemToDev */
496 <&dma 17 0 0x2>, /* Logical - DevToMem */
497 <&dma 17 0 0x0>, /* Logical - MemToDev */
498 <&dma 16 0 0x2>, /* Logical - DevToMem */
499 <&dma 16 0 0x0>, /* Logical - MemToDev */
500 <&dma 39 0 0x2>, /* Logical - DevToMem */
501 <&dma 39 0 0x0>; /* Logical - MemToDev */
502
503 dma-names = "iep_1_9", "oep_1_9",
504 "iep_2_10", "oep_2_10",
505 "iep_3_11", "oep_3_11",
506 "iep_4_12", "oep_4_12",
507 "iep_5_13", "oep_5_13",
508 "iep_6_14", "oep_6_14",
509 "iep_7_15", "oep_7_15",
510 "iep_8", "oep_8";
511
512 clocks = <&prcc_pclk 5 0>;
513 };
514
515 dma: dma-controller@801C0000 {
516 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
517 reg = <0x801C0000 0x1000 0x40010000 0x800>;
518 reg-names = "base", "lcpa";
519 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
520
521 #dma-cells = <3>;
522 memcpy-channels = <56 57 58 59 60>;
523
524 clocks = <&prcmu_clk PRCMU_DMACLK>;
525 };
526
527 prcmu: prcmu@80157000 {
528 compatible = "stericsson,db8500-prcmu", "syscon";
529 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
530 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
531 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
532 #address-cells = <1>;
533 #size-cells = <1>;
534 interrupt-controller;
535 #interrupt-cells = <2>;
536 ranges;
537
538 prcmu-timer-4@80157450 {
539 compatible = "stericsson,db8500-prcmu-timer-4";
540 reg = <0x80157450 0xC>;
541 };
542
543 thermal: thermal@801573c0 {
544 compatible = "stericsson,db8500-thermal";
545 reg = <0x801573c0 0x40>;
546 interrupt-parent = <&prcmu>;
547 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
548 <22 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
550 #thermal-sensor-cells = <0>;
551 };
552
553 db8500-prcmu-regulators {
554 compatible = "stericsson,db8500-prcmu-regulator";
555
556 // DB8500_REGULATOR_VAPE
557 db8500_vape_reg: db8500_vape {
558 regulator-always-on;
559 };
560
561 // DB8500_REGULATOR_VARM
562 db8500_varm_reg: db8500_varm {
563 };
564
565 // DB8500_REGULATOR_VMODEM
566 db8500_vmodem_reg: db8500_vmodem {
567 };
568
569 // DB8500_REGULATOR_VPLL
570 db8500_vpll_reg: db8500_vpll {
571 };
572
573 // DB8500_REGULATOR_VSMPS1
574 db8500_vsmps1_reg: db8500_vsmps1 {
575 };
576
577 // DB8500_REGULATOR_VSMPS2
578 db8500_vsmps2_reg: db8500_vsmps2 {
579 };
580
581 // DB8500_REGULATOR_VSMPS3
582 db8500_vsmps3_reg: db8500_vsmps3 {
583 };
584
585 // DB8500_REGULATOR_VRF1
586 db8500_vrf1_reg: db8500_vrf1 {
587 };
588
589 // DB8500_REGULATOR_SWITCH_SVAMMDSP
590 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
591 };
592
593 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
594 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
595 };
596
597 // DB8500_REGULATOR_SWITCH_SVAPIPE
598 db8500_sva_pipe_reg: db8500_sva_pipe {
599 };
600
601 // DB8500_REGULATOR_SWITCH_SIAMMDSP
602 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
603 };
604
605 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
606 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
607 };
608
609 // DB8500_REGULATOR_SWITCH_SIAPIPE
610 db8500_sia_pipe_reg: db8500_sia_pipe {
611 };
612
613 // DB8500_REGULATOR_SWITCH_SGA
614 db8500_sga_reg: db8500_sga {
615 vin-supply = <&db8500_vape_reg>;
616 };
617
618 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
619 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
620 vin-supply = <&db8500_vape_reg>;
621 };
622
623 // DB8500_REGULATOR_SWITCH_ESRAM12
624 db8500_esram12_reg: db8500_esram12 {
625 };
626
627 // DB8500_REGULATOR_SWITCH_ESRAM12RET
628 db8500_esram12_ret_reg: db8500_esram12_ret {
629 };
630
631 // DB8500_REGULATOR_SWITCH_ESRAM34
632 db8500_esram34_reg: db8500_esram34 {
633 };
634
635 // DB8500_REGULATOR_SWITCH_ESRAM34RET
636 db8500_esram34_ret_reg: db8500_esram34_ret {
637 };
638 };
639 };
640
641 i2c@80004000 {
642 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
643 reg = <0x80004000 0x1000>;
644 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
645
646 #address-cells = <1>;
647 #size-cells = <0>;
648 v-i2c-supply = <&db8500_vape_reg>;
649
650 clock-frequency = <400000>;
651 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
652 clock-names = "i2cclk", "apb_pclk";
653 power-domains = <&pm_domains DOMAIN_VAPE>;
654 };
655
656 i2c@80122000 {
657 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
658 reg = <0x80122000 0x1000>;
659 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
660
661 #address-cells = <1>;
662 #size-cells = <0>;
663 v-i2c-supply = <&db8500_vape_reg>;
664
665 clock-frequency = <400000>;
666
667 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
668 clock-names = "i2cclk", "apb_pclk";
669 power-domains = <&pm_domains DOMAIN_VAPE>;
670 };
671
672 i2c@80128000 {
673 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
674 reg = <0x80128000 0x1000>;
675 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
676
677 #address-cells = <1>;
678 #size-cells = <0>;
679 v-i2c-supply = <&db8500_vape_reg>;
680
681 clock-frequency = <400000>;
682
683 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
684 clock-names = "i2cclk", "apb_pclk";
685 power-domains = <&pm_domains DOMAIN_VAPE>;
686 };
687
688 i2c@80110000 {
689 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
690 reg = <0x80110000 0x1000>;
691 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
692
693 #address-cells = <1>;
694 #size-cells = <0>;
695 v-i2c-supply = <&db8500_vape_reg>;
696
697 clock-frequency = <400000>;
698
699 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
700 clock-names = "i2cclk", "apb_pclk";
701 power-domains = <&pm_domains DOMAIN_VAPE>;
702 };
703
704 i2c@8012a000 {
705 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
706 reg = <0x8012a000 0x1000>;
707 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
708
709 #address-cells = <1>;
710 #size-cells = <0>;
711 v-i2c-supply = <&db8500_vape_reg>;
712
713 clock-frequency = <400000>;
714
715 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
716 clock-names = "i2cclk", "apb_pclk";
717 power-domains = <&pm_domains DOMAIN_VAPE>;
718 };
719
720 spi@80002000 {
721 compatible = "arm,pl022", "arm,primecell";
722 reg = <0x80002000 0x1000>;
723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
724 #address-cells = <1>;
725 #size-cells = <0>;
726 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
727 clock-names = "SSPCLK", "apb_pclk";
728 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
729 <&dma 8 0 0x0>; /* Logical - MemToDev */
730 dma-names = "rx", "tx";
731 power-domains = <&pm_domains DOMAIN_VAPE>;
732 };
733
734 spi@80003000 {
735 compatible = "arm,pl022", "arm,primecell";
736 reg = <0x80003000 0x1000>;
737 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
738 #address-cells = <1>;
739 #size-cells = <0>;
740 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
741 clock-names = "SSPCLK", "apb_pclk";
742 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
743 <&dma 9 0 0x0>; /* Logical - MemToDev */
744 dma-names = "rx", "tx";
745 power-domains = <&pm_domains DOMAIN_VAPE>;
746 };
747
748 spi@8011a000 {
749 compatible = "arm,pl022", "arm,primecell";
750 reg = <0x8011a000 0x1000>;
751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 /* Same clock wired to kernel and pclk */
755 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
756 clock-names = "SSPCLK", "apb_pclk";
757 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
758 <&dma 0 0 0x0>; /* Logical - MemToDev */
759 dma-names = "rx", "tx";
760 power-domains = <&pm_domains DOMAIN_VAPE>;
761 };
762
763 spi@80112000 {
764 compatible = "arm,pl022", "arm,primecell";
765 reg = <0x80112000 0x1000>;
766 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
768 #size-cells = <0>;
769 /* Same clock wired to kernel and pclk */
770 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
771 clock-names = "SSPCLK", "apb_pclk";
772 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
773 <&dma 35 0 0x0>; /* Logical - MemToDev */
774 dma-names = "rx", "tx";
775 power-domains = <&pm_domains DOMAIN_VAPE>;
776 };
777
778 spi@80111000 {
779 compatible = "arm,pl022", "arm,primecell";
780 reg = <0x80111000 0x1000>;
781 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
782 #address-cells = <1>;
783 #size-cells = <0>;
784 /* Same clock wired to kernel and pclk */
785 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
786 clock-names = "SSPCLK", "apb_pclk";
787 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
788 <&dma 33 0 0x0>; /* Logical - MemToDev */
789 dma-names = "rx", "tx";
790 power-domains = <&pm_domains DOMAIN_VAPE>;
791 };
792
793 spi@80129000 {
794 compatible = "arm,pl022", "arm,primecell";
795 reg = <0x80129000 0x1000>;
796 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
797 #address-cells = <1>;
798 #size-cells = <0>;
799 /* Same clock wired to kernel and pclk */
800 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
801 clock-names = "SSPCLK", "apb_pclk";
802 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
803 <&dma 40 0 0x0>; /* Logical - MemToDev */
804 dma-names = "rx", "tx";
805 power-domains = <&pm_domains DOMAIN_VAPE>;
806 };
807
808 ux500_serial0: uart@80120000 {
809 compatible = "arm,pl011", "arm,primecell";
810 reg = <0x80120000 0x1000>;
811 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
812
813 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
814 <&dma 13 0 0x0>; /* Logical - MemToDev */
815 dma-names = "rx", "tx";
816
817 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
818 clock-names = "uart", "apb_pclk";
819
820 status = "disabled";
821 };
822
823 ux500_serial1: uart@80121000 {
824 compatible = "arm,pl011", "arm,primecell";
825 reg = <0x80121000 0x1000>;
826 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
827
828 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
829 <&dma 12 0 0x0>; /* Logical - MemToDev */
830 dma-names = "rx", "tx";
831
832 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
833 clock-names = "uart", "apb_pclk";
834
835 status = "disabled";
836 };
837
838 ux500_serial2: uart@80007000 {
839 compatible = "arm,pl011", "arm,primecell";
840 reg = <0x80007000 0x1000>;
841 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
842
843 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
844 <&dma 11 0 0x0>; /* Logical - MemToDev */
845 dma-names = "rx", "tx";
846
847 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
848 clock-names = "uart", "apb_pclk";
849
850 status = "disabled";
851 };
852
853 sdi0_per1@80126000 {
854 compatible = "arm,pl18x", "arm,primecell";
855 reg = <0x80126000 0x1000>;
856 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
857
858 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
859 <&dma 29 0 0x0>; /* Logical - MemToDev */
860 dma-names = "rx", "tx";
861
862 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
863 clock-names = "sdi", "apb_pclk";
864 power-domains = <&pm_domains DOMAIN_VAPE>;
865
866 status = "disabled";
867 };
868
869 sdi1_per2@80118000 {
870 compatible = "arm,pl18x", "arm,primecell";
871 reg = <0x80118000 0x1000>;
872 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
873
874 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
875 <&dma 32 0 0x0>; /* Logical - MemToDev */
876 dma-names = "rx", "tx";
877
878 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
879 clock-names = "sdi", "apb_pclk";
880 power-domains = <&pm_domains DOMAIN_VAPE>;
881
882 status = "disabled";
883 };
884
885 sdi2_per3@80005000 {
886 compatible = "arm,pl18x", "arm,primecell";
887 reg = <0x80005000 0x1000>;
888 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
889
890 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
891 <&dma 28 0 0x0>; /* Logical - MemToDev */
892 dma-names = "rx", "tx";
893
894 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
895 clock-names = "sdi", "apb_pclk";
896 power-domains = <&pm_domains DOMAIN_VAPE>;
897
898 status = "disabled";
899 };
900
901 sdi3_per2@80119000 {
902 compatible = "arm,pl18x", "arm,primecell";
903 reg = <0x80119000 0x1000>;
904 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
905
906 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
907 <&dma 41 0 0x0>; /* Logical - MemToDev */
908 dma-names = "rx", "tx";
909
910 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
911 clock-names = "sdi", "apb_pclk";
912 power-domains = <&pm_domains DOMAIN_VAPE>;
913
914 status = "disabled";
915 };
916
917 sdi4_per2@80114000 {
918 compatible = "arm,pl18x", "arm,primecell";
919 reg = <0x80114000 0x1000>;
920 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
921
922 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
923 <&dma 42 0 0x0>; /* Logical - MemToDev */
924 dma-names = "rx", "tx";
925
926 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
927 clock-names = "sdi", "apb_pclk";
928 power-domains = <&pm_domains DOMAIN_VAPE>;
929
930 status = "disabled";
931 };
932
933 sdi5_per3@80008000 {
934 compatible = "arm,pl18x", "arm,primecell";
935 reg = <0x80008000 0x1000>;
936 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
937
938 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
939 <&dma 43 0 0x0>; /* Logical - MemToDev */
940 dma-names = "rx", "tx";
941
942 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
943 clock-names = "sdi", "apb_pclk";
944 power-domains = <&pm_domains DOMAIN_VAPE>;
945
946 status = "disabled";
947 };
948
949 sound {
950 compatible = "stericsson,snd-soc-mop500";
951 stericsson,cpu-dai = <&msp1 &msp3>;
952 };
953
954 msp0: msp@80123000 {
955 compatible = "stericsson,ux500-msp-i2s";
956 reg = <0x80123000 0x1000>;
957 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
958 v-ape-supply = <&db8500_vape_reg>;
959
960 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
961 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
962 dma-names = "rx", "tx";
963
964 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
965 clock-names = "msp", "apb_pclk";
966
967 status = "disabled";
968 };
969
970 msp1: msp@80124000 {
971 compatible = "stericsson,ux500-msp-i2s";
972 reg = <0x80124000 0x1000>;
973 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
974 v-ape-supply = <&db8500_vape_reg>;
975
976 /* This DMA channel only exist on DB8500 v1 */
977 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
978 dma-names = "tx";
979
980 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
981 clock-names = "msp", "apb_pclk";
982
983 status = "disabled";
984 };
985
986 // HDMI sound
987 msp2: msp@80117000 {
988 compatible = "stericsson,ux500-msp-i2s";
989 reg = <0x80117000 0x1000>;
990 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
991 v-ape-supply = <&db8500_vape_reg>;
992
993 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
994 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
995 HighPrio - Fixed */
996 dma-names = "rx", "tx";
997
998 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
999 clock-names = "msp", "apb_pclk";
1000
1001 status = "disabled";
1002 };
1003
1004 msp3: msp@80125000 {
1005 compatible = "stericsson,ux500-msp-i2s";
1006 reg = <0x80125000 0x1000>;
1007 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1008 v-ape-supply = <&db8500_vape_reg>;
1009
1010 /* This DMA channel only exist on DB8500 v2 */
1011 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1012 dma-names = "rx";
1013
1014 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1015 clock-names = "msp", "apb_pclk";
1016
1017 status = "disabled";
1018 };
1019
1020 external-bus@50000000 {
1021 compatible = "simple-bus";
1022 reg = <0x50000000 0x4000000>;
1023 #address-cells = <1>;
1024 #size-cells = <1>;
1025 ranges = <0 0x50000000 0x4000000>;
1026 status = "disabled";
1027 };
1028
1029 gpu@a0300000 {
1030 /*
1031 * This block is referred to as "Smart Graphics Adapter SGA500"
1032 * in documentation but is in practice a pretty straight-forward
1033 * MALI-400 GPU block.
1034 */
1035 compatible = "stericsson,db8500-mali", "arm,mali-400";
1036 reg = <0xa0300000 0x10000>;
1037 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1042 interrupt-names = "gp",
1043 "gpmmu",
1044 "pp0",
1045 "ppmmu0",
1046 "combined";
1047 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1048 clock-names = "bus", "core";
1049 mali-supply = <&db8500_sga_reg>;
1050 power-domains = <&pm_domains DOMAIN_VAPE>;
1051 };
1052
1053 mcde@a0350000 {
1054 compatible = "ste,mcde";
1055 reg = <0xa0350000 0x1000>;
1056 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1057 epod-supply = <&db8500_b2r2_mcde_reg>;
1058 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1059 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1060 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1061 clock-names = "mcde", "lcd", "hdmi";
1062 #address-cells = <1>;
1063 #size-cells = <1>;
1064 ranges;
1065 status = "disabled";
1066
1067 dsi0: dsi@a0351000 {
1068 compatible = "ste,mcde-dsi";
1069 reg = <0xa0351000 0x1000>;
1070 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1071 clock-names = "hs", "lp";
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074 };
1075 dsi1: dsi@a0352000 {
1076 compatible = "ste,mcde-dsi";
1077 reg = <0xa0352000 0x1000>;
1078 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1079 clock-names = "hs", "lp";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 };
1083 dsi2: dsi@a0353000 {
1084 compatible = "ste,mcde-dsi";
1085 reg = <0xa0353000 0x1000>;
1086 /* This DSI port only has the Low Power / Energy Save clock */
1087 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1088 clock-names = "lp";
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 };
1092 };
1093
1094 cryp@a03cb000 {
1095 compatible = "stericsson,ux500-cryp";
1096 reg = <0xa03cb000 0x1000>;
1097 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1098
1099 v-ape-supply = <&db8500_vape_reg>;
1100 clocks = <&prcc_pclk 6 1>;
1101 };
1102
1103 hash@a03c2000 {
1104 compatible = "stericsson,ux500-hash";
1105 reg = <0xa03c2000 0x1000>;
1106
1107 v-ape-supply = <&db8500_vape_reg>;
1108 clocks = <&prcc_pclk 6 2>;
1109 };
1110 };
1111};