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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2012 Altera <www.altera.com>
4 */
5
6#include <dt-bindings/reset/altr,rst-mgr.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11
12 aliases {
13 serial0 = &uart0;
14 serial1 = &uart1;
15 timer0 = &timer0;
16 timer1 = &timer1;
17 timer2 = &timer2;
18 timer3 = &timer3;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
25
26 cpu0: cpu@0 {
27 compatible = "arm,cortex-a9";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 };
32 cpu1: cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 };
38 };
39
40 pmu: pmu@ff111000 {
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
47 };
48
49 intc: interrupt-controller@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
55 };
56
57 soc {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 device_type = "soc";
62 interrupt-parent = <&intc>;
63 ranges;
64
65 amba {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 pdma: pdma@ffe01000 {
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
75 <0 105 4>,
76 <0 106 4>,
77 <0 107 4>,
78 <0 108 4>,
79 <0 109 4>,
80 <0 110 4>,
81 <0 111 4>;
82 #dma-cells = <1>;
83 clocks = <&l4_main_clk>;
84 clock-names = "apb_pclk";
85 resets = <&rst DMA_RESET>;
86 reset-names = "dma";
87 };
88 };
89
90 base_fpga_region {
91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0>;
93
94 #address-cells = <0x1>;
95 #size-cells = <0x1>;
96 };
97
98 can0: can@ffc00000 {
99 compatible = "bosch,d_can";
100 reg = <0xffc00000 0x1000>;
101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
102 clocks = <&can0_clk>;
103 resets = <&rst CAN0_RESET>;
104 status = "disabled";
105 };
106
107 can1: can@ffc01000 {
108 compatible = "bosch,d_can";
109 reg = <0xffc01000 0x1000>;
110 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
111 clocks = <&can1_clk>;
112 resets = <&rst CAN1_RESET>;
113 status = "disabled";
114 };
115
116 clkmgr@ffd04000 {
117 compatible = "altr,clk-mgr";
118 reg = <0xffd04000 0x1000>;
119
120 clocks {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 osc1: osc1 {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 };
128
129 osc2: osc2 {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 };
133
134 f2s_periph_ref_clk: f2s_periph_ref_clk {
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
137 };
138
139 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 };
143
144 main_pll: main_pll@40 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 #clock-cells = <0>;
148 compatible = "altr,socfpga-pll-clock";
149 clocks = <&osc1>;
150 reg = <0x40>;
151
152 mpuclk: mpuclk@48 {
153 #clock-cells = <0>;
154 compatible = "altr,socfpga-perip-clk";
155 clocks = <&main_pll>;
156 div-reg = <0xe0 0 9>;
157 reg = <0x48>;
158 };
159
160 mainclk: mainclk@4c {
161 #clock-cells = <0>;
162 compatible = "altr,socfpga-perip-clk";
163 clocks = <&main_pll>;
164 div-reg = <0xe4 0 9>;
165 reg = <0x4C>;
166 };
167
168 dbg_base_clk: dbg_base_clk@50 {
169 #clock-cells = <0>;
170 compatible = "altr,socfpga-perip-clk";
171 clocks = <&main_pll>, <&osc1>;
172 div-reg = <0xe8 0 9>;
173 reg = <0x50>;
174 };
175
176 main_qspi_clk: main_qspi_clk@54 {
177 #clock-cells = <0>;
178 compatible = "altr,socfpga-perip-clk";
179 clocks = <&main_pll>;
180 reg = <0x54>;
181 };
182
183 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
184 #clock-cells = <0>;
185 compatible = "altr,socfpga-perip-clk";
186 clocks = <&main_pll>;
187 reg = <0x58>;
188 };
189
190 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
191 #clock-cells = <0>;
192 compatible = "altr,socfpga-perip-clk";
193 clocks = <&main_pll>;
194 reg = <0x5C>;
195 };
196 };
197
198 periph_pll: periph_pll@80 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 #clock-cells = <0>;
202 compatible = "altr,socfpga-pll-clock";
203 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
204 reg = <0x80>;
205
206 emac0_clk: emac0_clk@88 {
207 #clock-cells = <0>;
208 compatible = "altr,socfpga-perip-clk";
209 clocks = <&periph_pll>;
210 reg = <0x88>;
211 };
212
213 emac1_clk: emac1_clk@8c {
214 #clock-cells = <0>;
215 compatible = "altr,socfpga-perip-clk";
216 clocks = <&periph_pll>;
217 reg = <0x8C>;
218 };
219
220 per_qspi_clk: per_qsi_clk@90 {
221 #clock-cells = <0>;
222 compatible = "altr,socfpga-perip-clk";
223 clocks = <&periph_pll>;
224 reg = <0x90>;
225 };
226
227 per_nand_mmc_clk: per_nand_mmc_clk@94 {
228 #clock-cells = <0>;
229 compatible = "altr,socfpga-perip-clk";
230 clocks = <&periph_pll>;
231 reg = <0x94>;
232 };
233
234 per_base_clk: per_base_clk@98 {
235 #clock-cells = <0>;
236 compatible = "altr,socfpga-perip-clk";
237 clocks = <&periph_pll>;
238 reg = <0x98>;
239 };
240
241 h2f_usr1_clk: h2f_usr1_clk@9c {
242 #clock-cells = <0>;
243 compatible = "altr,socfpga-perip-clk";
244 clocks = <&periph_pll>;
245 reg = <0x9C>;
246 };
247 };
248
249 sdram_pll: sdram_pll@c0 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-pll-clock";
254 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
255 reg = <0xC0>;
256
257 ddr_dqs_clk: ddr_dqs_clk@c8 {
258 #clock-cells = <0>;
259 compatible = "altr,socfpga-perip-clk";
260 clocks = <&sdram_pll>;
261 reg = <0xC8>;
262 };
263
264 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
265 #clock-cells = <0>;
266 compatible = "altr,socfpga-perip-clk";
267 clocks = <&sdram_pll>;
268 reg = <0xCC>;
269 };
270
271 ddr_dq_clk: ddr_dq_clk@d0 {
272 #clock-cells = <0>;
273 compatible = "altr,socfpga-perip-clk";
274 clocks = <&sdram_pll>;
275 reg = <0xD0>;
276 };
277
278 h2f_usr2_clk: h2f_usr2_clk@d4 {
279 #clock-cells = <0>;
280 compatible = "altr,socfpga-perip-clk";
281 clocks = <&sdram_pll>;
282 reg = <0xD4>;
283 };
284 };
285
286 mpu_periph_clk: mpu_periph_clk {
287 #clock-cells = <0>;
288 compatible = "altr,socfpga-perip-clk";
289 clocks = <&mpuclk>;
290 fixed-divider = <4>;
291 };
292
293 mpu_l2_ram_clk: mpu_l2_ram_clk {
294 #clock-cells = <0>;
295 compatible = "altr,socfpga-perip-clk";
296 clocks = <&mpuclk>;
297 fixed-divider = <2>;
298 };
299
300 l4_main_clk: l4_main_clk {
301 #clock-cells = <0>;
302 compatible = "altr,socfpga-gate-clk";
303 clocks = <&mainclk>;
304 clk-gate = <0x60 0>;
305 };
306
307 l3_main_clk: l3_main_clk {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-perip-clk";
310 clocks = <&mainclk>;
311 fixed-divider = <1>;
312 };
313
314 l3_mp_clk: l3_mp_clk {
315 #clock-cells = <0>;
316 compatible = "altr,socfpga-gate-clk";
317 clocks = <&mainclk>;
318 div-reg = <0x64 0 2>;
319 clk-gate = <0x60 1>;
320 };
321
322 l3_sp_clk: l3_sp_clk {
323 #clock-cells = <0>;
324 compatible = "altr,socfpga-gate-clk";
325 clocks = <&l3_mp_clk>;
326 div-reg = <0x64 2 2>;
327 };
328
329 l4_mp_clk: l4_mp_clk {
330 #clock-cells = <0>;
331 compatible = "altr,socfpga-gate-clk";
332 clocks = <&mainclk>, <&per_base_clk>;
333 div-reg = <0x64 4 3>;
334 clk-gate = <0x60 2>;
335 };
336
337 l4_sp_clk: l4_sp_clk {
338 #clock-cells = <0>;
339 compatible = "altr,socfpga-gate-clk";
340 clocks = <&mainclk>, <&per_base_clk>;
341 div-reg = <0x64 7 3>;
342 clk-gate = <0x60 3>;
343 };
344
345 dbg_at_clk: dbg_at_clk {
346 #clock-cells = <0>;
347 compatible = "altr,socfpga-gate-clk";
348 clocks = <&dbg_base_clk>;
349 div-reg = <0x68 0 2>;
350 clk-gate = <0x60 4>;
351 };
352
353 dbg_clk: dbg_clk {
354 #clock-cells = <0>;
355 compatible = "altr,socfpga-gate-clk";
356 clocks = <&dbg_at_clk>;
357 div-reg = <0x68 2 2>;
358 clk-gate = <0x60 5>;
359 };
360
361 dbg_trace_clk: dbg_trace_clk {
362 #clock-cells = <0>;
363 compatible = "altr,socfpga-gate-clk";
364 clocks = <&dbg_base_clk>;
365 div-reg = <0x6C 0 3>;
366 clk-gate = <0x60 6>;
367 };
368
369 dbg_timer_clk: dbg_timer_clk {
370 #clock-cells = <0>;
371 compatible = "altr,socfpga-gate-clk";
372 clocks = <&dbg_base_clk>;
373 clk-gate = <0x60 7>;
374 };
375
376 cfg_clk: cfg_clk {
377 #clock-cells = <0>;
378 compatible = "altr,socfpga-gate-clk";
379 clocks = <&cfg_h2f_usr0_clk>;
380 clk-gate = <0x60 8>;
381 };
382
383 h2f_user0_clk: h2f_user0_clk {
384 #clock-cells = <0>;
385 compatible = "altr,socfpga-gate-clk";
386 clocks = <&cfg_h2f_usr0_clk>;
387 clk-gate = <0x60 9>;
388 };
389
390 emac_0_clk: emac_0_clk {
391 #clock-cells = <0>;
392 compatible = "altr,socfpga-gate-clk";
393 clocks = <&emac0_clk>;
394 clk-gate = <0xa0 0>;
395 };
396
397 emac_1_clk: emac_1_clk {
398 #clock-cells = <0>;
399 compatible = "altr,socfpga-gate-clk";
400 clocks = <&emac1_clk>;
401 clk-gate = <0xa0 1>;
402 };
403
404 usb_mp_clk: usb_mp_clk {
405 #clock-cells = <0>;
406 compatible = "altr,socfpga-gate-clk";
407 clocks = <&per_base_clk>;
408 clk-gate = <0xa0 2>;
409 div-reg = <0xa4 0 3>;
410 };
411
412 spi_m_clk: spi_m_clk {
413 #clock-cells = <0>;
414 compatible = "altr,socfpga-gate-clk";
415 clocks = <&per_base_clk>;
416 clk-gate = <0xa0 3>;
417 div-reg = <0xa4 3 3>;
418 };
419
420 can0_clk: can0_clk {
421 #clock-cells = <0>;
422 compatible = "altr,socfpga-gate-clk";
423 clocks = <&per_base_clk>;
424 clk-gate = <0xa0 4>;
425 div-reg = <0xa4 6 3>;
426 };
427
428 can1_clk: can1_clk {
429 #clock-cells = <0>;
430 compatible = "altr,socfpga-gate-clk";
431 clocks = <&per_base_clk>;
432 clk-gate = <0xa0 5>;
433 div-reg = <0xa4 9 3>;
434 };
435
436 gpio_db_clk: gpio_db_clk {
437 #clock-cells = <0>;
438 compatible = "altr,socfpga-gate-clk";
439 clocks = <&per_base_clk>;
440 clk-gate = <0xa0 6>;
441 div-reg = <0xa8 0 24>;
442 };
443
444 h2f_user1_clk: h2f_user1_clk {
445 #clock-cells = <0>;
446 compatible = "altr,socfpga-gate-clk";
447 clocks = <&h2f_usr1_clk>;
448 clk-gate = <0xa0 7>;
449 };
450
451 sdmmc_clk: sdmmc_clk {
452 #clock-cells = <0>;
453 compatible = "altr,socfpga-gate-clk";
454 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
455 clk-gate = <0xa0 8>;
456 };
457
458 sdmmc_clk_divided: sdmmc_clk_divided {
459 #clock-cells = <0>;
460 compatible = "altr,socfpga-gate-clk";
461 clocks = <&sdmmc_clk>;
462 clk-gate = <0xa0 8>;
463 fixed-divider = <4>;
464 };
465
466 nand_x_clk: nand_x_clk {
467 #clock-cells = <0>;
468 compatible = "altr,socfpga-gate-clk";
469 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
470 clk-gate = <0xa0 9>;
471 };
472
473 nand_ecc_clk: nand_ecc_clk {
474 #clock-cells = <0>;
475 compatible = "altr,socfpga-gate-clk";
476 clocks = <&nand_x_clk>;
477 clk-gate = <0xa0 9>;
478 };
479
480 nand_clk: nand_clk {
481 #clock-cells = <0>;
482 compatible = "altr,socfpga-gate-clk";
483 clocks = <&nand_x_clk>;
484 clk-gate = <0xa0 10>;
485 fixed-divider = <4>;
486 };
487
488 qspi_clk: qspi_clk {
489 #clock-cells = <0>;
490 compatible = "altr,socfpga-gate-clk";
491 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
492 clk-gate = <0xa0 11>;
493 };
494
495 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
496 #clock-cells = <0>;
497 compatible = "altr,socfpga-gate-clk";
498 clocks = <&ddr_dqs_clk>;
499 clk-gate = <0xd8 0>;
500 };
501
502 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
503 #clock-cells = <0>;
504 compatible = "altr,socfpga-gate-clk";
505 clocks = <&ddr_2x_dqs_clk>;
506 clk-gate = <0xd8 1>;
507 };
508
509 ddr_dq_clk_gate: ddr_dq_clk_gate {
510 #clock-cells = <0>;
511 compatible = "altr,socfpga-gate-clk";
512 clocks = <&ddr_dq_clk>;
513 clk-gate = <0xd8 2>;
514 };
515
516 h2f_user2_clk: h2f_user2_clk {
517 #clock-cells = <0>;
518 compatible = "altr,socfpga-gate-clk";
519 clocks = <&h2f_usr2_clk>;
520 clk-gate = <0xd8 3>;
521 };
522
523 };
524 };
525
526 fpga_bridge0: fpga_bridge@ff400000 {
527 compatible = "altr,socfpga-lwhps2fpga-bridge";
528 reg = <0xff400000 0x100000>;
529 resets = <&rst LWHPS2FPGA_RESET>;
530 clocks = <&l4_main_clk>;
531 status = "disabled";
532 };
533
534 fpga_bridge1: fpga_bridge@ff500000 {
535 compatible = "altr,socfpga-hps2fpga-bridge";
536 reg = <0xff500000 0x10000>;
537 resets = <&rst HPS2FPGA_RESET>;
538 clocks = <&l4_main_clk>;
539 status = "disabled";
540 };
541
542 fpga_bridge2: fpga-bridge@ff600000 {
543 compatible = "altr,socfpga-fpga2hps-bridge";
544 reg = <0xff600000 0x100000>;
545 resets = <&rst FPGA2HPS_RESET>;
546 clocks = <&l4_main_clk>;
547 status = "disabled";
548 };
549
550 fpga_bridge3: fpga-bridge@ffc25080 {
551 compatible = "altr,socfpga-fpga2sdram-bridge";
552 reg = <0xffc25080 0x4>;
553 status = "disabled";
554 };
555
556 fpgamgr0: fpgamgr@ff706000 {
557 compatible = "altr,socfpga-fpga-mgr";
558 reg = <0xff706000 0x1000
559 0xffb90000 0x4>;
560 interrupts = <0 175 4>;
561 };
562
563 socfpga_axi_setup: stmmac-axi-config {
564 snps,wr_osr_lmt = <0xf>;
565 snps,rd_osr_lmt = <0xf>;
566 snps,blen = <0 0 0 0 16 0 0>;
567 };
568
569 gmac0: ethernet@ff700000 {
570 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
571 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
572 reg = <0xff700000 0x2000>;
573 interrupts = <0 115 4>;
574 interrupt-names = "macirq";
575 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
576 clocks = <&emac_0_clk>;
577 clock-names = "stmmaceth";
578 resets = <&rst EMAC0_RESET>;
579 reset-names = "stmmaceth";
580 snps,multicast-filter-bins = <256>;
581 snps,perfect-filter-entries = <128>;
582 tx-fifo-depth = <4096>;
583 rx-fifo-depth = <4096>;
584 snps,axi-config = <&socfpga_axi_setup>;
585 status = "disabled";
586 };
587
588 gmac1: ethernet@ff702000 {
589 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
590 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
591 reg = <0xff702000 0x2000>;
592 interrupts = <0 120 4>;
593 interrupt-names = "macirq";
594 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
595 clocks = <&emac_1_clk>;
596 clock-names = "stmmaceth";
597 resets = <&rst EMAC1_RESET>;
598 reset-names = "stmmaceth";
599 snps,multicast-filter-bins = <256>;
600 snps,perfect-filter-entries = <128>;
601 tx-fifo-depth = <4096>;
602 rx-fifo-depth = <4096>;
603 snps,axi-config = <&socfpga_axi_setup>;
604 status = "disabled";
605 };
606
607 gpio0: gpio@ff708000 {
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "snps,dw-apb-gpio";
611 reg = <0xff708000 0x1000>;
612 clocks = <&l4_mp_clk>;
613 resets = <&rst GPIO0_RESET>;
614 status = "disabled";
615
616 porta: gpio-controller@0 {
617 compatible = "snps,dw-apb-gpio-port";
618 gpio-controller;
619 #gpio-cells = <2>;
620 snps,nr-gpios = <29>;
621 reg = <0>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 interrupts = <0 164 4>;
625 };
626 };
627
628 gpio1: gpio@ff709000 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "snps,dw-apb-gpio";
632 reg = <0xff709000 0x1000>;
633 clocks = <&l4_mp_clk>;
634 resets = <&rst GPIO1_RESET>;
635 status = "disabled";
636
637 portb: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <29>;
642 reg = <0>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 interrupts = <0 165 4>;
646 };
647 };
648
649 gpio2: gpio@ff70a000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,dw-apb-gpio";
653 reg = <0xff70a000 0x1000>;
654 clocks = <&l4_mp_clk>;
655 resets = <&rst GPIO2_RESET>;
656 status = "disabled";
657
658 portc: gpio-controller@0 {
659 compatible = "snps,dw-apb-gpio-port";
660 gpio-controller;
661 #gpio-cells = <2>;
662 snps,nr-gpios = <27>;
663 reg = <0>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
666 interrupts = <0 166 4>;
667 };
668 };
669
670 i2c0: i2c@ffc04000 {
671 #address-cells = <1>;
672 #size-cells = <0>;
673 compatible = "snps,designware-i2c";
674 reg = <0xffc04000 0x1000>;
675 resets = <&rst I2C0_RESET>;
676 clocks = <&l4_sp_clk>;
677 interrupts = <0 158 0x4>;
678 status = "disabled";
679 };
680
681 i2c1: i2c@ffc05000 {
682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "snps,designware-i2c";
685 reg = <0xffc05000 0x1000>;
686 resets = <&rst I2C1_RESET>;
687 clocks = <&l4_sp_clk>;
688 interrupts = <0 159 0x4>;
689 status = "disabled";
690 };
691
692 i2c2: i2c@ffc06000 {
693 #address-cells = <1>;
694 #size-cells = <0>;
695 compatible = "snps,designware-i2c";
696 reg = <0xffc06000 0x1000>;
697 resets = <&rst I2C2_RESET>;
698 clocks = <&l4_sp_clk>;
699 interrupts = <0 160 0x4>;
700 status = "disabled";
701 };
702
703 i2c3: i2c@ffc07000 {
704 #address-cells = <1>;
705 #size-cells = <0>;
706 compatible = "snps,designware-i2c";
707 reg = <0xffc07000 0x1000>;
708 resets = <&rst I2C3_RESET>;
709 clocks = <&l4_sp_clk>;
710 interrupts = <0 161 0x4>;
711 status = "disabled";
712 };
713
714 eccmgr: eccmgr {
715 compatible = "altr,socfpga-ecc-manager";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges;
719
720 l2-ecc@ffd08140 {
721 compatible = "altr,socfpga-l2-ecc";
722 reg = <0xffd08140 0x4>;
723 interrupts = <0 36 1>, <0 37 1>;
724 };
725
726 ocram-ecc@ffd08144 {
727 compatible = "altr,socfpga-ocram-ecc";
728 reg = <0xffd08144 0x4>;
729 iram = <&ocram>;
730 interrupts = <0 178 1>, <0 179 1>;
731 };
732 };
733
734 L2: cache-controller@fffef000 {
735 compatible = "arm,pl310-cache";
736 reg = <0xfffef000 0x1000>;
737 interrupts = <0 38 0x04>;
738 cache-unified;
739 cache-level = <2>;
740 arm,tag-latency = <1 1 1>;
741 arm,data-latency = <2 1 1>;
742 prefetch-data = <1>;
743 prefetch-instr = <1>;
744 arm,shared-override;
745 arm,double-linefill = <1>;
746 arm,double-linefill-incr = <0>;
747 arm,double-linefill-wrap = <1>;
748 arm,prefetch-drop = <0>;
749 arm,prefetch-offset = <7>;
750 };
751
752 l3regs@0xff800000 {
753 compatible = "altr,l3regs", "syscon";
754 reg = <0xff800000 0x1000>;
755 };
756
757 mmc: mmc@ff704000 {
758 compatible = "altr,socfpga-dw-mshc";
759 reg = <0xff704000 0x1000>;
760 interrupts = <0 139 4>;
761 fifo-depth = <0x400>;
762 #address-cells = <1>;
763 #size-cells = <0>;
764 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
765 clock-names = "biu", "ciu";
766 resets = <&rst SDMMC_RESET>;
767 altr,sysmgr-syscon = <&sysmgr 0x108 3>;
768 status = "disabled";
769 };
770
771 nand0: nand@ff900000 {
772 #address-cells = <0x1>;
773 #size-cells = <0x0>;
774 compatible = "altr,socfpga-denali-nand";
775 reg = <0xff900000 0x100000>,
776 <0xffb80000 0x10000>;
777 reg-names = "nand_data", "denali_reg";
778 interrupts = <0x0 0x90 0x4>;
779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
780 clock-names = "nand", "nand_x", "ecc";
781 resets = <&rst NAND_RESET>;
782 status = "disabled";
783 };
784
785 ocram: sram@ffff0000 {
786 compatible = "mmio-sram";
787 reg = <0xffff0000 0x10000>;
788 };
789
790 qspi: spi@ff705000 {
791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
792 #address-cells = <1>;
793 #size-cells = <0>;
794 reg = <0xff705000 0x1000>,
795 <0xffa00000 0x1000>;
796 interrupts = <0 151 4>;
797 cdns,fifo-depth = <128>;
798 cdns,fifo-width = <4>;
799 cdns,trigger-address = <0x00000000>;
800 clocks = <&qspi_clk>;
801 resets = <&rst QSPI_RESET>;
802 status = "disabled";
803 };
804
805 rst: rstmgr@ffd05000 {
806 #reset-cells = <1>;
807 compatible = "altr,rst-mgr";
808 reg = <0xffd05000 0x1000>;
809 altr,modrst-offset = <0x10>;
810 };
811
812 scu: snoop-control-unit@fffec000 {
813 compatible = "arm,cortex-a9-scu";
814 reg = <0xfffec000 0x100>;
815 };
816
817 sdr: sdr@ffc25000 {
818 compatible = "altr,sdr-ctl", "syscon";
819 reg = <0xffc25000 0x1000>;
820 resets = <&rst SDR_RESET>;
821 };
822
823 sdramedac {
824 compatible = "altr,sdram-edac";
825 altr,sdr-syscon = <&sdr>;
826 interrupts = <0 39 4>;
827 };
828
829 spi0: spi@fff00000 {
830 compatible = "snps,dw-apb-ssi";
831 #address-cells = <1>;
832 #size-cells = <0>;
833 reg = <0xfff00000 0x1000>;
834 interrupts = <0 154 4>;
835 num-cs = <4>;
836 clocks = <&spi_m_clk>;
837 resets = <&rst SPIM0_RESET>;
838 reset-names = "spi";
839 status = "disabled";
840 };
841
842 spi1: spi@fff01000 {
843 compatible = "snps,dw-apb-ssi";
844 #address-cells = <1>;
845 #size-cells = <0>;
846 reg = <0xfff01000 0x1000>;
847 interrupts = <0 155 4>;
848 num-cs = <4>;
849 clocks = <&spi_m_clk>;
850 resets = <&rst SPIM1_RESET>;
851 reset-names = "spi";
852 status = "disabled";
853 };
854
855 sysmgr: sysmgr@ffd08000 {
856 compatible = "altr,sys-mgr", "syscon";
857 reg = <0xffd08000 0x4000>;
858 };
859
860 /* Local timer */
861 timer@fffec600 {
862 compatible = "arm,cortex-a9-twd-timer";
863 reg = <0xfffec600 0x100>;
864 interrupts = <1 13 0xf01>;
865 clocks = <&mpu_periph_clk>;
866 };
867
868 timer0: timer0@ffc08000 {
869 compatible = "snps,dw-apb-timer";
870 interrupts = <0 167 4>;
871 reg = <0xffc08000 0x1000>;
872 clocks = <&l4_sp_clk>;
873 clock-names = "timer";
874 resets = <&rst SPTIMER0_RESET>;
875 reset-names = "timer";
876 };
877
878 timer1: timer1@ffc09000 {
879 compatible = "snps,dw-apb-timer";
880 interrupts = <0 168 4>;
881 reg = <0xffc09000 0x1000>;
882 clocks = <&l4_sp_clk>;
883 clock-names = "timer";
884 resets = <&rst SPTIMER1_RESET>;
885 reset-names = "timer";
886 };
887
888 timer2: timer2@ffd00000 {
889 compatible = "snps,dw-apb-timer";
890 interrupts = <0 169 4>;
891 reg = <0xffd00000 0x1000>;
892 clocks = <&osc1>;
893 clock-names = "timer";
894 resets = <&rst OSC1TIMER0_RESET>;
895 reset-names = "timer";
896 };
897
898 timer3: timer3@ffd01000 {
899 compatible = "snps,dw-apb-timer";
900 interrupts = <0 170 4>;
901 reg = <0xffd01000 0x1000>;
902 clocks = <&osc1>;
903 clock-names = "timer";
904 resets = <&rst OSC1TIMER1_RESET>;
905 reset-names = "timer";
906 };
907
908 uart0: serial0@ffc02000 {
909 compatible = "snps,dw-apb-uart";
910 reg = <0xffc02000 0x1000>;
911 interrupts = <0 162 4>;
912 reg-shift = <2>;
913 reg-io-width = <4>;
914 clocks = <&l4_sp_clk>;
915 dmas = <&pdma 28>,
916 <&pdma 29>;
917 dma-names = "tx", "rx";
918 resets = <&rst UART0_RESET>;
919 };
920
921 uart1: serial1@ffc03000 {
922 compatible = "snps,dw-apb-uart";
923 reg = <0xffc03000 0x1000>;
924 interrupts = <0 163 4>;
925 reg-shift = <2>;
926 reg-io-width = <4>;
927 clocks = <&l4_sp_clk>;
928 dmas = <&pdma 30>,
929 <&pdma 31>;
930 dma-names = "tx", "rx";
931 resets = <&rst UART1_RESET>;
932 };
933
934 usbphy0: usbphy {
935 #phy-cells = <0>;
936 compatible = "usb-nop-xceiv";
937 status = "okay";
938 };
939
940 usb0: usb@ffb00000 {
941 compatible = "snps,dwc2";
942 reg = <0xffb00000 0xffff>;
943 interrupts = <0 125 4>;
944 clocks = <&usb_mp_clk>;
945 clock-names = "otg";
946 resets = <&rst USB0_RESET>;
947 reset-names = "dwc2";
948 phys = <&usbphy0>;
949 phy-names = "usb2-phy";
950 status = "disabled";
951 };
952
953 usb1: usb@ffb40000 {
954 compatible = "snps,dwc2";
955 reg = <0xffb40000 0xffff>;
956 interrupts = <0 128 4>;
957 clocks = <&usb_mp_clk>;
958 clock-names = "otg";
959 resets = <&rst USB1_RESET>;
960 reset-names = "dwc2";
961 phys = <&usbphy0>;
962 phy-names = "usb2-phy";
963 status = "disabled";
964 };
965
966 watchdog0: watchdog@ffd02000 {
967 compatible = "snps,dw-wdt";
968 reg = <0xffd02000 0x1000>;
969 interrupts = <0 171 4>;
970 clocks = <&osc1>;
971 resets = <&rst L4WD0_RESET>;
972 status = "disabled";
973 };
974
975 watchdog1: watchdog@ffd03000 {
976 compatible = "snps,dw-wdt";
977 reg = <0xffd03000 0x1000>;
978 interrupts = <0 172 4>;
979 clocks = <&osc1>;
980 resets = <&rst L4WD1_RESET>;
981 status = "disabled";
982 };
983 };
984};
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2012 Altera <www.altera.com>
4 */
5
6#include <dt-bindings/reset/altr,rst-mgr.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11
12 aliases {
13 serial0 = &uart0;
14 serial1 = &uart1;
15 timer0 = &timer0;
16 timer1 = &timer1;
17 timer2 = &timer2;
18 timer3 = &timer3;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
25
26 cpu0: cpu@0 {
27 compatible = "arm,cortex-a9";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 };
32 cpu1: cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 next-level-cache = <&L2>;
37 };
38 };
39
40 pmu: pmu@ff111000 {
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
47 };
48
49 intc: intc@fffed000 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 interrupt-controller;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
55 };
56
57 soc {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 device_type = "soc";
62 interrupt-parent = <&intc>;
63 ranges;
64
65 amba {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 ranges;
70
71 pdma: pdma@ffe01000 {
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
75 <0 105 4>,
76 <0 106 4>,
77 <0 107 4>,
78 <0 108 4>,
79 <0 109 4>,
80 <0 110 4>,
81 <0 111 4>;
82 #dma-cells = <1>;
83 #dma-channels = <8>;
84 #dma-requests = <32>;
85 clocks = <&l4_main_clk>;
86 clock-names = "apb_pclk";
87 resets = <&rst DMA_RESET>;
88 reset-names = "dma";
89 };
90 };
91
92 base_fpga_region {
93 compatible = "fpga-region";
94 fpga-mgr = <&fpgamgr0>;
95
96 #address-cells = <0x1>;
97 #size-cells = <0x1>;
98 };
99
100 can0: can@ffc00000 {
101 compatible = "bosch,d_can";
102 reg = <0xffc00000 0x1000>;
103 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
104 clocks = <&can0_clk>;
105 resets = <&rst CAN0_RESET>;
106 status = "disabled";
107 };
108
109 can1: can@ffc01000 {
110 compatible = "bosch,d_can";
111 reg = <0xffc01000 0x1000>;
112 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
113 clocks = <&can1_clk>;
114 resets = <&rst CAN1_RESET>;
115 status = "disabled";
116 };
117
118 clkmgr@ffd04000 {
119 compatible = "altr,clk-mgr";
120 reg = <0xffd04000 0x1000>;
121
122 clocks {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 osc1: osc1 {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 };
130
131 osc2: osc2 {
132 #clock-cells = <0>;
133 compatible = "fixed-clock";
134 };
135
136 f2s_periph_ref_clk: f2s_periph_ref_clk {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 };
140
141 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 };
145
146 main_pll: main_pll@40 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 #clock-cells = <0>;
150 compatible = "altr,socfpga-pll-clock";
151 clocks = <&osc1>;
152 reg = <0x40>;
153
154 mpuclk: mpuclk@48 {
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
158 div-reg = <0xe0 0 9>;
159 reg = <0x48>;
160 };
161
162 mainclk: mainclk@4c {
163 #clock-cells = <0>;
164 compatible = "altr,socfpga-perip-clk";
165 clocks = <&main_pll>;
166 div-reg = <0xe4 0 9>;
167 reg = <0x4C>;
168 };
169
170 dbg_base_clk: dbg_base_clk@50 {
171 #clock-cells = <0>;
172 compatible = "altr,socfpga-perip-clk";
173 clocks = <&main_pll>, <&osc1>;
174 div-reg = <0xe8 0 9>;
175 reg = <0x50>;
176 };
177
178 main_qspi_clk: main_qspi_clk@54 {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x54>;
183 };
184
185 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x58>;
190 };
191
192 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-perip-clk";
195 clocks = <&main_pll>;
196 reg = <0x5C>;
197 };
198 };
199
200 periph_pll: periph_pll@80 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-pll-clock";
205 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
206 reg = <0x80>;
207
208 emac0_clk: emac0_clk@88 {
209 #clock-cells = <0>;
210 compatible = "altr,socfpga-perip-clk";
211 clocks = <&periph_pll>;
212 reg = <0x88>;
213 };
214
215 emac1_clk: emac1_clk@8c {
216 #clock-cells = <0>;
217 compatible = "altr,socfpga-perip-clk";
218 clocks = <&periph_pll>;
219 reg = <0x8C>;
220 };
221
222 per_qspi_clk: per_qsi_clk@90 {
223 #clock-cells = <0>;
224 compatible = "altr,socfpga-perip-clk";
225 clocks = <&periph_pll>;
226 reg = <0x90>;
227 };
228
229 per_nand_mmc_clk: per_nand_mmc_clk@94 {
230 #clock-cells = <0>;
231 compatible = "altr,socfpga-perip-clk";
232 clocks = <&periph_pll>;
233 reg = <0x94>;
234 };
235
236 per_base_clk: per_base_clk@98 {
237 #clock-cells = <0>;
238 compatible = "altr,socfpga-perip-clk";
239 clocks = <&periph_pll>;
240 reg = <0x98>;
241 };
242
243 h2f_usr1_clk: h2f_usr1_clk@9c {
244 #clock-cells = <0>;
245 compatible = "altr,socfpga-perip-clk";
246 clocks = <&periph_pll>;
247 reg = <0x9C>;
248 };
249 };
250
251 sdram_pll: sdram_pll@c0 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-pll-clock";
256 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
257 reg = <0xC0>;
258
259 ddr_dqs_clk: ddr_dqs_clk@c8 {
260 #clock-cells = <0>;
261 compatible = "altr,socfpga-perip-clk";
262 clocks = <&sdram_pll>;
263 reg = <0xC8>;
264 };
265
266 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
267 #clock-cells = <0>;
268 compatible = "altr,socfpga-perip-clk";
269 clocks = <&sdram_pll>;
270 reg = <0xCC>;
271 };
272
273 ddr_dq_clk: ddr_dq_clk@d0 {
274 #clock-cells = <0>;
275 compatible = "altr,socfpga-perip-clk";
276 clocks = <&sdram_pll>;
277 reg = <0xD0>;
278 };
279
280 h2f_usr2_clk: h2f_usr2_clk@d4 {
281 #clock-cells = <0>;
282 compatible = "altr,socfpga-perip-clk";
283 clocks = <&sdram_pll>;
284 reg = <0xD4>;
285 };
286 };
287
288 mpu_periph_clk: mpu_periph_clk {
289 #clock-cells = <0>;
290 compatible = "altr,socfpga-perip-clk";
291 clocks = <&mpuclk>;
292 fixed-divider = <4>;
293 };
294
295 mpu_l2_ram_clk: mpu_l2_ram_clk {
296 #clock-cells = <0>;
297 compatible = "altr,socfpga-perip-clk";
298 clocks = <&mpuclk>;
299 fixed-divider = <2>;
300 };
301
302 l4_main_clk: l4_main_clk {
303 #clock-cells = <0>;
304 compatible = "altr,socfpga-gate-clk";
305 clocks = <&mainclk>;
306 clk-gate = <0x60 0>;
307 };
308
309 l3_main_clk: l3_main_clk {
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-perip-clk";
312 clocks = <&mainclk>;
313 fixed-divider = <1>;
314 };
315
316 l3_mp_clk: l3_mp_clk {
317 #clock-cells = <0>;
318 compatible = "altr,socfpga-gate-clk";
319 clocks = <&mainclk>;
320 div-reg = <0x64 0 2>;
321 clk-gate = <0x60 1>;
322 };
323
324 l3_sp_clk: l3_sp_clk {
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-gate-clk";
327 clocks = <&l3_mp_clk>;
328 div-reg = <0x64 2 2>;
329 };
330
331 l4_mp_clk: l4_mp_clk {
332 #clock-cells = <0>;
333 compatible = "altr,socfpga-gate-clk";
334 clocks = <&mainclk>, <&per_base_clk>;
335 div-reg = <0x64 4 3>;
336 clk-gate = <0x60 2>;
337 };
338
339 l4_sp_clk: l4_sp_clk {
340 #clock-cells = <0>;
341 compatible = "altr,socfpga-gate-clk";
342 clocks = <&mainclk>, <&per_base_clk>;
343 div-reg = <0x64 7 3>;
344 clk-gate = <0x60 3>;
345 };
346
347 dbg_at_clk: dbg_at_clk {
348 #clock-cells = <0>;
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&dbg_base_clk>;
351 div-reg = <0x68 0 2>;
352 clk-gate = <0x60 4>;
353 };
354
355 dbg_clk: dbg_clk {
356 #clock-cells = <0>;
357 compatible = "altr,socfpga-gate-clk";
358 clocks = <&dbg_at_clk>;
359 div-reg = <0x68 2 2>;
360 clk-gate = <0x60 5>;
361 };
362
363 dbg_trace_clk: dbg_trace_clk {
364 #clock-cells = <0>;
365 compatible = "altr,socfpga-gate-clk";
366 clocks = <&dbg_base_clk>;
367 div-reg = <0x6C 0 3>;
368 clk-gate = <0x60 6>;
369 };
370
371 dbg_timer_clk: dbg_timer_clk {
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-gate-clk";
374 clocks = <&dbg_base_clk>;
375 clk-gate = <0x60 7>;
376 };
377
378 cfg_clk: cfg_clk {
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-gate-clk";
381 clocks = <&cfg_h2f_usr0_clk>;
382 clk-gate = <0x60 8>;
383 };
384
385 h2f_user0_clk: h2f_user0_clk {
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-gate-clk";
388 clocks = <&cfg_h2f_usr0_clk>;
389 clk-gate = <0x60 9>;
390 };
391
392 emac_0_clk: emac_0_clk {
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-gate-clk";
395 clocks = <&emac0_clk>;
396 clk-gate = <0xa0 0>;
397 };
398
399 emac_1_clk: emac_1_clk {
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-gate-clk";
402 clocks = <&emac1_clk>;
403 clk-gate = <0xa0 1>;
404 };
405
406 usb_mp_clk: usb_mp_clk {
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-gate-clk";
409 clocks = <&per_base_clk>;
410 clk-gate = <0xa0 2>;
411 div-reg = <0xa4 0 3>;
412 };
413
414 spi_m_clk: spi_m_clk {
415 #clock-cells = <0>;
416 compatible = "altr,socfpga-gate-clk";
417 clocks = <&per_base_clk>;
418 clk-gate = <0xa0 3>;
419 div-reg = <0xa4 3 3>;
420 };
421
422 can0_clk: can0_clk {
423 #clock-cells = <0>;
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&per_base_clk>;
426 clk-gate = <0xa0 4>;
427 div-reg = <0xa4 6 3>;
428 };
429
430 can1_clk: can1_clk {
431 #clock-cells = <0>;
432 compatible = "altr,socfpga-gate-clk";
433 clocks = <&per_base_clk>;
434 clk-gate = <0xa0 5>;
435 div-reg = <0xa4 9 3>;
436 };
437
438 gpio_db_clk: gpio_db_clk {
439 #clock-cells = <0>;
440 compatible = "altr,socfpga-gate-clk";
441 clocks = <&per_base_clk>;
442 clk-gate = <0xa0 6>;
443 div-reg = <0xa8 0 24>;
444 };
445
446 h2f_user1_clk: h2f_user1_clk {
447 #clock-cells = <0>;
448 compatible = "altr,socfpga-gate-clk";
449 clocks = <&h2f_usr1_clk>;
450 clk-gate = <0xa0 7>;
451 };
452
453 sdmmc_clk: sdmmc_clk {
454 #clock-cells = <0>;
455 compatible = "altr,socfpga-gate-clk";
456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
457 clk-gate = <0xa0 8>;
458 clk-phase = <0 135>;
459 };
460
461 sdmmc_clk_divided: sdmmc_clk_divided {
462 #clock-cells = <0>;
463 compatible = "altr,socfpga-gate-clk";
464 clocks = <&sdmmc_clk>;
465 clk-gate = <0xa0 8>;
466 fixed-divider = <4>;
467 };
468
469 nand_x_clk: nand_x_clk {
470 #clock-cells = <0>;
471 compatible = "altr,socfpga-gate-clk";
472 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
473 clk-gate = <0xa0 9>;
474 };
475
476 nand_ecc_clk: nand_ecc_clk {
477 #clock-cells = <0>;
478 compatible = "altr,socfpga-gate-clk";
479 clocks = <&nand_x_clk>;
480 clk-gate = <0xa0 9>;
481 };
482
483 nand_clk: nand_clk {
484 #clock-cells = <0>;
485 compatible = "altr,socfpga-gate-clk";
486 clocks = <&nand_x_clk>;
487 clk-gate = <0xa0 10>;
488 fixed-divider = <4>;
489 };
490
491 qspi_clk: qspi_clk {
492 #clock-cells = <0>;
493 compatible = "altr,socfpga-gate-clk";
494 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
495 clk-gate = <0xa0 11>;
496 };
497
498 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
499 #clock-cells = <0>;
500 compatible = "altr,socfpga-gate-clk";
501 clocks = <&ddr_dqs_clk>;
502 clk-gate = <0xd8 0>;
503 };
504
505 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
506 #clock-cells = <0>;
507 compatible = "altr,socfpga-gate-clk";
508 clocks = <&ddr_2x_dqs_clk>;
509 clk-gate = <0xd8 1>;
510 };
511
512 ddr_dq_clk_gate: ddr_dq_clk_gate {
513 #clock-cells = <0>;
514 compatible = "altr,socfpga-gate-clk";
515 clocks = <&ddr_dq_clk>;
516 clk-gate = <0xd8 2>;
517 };
518
519 h2f_user2_clk: h2f_user2_clk {
520 #clock-cells = <0>;
521 compatible = "altr,socfpga-gate-clk";
522 clocks = <&h2f_usr2_clk>;
523 clk-gate = <0xd8 3>;
524 };
525
526 };
527 };
528
529 fpga_bridge0: fpga_bridge@ff400000 {
530 compatible = "altr,socfpga-lwhps2fpga-bridge";
531 reg = <0xff400000 0x100000>;
532 resets = <&rst LWHPS2FPGA_RESET>;
533 clocks = <&l4_main_clk>;
534 };
535
536 fpga_bridge1: fpga_bridge@ff500000 {
537 compatible = "altr,socfpga-hps2fpga-bridge";
538 reg = <0xff500000 0x10000>;
539 resets = <&rst HPS2FPGA_RESET>;
540 clocks = <&l4_main_clk>;
541 };
542
543 fpgamgr0: fpgamgr@ff706000 {
544 compatible = "altr,socfpga-fpga-mgr";
545 reg = <0xff706000 0x1000
546 0xffb90000 0x4>;
547 interrupts = <0 175 4>;
548 };
549
550 gmac0: ethernet@ff700000 {
551 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
552 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
553 reg = <0xff700000 0x2000>;
554 interrupts = <0 115 4>;
555 interrupt-names = "macirq";
556 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
557 clocks = <&emac_0_clk>;
558 clock-names = "stmmaceth";
559 resets = <&rst EMAC0_RESET>;
560 reset-names = "stmmaceth";
561 snps,multicast-filter-bins = <256>;
562 snps,perfect-filter-entries = <128>;
563 tx-fifo-depth = <4096>;
564 rx-fifo-depth = <4096>;
565 status = "disabled";
566 };
567
568 gmac1: ethernet@ff702000 {
569 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
570 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
571 reg = <0xff702000 0x2000>;
572 interrupts = <0 120 4>;
573 interrupt-names = "macirq";
574 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
575 clocks = <&emac_1_clk>;
576 clock-names = "stmmaceth";
577 resets = <&rst EMAC1_RESET>;
578 reset-names = "stmmaceth";
579 snps,multicast-filter-bins = <256>;
580 snps,perfect-filter-entries = <128>;
581 tx-fifo-depth = <4096>;
582 rx-fifo-depth = <4096>;
583 status = "disabled";
584 };
585
586 gpio0: gpio@ff708000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "snps,dw-apb-gpio";
590 reg = <0xff708000 0x1000>;
591 clocks = <&l4_mp_clk>;
592 resets = <&rst GPIO0_RESET>;
593 status = "disabled";
594
595 porta: gpio-controller@0 {
596 compatible = "snps,dw-apb-gpio-port";
597 gpio-controller;
598 #gpio-cells = <2>;
599 snps,nr-gpios = <29>;
600 reg = <0>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 interrupts = <0 164 4>;
604 };
605 };
606
607 gpio1: gpio@ff709000 {
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "snps,dw-apb-gpio";
611 reg = <0xff709000 0x1000>;
612 clocks = <&l4_mp_clk>;
613 resets = <&rst GPIO1_RESET>;
614 status = "disabled";
615
616 portb: gpio-controller@0 {
617 compatible = "snps,dw-apb-gpio-port";
618 gpio-controller;
619 #gpio-cells = <2>;
620 snps,nr-gpios = <29>;
621 reg = <0>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 interrupts = <0 165 4>;
625 };
626 };
627
628 gpio2: gpio@ff70a000 {
629 #address-cells = <1>;
630 #size-cells = <0>;
631 compatible = "snps,dw-apb-gpio";
632 reg = <0xff70a000 0x1000>;
633 clocks = <&l4_mp_clk>;
634 resets = <&rst GPIO2_RESET>;
635 status = "disabled";
636
637 portc: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <27>;
642 reg = <0>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 interrupts = <0 166 4>;
646 };
647 };
648
649 i2c0: i2c@ffc04000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,designware-i2c";
653 reg = <0xffc04000 0x1000>;
654 resets = <&rst I2C0_RESET>;
655 clocks = <&l4_sp_clk>;
656 interrupts = <0 158 0x4>;
657 status = "disabled";
658 };
659
660 i2c1: i2c@ffc05000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "snps,designware-i2c";
664 reg = <0xffc05000 0x1000>;
665 resets = <&rst I2C1_RESET>;
666 clocks = <&l4_sp_clk>;
667 interrupts = <0 159 0x4>;
668 status = "disabled";
669 };
670
671 i2c2: i2c@ffc06000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc06000 0x1000>;
676 resets = <&rst I2C2_RESET>;
677 clocks = <&l4_sp_clk>;
678 interrupts = <0 160 0x4>;
679 status = "disabled";
680 };
681
682 i2c3: i2c@ffc07000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "snps,designware-i2c";
686 reg = <0xffc07000 0x1000>;
687 resets = <&rst I2C3_RESET>;
688 clocks = <&l4_sp_clk>;
689 interrupts = <0 161 0x4>;
690 status = "disabled";
691 };
692
693 eccmgr: eccmgr {
694 compatible = "altr,socfpga-ecc-manager";
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges;
698
699 l2-ecc@ffd08140 {
700 compatible = "altr,socfpga-l2-ecc";
701 reg = <0xffd08140 0x4>;
702 interrupts = <0 36 1>, <0 37 1>;
703 };
704
705 ocram-ecc@ffd08144 {
706 compatible = "altr,socfpga-ocram-ecc";
707 reg = <0xffd08144 0x4>;
708 iram = <&ocram>;
709 interrupts = <0 178 1>, <0 179 1>;
710 };
711 };
712
713 L2: l2-cache@fffef000 {
714 compatible = "arm,pl310-cache";
715 reg = <0xfffef000 0x1000>;
716 interrupts = <0 38 0x04>;
717 cache-unified;
718 cache-level = <2>;
719 arm,tag-latency = <1 1 1>;
720 arm,data-latency = <2 1 1>;
721 prefetch-data = <1>;
722 prefetch-instr = <1>;
723 arm,shared-override;
724 arm,double-linefill = <1>;
725 arm,double-linefill-incr = <0>;
726 arm,double-linefill-wrap = <1>;
727 arm,prefetch-drop = <0>;
728 arm,prefetch-offset = <7>;
729 };
730
731 l3regs@0xff800000 {
732 compatible = "altr,l3regs", "syscon";
733 reg = <0xff800000 0x1000>;
734 };
735
736 mmc: dwmmc0@ff704000 {
737 compatible = "altr,socfpga-dw-mshc";
738 reg = <0xff704000 0x1000>;
739 interrupts = <0 139 4>;
740 fifo-depth = <0x400>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
744 clock-names = "biu", "ciu";
745 resets = <&rst SDMMC_RESET>;
746 status = "disabled";
747 };
748
749 nand0: nand@ff900000 {
750 #address-cells = <0x1>;
751 #size-cells = <0x0>;
752 compatible = "altr,socfpga-denali-nand";
753 reg = <0xff900000 0x100000>,
754 <0xffb80000 0x10000>;
755 reg-names = "nand_data", "denali_reg";
756 interrupts = <0x0 0x90 0x4>;
757 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
758 clock-names = "nand", "nand_x", "ecc";
759 resets = <&rst NAND_RESET>;
760 status = "disabled";
761 };
762
763 ocram: sram@ffff0000 {
764 compatible = "mmio-sram";
765 reg = <0xffff0000 0x10000>;
766 };
767
768 qspi: spi@ff705000 {
769 compatible = "cdns,qspi-nor";
770 #address-cells = <1>;
771 #size-cells = <0>;
772 reg = <0xff705000 0x1000>,
773 <0xffa00000 0x1000>;
774 interrupts = <0 151 4>;
775 cdns,fifo-depth = <128>;
776 cdns,fifo-width = <4>;
777 cdns,trigger-address = <0x00000000>;
778 clocks = <&qspi_clk>;
779 resets = <&rst QSPI_RESET>;
780 status = "disabled";
781 };
782
783 rst: rstmgr@ffd05000 {
784 #reset-cells = <1>;
785 compatible = "altr,rst-mgr";
786 reg = <0xffd05000 0x1000>;
787 altr,modrst-offset = <0x10>;
788 };
789
790 scu: snoop-control-unit@fffec000 {
791 compatible = "arm,cortex-a9-scu";
792 reg = <0xfffec000 0x100>;
793 };
794
795 sdr: sdr@ffc25000 {
796 compatible = "altr,sdr-ctl", "syscon";
797 reg = <0xffc25000 0x1000>;
798 resets = <&rst SDR_RESET>;
799 };
800
801 sdramedac {
802 compatible = "altr,sdram-edac";
803 altr,sdr-syscon = <&sdr>;
804 interrupts = <0 39 4>;
805 };
806
807 spi0: spi@fff00000 {
808 compatible = "snps,dw-apb-ssi";
809 #address-cells = <1>;
810 #size-cells = <0>;
811 reg = <0xfff00000 0x1000>;
812 interrupts = <0 154 4>;
813 num-cs = <4>;
814 clocks = <&spi_m_clk>;
815 resets = <&rst SPIM0_RESET>;
816 status = "disabled";
817 };
818
819 spi1: spi@fff01000 {
820 compatible = "snps,dw-apb-ssi";
821 #address-cells = <1>;
822 #size-cells = <0>;
823 reg = <0xfff01000 0x1000>;
824 interrupts = <0 155 4>;
825 num-cs = <4>;
826 clocks = <&spi_m_clk>;
827 resets = <&rst SPIM1_RESET>;
828 status = "disabled";
829 };
830
831 sysmgr: sysmgr@ffd08000 {
832 compatible = "altr,sys-mgr", "syscon";
833 reg = <0xffd08000 0x4000>;
834 };
835
836 /* Local timer */
837 timer@fffec600 {
838 compatible = "arm,cortex-a9-twd-timer";
839 reg = <0xfffec600 0x100>;
840 interrupts = <1 13 0xf01>;
841 clocks = <&mpu_periph_clk>;
842 };
843
844 timer0: timer0@ffc08000 {
845 compatible = "snps,dw-apb-timer";
846 interrupts = <0 167 4>;
847 reg = <0xffc08000 0x1000>;
848 clocks = <&l4_sp_clk>;
849 clock-names = "timer";
850 resets = <&rst SPTIMER0_RESET>;
851 reset-names = "timer";
852 };
853
854 timer1: timer1@ffc09000 {
855 compatible = "snps,dw-apb-timer";
856 interrupts = <0 168 4>;
857 reg = <0xffc09000 0x1000>;
858 clocks = <&l4_sp_clk>;
859 clock-names = "timer";
860 resets = <&rst SPTIMER1_RESET>;
861 reset-names = "timer";
862 };
863
864 timer2: timer2@ffd00000 {
865 compatible = "snps,dw-apb-timer";
866 interrupts = <0 169 4>;
867 reg = <0xffd00000 0x1000>;
868 clocks = <&osc1>;
869 clock-names = "timer";
870 resets = <&rst OSC1TIMER0_RESET>;
871 reset-names = "timer";
872 };
873
874 timer3: timer3@ffd01000 {
875 compatible = "snps,dw-apb-timer";
876 interrupts = <0 170 4>;
877 reg = <0xffd01000 0x1000>;
878 clocks = <&osc1>;
879 clock-names = "timer";
880 resets = <&rst OSC1TIMER1_RESET>;
881 reset-names = "timer";
882 };
883
884 uart0: serial0@ffc02000 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0xffc02000 0x1000>;
887 interrupts = <0 162 4>;
888 reg-shift = <2>;
889 reg-io-width = <4>;
890 clocks = <&l4_sp_clk>;
891 dmas = <&pdma 28>,
892 <&pdma 29>;
893 dma-names = "tx", "rx";
894 resets = <&rst UART0_RESET>;
895 };
896
897 uart1: serial1@ffc03000 {
898 compatible = "snps,dw-apb-uart";
899 reg = <0xffc03000 0x1000>;
900 interrupts = <0 163 4>;
901 reg-shift = <2>;
902 reg-io-width = <4>;
903 clocks = <&l4_sp_clk>;
904 dmas = <&pdma 30>,
905 <&pdma 31>;
906 dma-names = "tx", "rx";
907 resets = <&rst UART1_RESET>;
908 };
909
910 usbphy0: usbphy {
911 #phy-cells = <0>;
912 compatible = "usb-nop-xceiv";
913 status = "okay";
914 };
915
916 usb0: usb@ffb00000 {
917 compatible = "snps,dwc2";
918 reg = <0xffb00000 0xffff>;
919 interrupts = <0 125 4>;
920 clocks = <&usb_mp_clk>;
921 clock-names = "otg";
922 resets = <&rst USB0_RESET>;
923 reset-names = "dwc2";
924 phys = <&usbphy0>;
925 phy-names = "usb2-phy";
926 status = "disabled";
927 };
928
929 usb1: usb@ffb40000 {
930 compatible = "snps,dwc2";
931 reg = <0xffb40000 0xffff>;
932 interrupts = <0 128 4>;
933 clocks = <&usb_mp_clk>;
934 clock-names = "otg";
935 resets = <&rst USB1_RESET>;
936 reset-names = "dwc2";
937 phys = <&usbphy0>;
938 phy-names = "usb2-phy";
939 status = "disabled";
940 };
941
942 watchdog0: watchdog@ffd02000 {
943 compatible = "snps,dw-wdt";
944 reg = <0xffd02000 0x1000>;
945 interrupts = <0 171 4>;
946 clocks = <&osc1>;
947 resets = <&rst L4WD0_RESET>;
948 status = "disabled";
949 };
950
951 watchdog1: watchdog@ffd03000 {
952 compatible = "snps,dw-wdt";
953 reg = <0xffd03000 0x1000>;
954 interrupts = <0 172 4>;
955 clocks = <&osc1>;
956 resets = <&rst L4WD1_RESET>;
957 status = "disabled";
958 };
959 };
960};