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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/rv1108-cru.h>
7#include <dt-bindings/pinctrl/rockchip.h>
8#include <dt-bindings/thermal/thermal.h>
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 compatible = "rockchip,rv1108";
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
40 };
41 };
42
43 cpu_opp_table: opp-table-0 {
44 compatible = "operating-points-v2";
45
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
50 };
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
55 };
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
60 };
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
65 };
66 };
67
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71 };
72
73 timer {
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
79 };
80
81 xin24m: oscillator {
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
86 };
87
88 bus_intmem: sram@10080000 {
89 compatible = "mmio-sram";
90 reg = <0x10080000 0x2000>;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges = <0 0x10080000 0x2000>;
94 };
95
96 uart2: serial@10210000 {
97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
98 reg = <0x10210000 0x100>;
99 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
100 reg-shift = <2>;
101 reg-io-width = <4>;
102 clock-frequency = <24000000>;
103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
104 clock-names = "baudclk", "apb_pclk";
105 dmas = <&pdma 6>, <&pdma 7>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart2m0_xfer>;
108 status = "disabled";
109 };
110
111 uart1: serial@10220000 {
112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
113 reg = <0x10220000 0x100>;
114 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 clock-frequency = <24000000>;
118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
119 clock-names = "baudclk", "apb_pclk";
120 dmas = <&pdma 4>, <&pdma 5>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&uart1_xfer>;
123 status = "disabled";
124 };
125
126 uart0: serial@10230000 {
127 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
128 reg = <0x10230000 0x100>;
129 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
130 reg-shift = <2>;
131 reg-io-width = <4>;
132 clock-frequency = <24000000>;
133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
134 clock-names = "baudclk", "apb_pclk";
135 dmas = <&pdma 2>, <&pdma 3>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
138 status = "disabled";
139 };
140
141 i2c1: i2c@10240000 {
142 compatible = "rockchip,rv1108-i2c";
143 reg = <0x10240000 0x1000>;
144 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
148 clock-names = "i2c", "pclk";
149 pinctrl-names = "default";
150 pinctrl-0 = <&i2c1_xfer>;
151 rockchip,grf = <&grf>;
152 status = "disabled";
153 };
154
155 i2c2: i2c@10250000 {
156 compatible = "rockchip,rv1108-i2c";
157 reg = <0x10250000 0x1000>;
158 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
162 clock-names = "i2c", "pclk";
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c2m1_xfer>;
165 rockchip,grf = <&grf>;
166 status = "disabled";
167 };
168
169 i2c3: i2c@10260000 {
170 compatible = "rockchip,rv1108-i2c";
171 reg = <0x10260000 0x1000>;
172 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
176 clock-names = "i2c", "pclk";
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c3_xfer>;
179 rockchip,grf = <&grf>;
180 status = "disabled";
181 };
182
183 spi: spi@10270000 {
184 compatible = "rockchip,rv1108-spi";
185 reg = <0x10270000 0x1000>;
186 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
188 clock-names = "spiclk", "apb_pclk";
189 dmas = <&pdma 8>, <&pdma 9>;
190 dma-names = "tx", "rx";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 status = "disabled";
194 };
195
196 pwm4: pwm@10280000 {
197 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
198 reg = <0x10280000 0x10>;
199 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
201 clock-names = "pwm", "pclk";
202 pinctrl-names = "default";
203 pinctrl-0 = <&pwm4_pin>;
204 #pwm-cells = <3>;
205 status = "disabled";
206 };
207
208 pwm5: pwm@10280010 {
209 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
210 reg = <0x10280010 0x10>;
211 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
213 clock-names = "pwm", "pclk";
214 pinctrl-names = "default";
215 pinctrl-0 = <&pwm5_pin>;
216 #pwm-cells = <3>;
217 status = "disabled";
218 };
219
220 pwm6: pwm@10280020 {
221 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
222 reg = <0x10280020 0x10>;
223 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
225 clock-names = "pwm", "pclk";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pwm6_pin>;
228 #pwm-cells = <3>;
229 status = "disabled";
230 };
231
232 pwm7: pwm@10280030 {
233 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
234 reg = <0x10280030 0x10>;
235 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
237 clock-names = "pwm", "pclk";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pwm7_pin>;
240 #pwm-cells = <3>;
241 status = "disabled";
242 };
243
244 pdma: dma-controller@102a0000 {
245 compatible = "arm,pl330", "arm,primecell";
246 reg = <0x102a0000 0x4000>;
247 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
248 #dma-cells = <1>;
249 arm,pl330-broken-no-flushp;
250 arm,pl330-periph-burst;
251 clocks = <&cru ACLK_DMAC>;
252 clock-names = "apb_pclk";
253 };
254
255 grf: syscon@10300000 {
256 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
257 reg = <0x10300000 0x1000>;
258 #address-cells = <1>;
259 #size-cells = <1>;
260
261 io_domains: io-domains {
262 compatible = "rockchip,rv1108-io-voltage-domain";
263 status = "disabled";
264 };
265
266 u2phy: usb2phy@100 {
267 compatible = "rockchip,rv1108-usb2phy";
268 reg = <0x100 0x0c>;
269 clocks = <&cru SCLK_USBPHY>;
270 clock-names = "phyclk";
271 #clock-cells = <0>;
272 clock-output-names = "usbphy";
273 rockchip,usbgrf = <&usbgrf>;
274 status = "disabled";
275
276 u2phy_otg: otg-port {
277 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-names = "otg-mux";
279 #phy-cells = <0>;
280 status = "disabled";
281 };
282
283 u2phy_host: host-port {
284 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-names = "linestate";
286 #phy-cells = <0>;
287 status = "disabled";
288 };
289 };
290 };
291
292 timer: timer@10350000 {
293 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
294 reg = <0x10350000 0x20>;
295 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&cru PCLK_TIMER>, <&xin24m>;
297 clock-names = "pclk", "timer";
298 };
299
300 watchdog: watchdog@10360000 {
301 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
302 reg = <0x10360000 0x100>;
303 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cru PCLK_WDT>;
305 status = "disabled";
306 };
307
308 thermal-zones {
309 soc_thermal: soc-thermal {
310 polling-delay-passive = <20>;
311 polling-delay = <1000>;
312 sustainable-power = <50>;
313 thermal-sensors = <&tsadc 0>;
314
315 trips {
316 threshold: trip-point0 {
317 temperature = <70000>;
318 hysteresis = <2000>;
319 type = "passive";
320 };
321 target: trip-point1 {
322 temperature = <85000>;
323 hysteresis = <2000>;
324 type = "passive";
325 };
326 soc_crit: soc-crit {
327 temperature = <95000>;
328 hysteresis = <2000>;
329 type = "critical";
330 };
331 };
332
333 cooling-maps {
334 map0 {
335 trip = <&target>;
336 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
337 contribution = <4096>;
338 };
339 };
340 };
341 };
342
343 tsadc: tsadc@10370000 {
344 compatible = "rockchip,rv1108-tsadc";
345 reg = <0x10370000 0x100>;
346 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
347 assigned-clocks = <&cru SCLK_TSADC>;
348 assigned-clock-rates = <750000>;
349 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
350 clock-names = "tsadc", "apb_pclk";
351 pinctrl-names = "init", "default", "sleep";
352 pinctrl-0 = <&otp_pin>;
353 pinctrl-1 = <&otp_out>;
354 pinctrl-2 = <&otp_pin>;
355 resets = <&cru SRST_TSADC>;
356 reset-names = "tsadc-apb";
357 rockchip,hw-tshut-temp = <120000>;
358 #thermal-sensor-cells = <1>;
359 status = "disabled";
360 };
361
362 adc: adc@1038c000 {
363 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
364 reg = <0x1038c000 0x100>;
365 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
366 #io-channel-cells = <1>;
367 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
368 clock-names = "saradc", "apb_pclk";
369 status = "disabled";
370 };
371
372 i2c0: i2c@20000000 {
373 compatible = "rockchip,rv1108-i2c";
374 reg = <0x20000000 0x1000>;
375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c0_xfer>;
382 rockchip,grf = <&grf>;
383 status = "disabled";
384 };
385
386 pwm0: pwm@20040000 {
387 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
388 reg = <0x20040000 0x10>;
389 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
391 clock-names = "pwm", "pclk";
392 pinctrl-names = "default";
393 pinctrl-0 = <&pwm0_pin>;
394 #pwm-cells = <3>;
395 status = "disabled";
396 };
397
398 pwm1: pwm@20040010 {
399 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
400 reg = <0x20040010 0x10>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
403 clock-names = "pwm", "pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&pwm1_pin>;
406 #pwm-cells = <3>;
407 status = "disabled";
408 };
409
410 pwm2: pwm@20040020 {
411 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
412 reg = <0x20040020 0x10>;
413 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
415 clock-names = "pwm", "pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&pwm2_pin>;
418 #pwm-cells = <3>;
419 status = "disabled";
420 };
421
422 pwm3: pwm@20040030 {
423 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
424 reg = <0x20040030 0x10>;
425 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
427 clock-names = "pwm", "pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&pwm3_pin>;
430 #pwm-cells = <3>;
431 status = "disabled";
432 };
433
434 pmugrf: syscon@20060000 {
435 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
436 reg = <0x20060000 0x1000>;
437
438 pmu_io_domains: io-domains {
439 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
440 status = "disabled";
441 };
442 };
443
444 usbgrf: syscon@202a0000 {
445 compatible = "rockchip,rv1108-usbgrf", "syscon";
446 reg = <0x202a0000 0x1000>;
447 };
448
449 cru: clock-controller@20200000 {
450 compatible = "rockchip,rv1108-cru";
451 reg = <0x20200000 0x1000>;
452 clocks = <&xin24m>;
453 clock-names = "xin24m";
454 rockchip,grf = <&grf>;
455 #clock-cells = <1>;
456 #reset-cells = <1>;
457 };
458
459 nfc: nand-controller@30100000 {
460 compatible = "rockchip,rv1108-nfc";
461 reg = <0x30100000 0x1000>;
462 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
464 clock-names = "ahb", "nfc";
465 assigned-clocks = <&cru SCLK_NANDC>;
466 assigned-clock-rates = <150000000>;
467 status = "disabled";
468 };
469
470 emmc: mmc@30110000 {
471 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
472 reg = <0x30110000 0x4000>;
473 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
475 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
476 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
477 fifo-depth = <0x100>;
478 max-frequency = <150000000>;
479 status = "disabled";
480 };
481
482 sdio: mmc@30120000 {
483 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
484 reg = <0x30120000 0x4000>;
485 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
487 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
488 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
489 fifo-depth = <0x100>;
490 max-frequency = <150000000>;
491 status = "disabled";
492 };
493
494 sdmmc: mmc@30130000 {
495 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
496 reg = <0x30130000 0x4000>;
497 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
499 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
500 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
501 fifo-depth = <0x100>;
502 max-frequency = <100000000>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
505 status = "disabled";
506 };
507
508 usb_host_ehci: usb@30140000 {
509 compatible = "generic-ehci";
510 reg = <0x30140000 0x20000>;
511 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cru HCLK_HOST0>, <&u2phy>;
513 phys = <&u2phy_host>;
514 phy-names = "usb";
515 status = "disabled";
516 };
517
518 usb_host_ohci: usb@30160000 {
519 compatible = "generic-ohci";
520 reg = <0x30160000 0x20000>;
521 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru HCLK_HOST0>, <&u2phy>;
523 phys = <&u2phy_host>;
524 phy-names = "usb";
525 status = "disabled";
526 };
527
528 usb_otg: usb@30180000 {
529 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
530 "snps,dwc2";
531 reg = <0x30180000 0x40000>;
532 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru HCLK_OTG>;
534 clock-names = "otg";
535 dr_mode = "otg";
536 g-np-tx-fifo-size = <16>;
537 g-rx-fifo-size = <280>;
538 g-tx-fifo-size = <256 128 128 64 32 16>;
539 phys = <&u2phy_otg>;
540 phy-names = "usb2-phy";
541 status = "disabled";
542 };
543
544 sfc: spi@301c0000 {
545 compatible = "rockchip,sfc";
546 reg = <0x301c0000 0x4000>;
547 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
549 clock-names = "clk_sfc", "hclk_sfc";
550 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
551 pinctrl-names = "default";
552 status = "disabled";
553 };
554
555 gmac: ethernet@30200000 {
556 compatible = "rockchip,rv1108-gmac";
557 reg = <0x30200000 0x10000>;
558 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-names = "macirq", "eth_wake_irq";
561 clocks = <&cru SCLK_MAC>,
562 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
563 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
564 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
565 clock-names = "stmmaceth",
566 "mac_clk_rx", "mac_clk_tx",
567 "clk_mac_ref", "clk_mac_refout",
568 "aclk_mac", "pclk_mac";
569 /* rv1108 only supports an rmii interface */
570 phy-mode = "rmii";
571 pinctrl-names = "default";
572 pinctrl-0 = <&rmii_pins>;
573 rockchip,grf = <&grf>;
574 status = "disabled";
575 };
576
577 gic: interrupt-controller@32010000 {
578 compatible = "arm,gic-400";
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 #address-cells = <0>;
582
583 reg = <0x32011000 0x1000>,
584 <0x32012000 0x2000>,
585 <0x32014000 0x2000>,
586 <0x32016000 0x2000>;
587 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
588 };
589
590 pinctrl: pinctrl {
591 compatible = "rockchip,rv1108-pinctrl";
592 rockchip,grf = <&grf>;
593 rockchip,pmu = <&pmugrf>;
594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges;
597
598 gpio0: gpio@20030000 {
599 compatible = "rockchip,gpio-bank";
600 reg = <0x20030000 0x100>;
601 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cru PCLK_GPIO0_PMU>;
603
604 gpio-controller;
605 #gpio-cells = <2>;
606
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 };
610
611 gpio1: gpio@10310000 {
612 compatible = "rockchip,gpio-bank";
613 reg = <0x10310000 0x100>;
614 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cru PCLK_GPIO1>;
616
617 gpio-controller;
618 #gpio-cells = <2>;
619
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 };
623
624 gpio2: gpio@10320000 {
625 compatible = "rockchip,gpio-bank";
626 reg = <0x10320000 0x100>;
627 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&cru PCLK_GPIO2>;
629
630 gpio-controller;
631 #gpio-cells = <2>;
632
633 interrupt-controller;
634 #interrupt-cells = <2>;
635 };
636
637 gpio3: gpio@10330000 {
638 compatible = "rockchip,gpio-bank";
639 reg = <0x10330000 0x100>;
640 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru PCLK_GPIO3>;
642
643 gpio-controller;
644 #gpio-cells = <2>;
645
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 };
649
650 pcfg_pull_up: pcfg-pull-up {
651 bias-pull-up;
652 };
653
654 pcfg_pull_down: pcfg-pull-down {
655 bias-pull-down;
656 };
657
658 pcfg_pull_none: pcfg-pull-none {
659 bias-disable;
660 };
661
662 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
663 drive-strength = <8>;
664 };
665
666 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
667 drive-strength = <12>;
668 };
669
670 pcfg_pull_none_smt: pcfg-pull-none-smt {
671 bias-disable;
672 input-schmitt-enable;
673 };
674
675 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
676 bias-pull-up;
677 drive-strength = <8>;
678 };
679
680 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
681 drive-strength = <4>;
682 };
683
684 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
685 bias-pull-up;
686 drive-strength = <4>;
687 };
688
689 pcfg_output_high: pcfg-output-high {
690 output-high;
691 };
692
693 pcfg_output_low: pcfg-output-low {
694 output-low;
695 };
696
697 pcfg_input_high: pcfg-input-high {
698 bias-pull-up;
699 input-enable;
700 };
701
702 emmc {
703 emmc_bus8: emmc-bus8 {
704 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
705 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
706 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
707 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
708 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
709 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
710 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
711 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
712 };
713
714 emmc_clk: emmc-clk {
715 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
716 };
717
718 emmc_cmd: emmc-cmd {
719 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
720 };
721 };
722
723 sfc {
724 sfc_bus4: sfc-bus4 {
725 rockchip,pins =
726 <2 RK_PA0 3 &pcfg_pull_none>,
727 <2 RK_PA1 3 &pcfg_pull_none>,
728 <2 RK_PA2 3 &pcfg_pull_none>,
729 <2 RK_PA3 3 &pcfg_pull_none>;
730 };
731
732 sfc_bus2: sfc-bus2 {
733 rockchip,pins =
734 <2 RK_PA0 3 &pcfg_pull_none>,
735 <2 RK_PA1 3 &pcfg_pull_none>;
736 };
737
738 sfc_cs0: sfc-cs0 {
739 rockchip,pins =
740 <2 RK_PB4 3 &pcfg_pull_none>;
741 };
742
743 sfc_clk: sfc-clk {
744 rockchip,pins =
745 <2 RK_PB7 2 &pcfg_pull_none>;
746 };
747 };
748
749 gmac {
750 rmii_pins: rmii-pins {
751 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
752 <1 RK_PC3 2 &pcfg_pull_none>,
753 <1 RK_PC4 2 &pcfg_pull_none>,
754 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
755 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
756 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
757 <1 RK_PB5 3 &pcfg_pull_none>,
758 <1 RK_PB6 3 &pcfg_pull_none>,
759 <1 RK_PB7 3 &pcfg_pull_none>,
760 <1 RK_PC2 3 &pcfg_pull_none>;
761 };
762 };
763
764 i2c0 {
765 i2c0_xfer: i2c0-xfer {
766 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
767 <0 RK_PB2 1 &pcfg_pull_none_smt>;
768 };
769 };
770
771 i2c1 {
772 i2c1_xfer: i2c1-xfer {
773 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
774 <2 RK_PD4 1 &pcfg_pull_up>;
775 };
776 };
777
778 i2c2m1 {
779 i2c2m1_xfer: i2c2m1-xfer {
780 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
781 <0 RK_PC6 3 &pcfg_pull_none>;
782 };
783
784 i2c2m1_pins: i2c2m1-pins {
785 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
786 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
787 };
788 };
789
790 i2c2m05v {
791 i2c2m05v_xfer: i2c2m05v-xfer {
792 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
793 <1 RK_PD4 2 &pcfg_pull_none>;
794 };
795
796 i2c2m05v_pins: i2c2m05v-pins {
797 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
798 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
799 };
800 };
801
802 i2c3 {
803 i2c3_xfer: i2c3-xfer {
804 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
805 <0 RK_PC4 2 &pcfg_pull_none>;
806 };
807 };
808
809 pwm0 {
810 pwm0_pin: pwm0-pin {
811 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
812 };
813 };
814
815 pwm1 {
816 pwm1_pin: pwm1-pin {
817 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
818 };
819 };
820
821 pwm2 {
822 pwm2_pin: pwm2-pin {
823 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
824 };
825 };
826
827 pwm3 {
828 pwm3_pin: pwm3-pin {
829 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
830 };
831 };
832
833 pwm4 {
834 pwm4_pin: pwm4-pin {
835 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
836 };
837 };
838
839 pwm5 {
840 pwm5_pin: pwm5-pin {
841 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
842 };
843 };
844
845 pwm6 {
846 pwm6_pin: pwm6-pin {
847 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
848 };
849 };
850
851 pwm7 {
852 pwm7_pin: pwm7-pin {
853 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
854 };
855 };
856
857 sdmmc {
858 sdmmc_clk: sdmmc-clk {
859 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
860 };
861
862 sdmmc_cmd: sdmmc-cmd {
863 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
864 };
865
866 sdmmc_cd: sdmmc-cd {
867 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
868 };
869
870 sdmmc_bus1: sdmmc-bus1 {
871 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
872 };
873
874 sdmmc_bus4: sdmmc-bus4 {
875 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
876 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
877 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
878 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
879 };
880 };
881
882 spim0 {
883 spim0_clk: spim0-clk {
884 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
885 };
886
887 spim0_cs0: spim0-cs0 {
888 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
889 };
890
891 spim0_tx: spim0-tx {
892 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
893 };
894
895 spim0_rx: spim0-rx {
896 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
897 };
898 };
899
900 spim1 {
901 spim1_clk: spim1-clk {
902 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
903 };
904
905 spim1_cs0: spim1-cs0 {
906 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
907 };
908
909 spim1_rx: spim1-rx {
910 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
911 };
912
913 spim1_tx: spim1-tx {
914 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
915 };
916 };
917
918 tsadc {
919 otp_out: otp-out {
920 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
921 };
922
923 otp_pin: otp-pin {
924 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
925 };
926 };
927
928 uart0 {
929 uart0_xfer: uart0-xfer {
930 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
931 <3 RK_PA5 1 &pcfg_pull_none>;
932 };
933
934 uart0_cts: uart0-cts {
935 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
936 };
937
938 uart0_rts: uart0-rts {
939 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
940 };
941
942 uart0_rts_pin: uart0-rts-pin {
943 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
944 };
945 };
946
947 uart1 {
948 uart1_xfer: uart1-xfer {
949 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
950 <1 RK_PD2 1 &pcfg_pull_none>;
951 };
952
953 uart1_cts: uart1-cts {
954 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
955 };
956
957 uart1_rts: uart1-rts {
958 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
959 };
960 };
961
962 uart2m0 {
963 uart2m0_xfer: uart2m0-xfer {
964 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
965 <2 RK_PD1 1 &pcfg_pull_none>;
966 };
967 };
968
969 uart2m1 {
970 uart2m1_xfer: uart2m1-xfer {
971 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
972 <3 RK_PC2 2 &pcfg_pull_none>;
973 };
974 };
975
976 uart2_5v {
977 uart2_5v_cts: uart2_5v-cts {
978 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
979 };
980
981 uart2_5v_rts: uart2_5v-rts {
982 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
983 };
984 };
985 };
986};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/rv1108-cru.h>
7#include <dt-bindings/pinctrl/rockchip.h>
8#include <dt-bindings/thermal/thermal.h>
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 compatible = "rockchip,rv1108";
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
40 };
41 };
42
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
45
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
50 };
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
55 };
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
60 };
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
65 };
66 };
67
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71 };
72
73 timer {
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
79 };
80
81 xin24m: oscillator {
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
86 };
87
88 amba {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 pdma: pdma@102a0000 {
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 clocks = <&cru ACLK_DMAC>;
101 clock-names = "apb_pclk";
102 };
103 };
104
105 bus_intmem@10080000 {
106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
111 };
112
113 uart2: serial@10210000 {
114 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115 reg = <0x10210000 0x100>;
116 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clock-frequency = <24000000>;
120 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121 clock-names = "baudclk", "apb_pclk";
122 dmas = <&pdma 6>, <&pdma 7>;
123 #dma-cells = <2>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
126 status = "disabled";
127 };
128
129 uart1: serial@10220000 {
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
138 dmas = <&pdma 4>, <&pdma 5>;
139 #dma-cells = <2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&uart1_xfer>;
142 status = "disabled";
143 };
144
145 uart0: serial@10230000 {
146 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
147 reg = <0x10230000 0x100>;
148 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
149 reg-shift = <2>;
150 reg-io-width = <4>;
151 clock-frequency = <24000000>;
152 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
153 clock-names = "baudclk", "apb_pclk";
154 dmas = <&pdma 2>, <&pdma 3>;
155 #dma-cells = <2>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
158 status = "disabled";
159 };
160
161 i2c1: i2c@10240000 {
162 compatible = "rockchip,rv1108-i2c";
163 reg = <0x10240000 0x1000>;
164 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
168 clock-names = "i2c", "pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c1_xfer>;
171 rockchip,grf = <&grf>;
172 status = "disabled";
173 };
174
175 i2c2: i2c@10250000 {
176 compatible = "rockchip,rv1108-i2c";
177 reg = <0x10250000 0x1000>;
178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
182 clock-names = "i2c", "pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2m1_xfer>;
185 rockchip,grf = <&grf>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@10260000 {
190 compatible = "rockchip,rv1108-i2c";
191 reg = <0x10260000 0x1000>;
192 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
196 clock-names = "i2c", "pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&i2c3_xfer>;
199 rockchip,grf = <&grf>;
200 status = "disabled";
201 };
202
203 spi: spi@10270000 {
204 compatible = "rockchip,rv1108-spi";
205 reg = <0x10270000 0x1000>;
206 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
208 clock-names = "spiclk", "apb_pclk";
209 dmas = <&pdma 8>, <&pdma 9>;
210 dma-names = "tx", "rx";
211 #dma-cells = <2>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 status = "disabled";
215 };
216
217 pwm4: pwm@10280000 {
218 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
219 reg = <0x10280000 0x10>;
220 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
222 clock-names = "pwm", "pclk";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pwm4_pin>;
225 #pwm-cells = <3>;
226 status = "disabled";
227 };
228
229 pwm5: pwm@10280010 {
230 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
231 reg = <0x10280010 0x10>;
232 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
234 clock-names = "pwm", "pclk";
235 pinctrl-names = "default";
236 pinctrl-0 = <&pwm5_pin>;
237 #pwm-cells = <3>;
238 status = "disabled";
239 };
240
241 pwm6: pwm@10280020 {
242 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
243 reg = <0x10280020 0x10>;
244 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
246 clock-names = "pwm", "pclk";
247 pinctrl-names = "default";
248 pinctrl-0 = <&pwm6_pin>;
249 #pwm-cells = <3>;
250 status = "disabled";
251 };
252
253 pwm7: pwm@10280030 {
254 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
255 reg = <0x10280030 0x10>;
256 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
258 clock-names = "pwm", "pclk";
259 pinctrl-names = "default";
260 pinctrl-0 = <&pwm7_pin>;
261 #pwm-cells = <3>;
262 status = "disabled";
263 };
264
265 grf: syscon@10300000 {
266 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
267 reg = <0x10300000 0x1000>;
268 #address-cells = <1>;
269 #size-cells = <1>;
270
271 u2phy: usb2-phy@100 {
272 compatible = "rockchip,rv1108-usb2phy";
273 reg = <0x100 0x0c>;
274 clocks = <&cru SCLK_USBPHY>;
275 clock-names = "phyclk";
276 #clock-cells = <0>;
277 clock-output-names = "usbphy";
278 rockchip,usbgrf = <&usbgrf>;
279 status = "disabled";
280
281 u2phy_otg: otg-port {
282 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "otg-mux";
284 #phy-cells = <0>;
285 status = "disabled";
286 };
287
288 u2phy_host: host-port {
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "linestate";
291 #phy-cells = <0>;
292 status = "disabled";
293 };
294 };
295 };
296
297 timer: timer@10350000 {
298 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
299 reg = <0x10350000 0x20>;
300 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&xin24m>, <&cru PCLK_TIMER>;
302 clock-names = "timer", "pclk";
303 };
304
305 watchdog: wdt@10360000 {
306 compatible = "snps,dw-wdt";
307 reg = <0x10360000 0x100>;
308 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cru PCLK_WDT>;
310 clock-names = "pclk_wdt";
311 status = "disabled";
312 };
313
314 thermal-zones {
315 soc_thermal: soc-thermal {
316 polling-delay-passive = <20>;
317 polling-delay = <1000>;
318 sustainable-power = <50>;
319 thermal-sensors = <&tsadc 0>;
320
321 trips {
322 threshold: trip-point0 {
323 temperature = <70000>;
324 hysteresis = <2000>;
325 type = "passive";
326 };
327 target: trip-point1 {
328 temperature = <85000>;
329 hysteresis = <2000>;
330 type = "passive";
331 };
332 soc_crit: soc-crit {
333 temperature = <95000>;
334 hysteresis = <2000>;
335 type = "critical";
336 };
337 };
338
339 cooling-maps {
340 map0 {
341 trip = <&target>;
342 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
343 contribution = <4096>;
344 };
345 };
346 };
347 };
348
349 tsadc: tsadc@10370000 {
350 compatible = "rockchip,rv1108-tsadc";
351 reg = <0x10370000 0x100>;
352 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
353 assigned-clocks = <&cru SCLK_TSADC>;
354 assigned-clock-rates = <750000>;
355 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
356 clock-names = "tsadc", "apb_pclk";
357 pinctrl-names = "init", "default", "sleep";
358 pinctrl-0 = <&otp_gpio>;
359 pinctrl-1 = <&otp_out>;
360 pinctrl-2 = <&otp_gpio>;
361 resets = <&cru SRST_TSADC>;
362 reset-names = "tsadc-apb";
363 rockchip,hw-tshut-temp = <120000>;
364 #thermal-sensor-cells = <1>;
365 status = "disabled";
366 };
367
368 adc: adc@1038c000 {
369 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
370 reg = <0x1038c000 0x100>;
371 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
372 #io-channel-cells = <1>;
373 clock-frequency = <1000000>;
374 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
375 clock-names = "saradc", "apb_pclk";
376 status = "disabled";
377 };
378
379 i2c0: i2c@20000000 {
380 compatible = "rockchip,rv1108-i2c";
381 reg = <0x20000000 0x1000>;
382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
389 rockchip,grf = <&grf>;
390 status = "disabled";
391 };
392
393 pwm0: pwm@20040000 {
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
395 reg = <0x20040000 0x10>;
396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
398 clock-names = "pwm", "pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm0_pin>;
401 #pwm-cells = <3>;
402 status = "disabled";
403 };
404
405 pwm1: pwm@20040010 {
406 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
407 reg = <0x20040010 0x10>;
408 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
410 clock-names = "pwm", "pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm1_pin>;
413 #pwm-cells = <3>;
414 status = "disabled";
415 };
416
417 pwm2: pwm@20040020 {
418 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
419 reg = <0x20040020 0x10>;
420 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
425 #pwm-cells = <3>;
426 status = "disabled";
427 };
428
429 pwm3: pwm@20040030 {
430 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
431 reg = <0x20040030 0x10>;
432 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 #pwm-cells = <3>;
438 status = "disabled";
439 };
440
441 pmugrf: syscon@20060000 {
442 compatible = "rockchip,rv1108-pmugrf", "syscon";
443 reg = <0x20060000 0x1000>;
444 };
445
446 usbgrf: syscon@202a0000 {
447 compatible = "rockchip,rv1108-usbgrf", "syscon";
448 reg = <0x202a0000 0x1000>;
449 };
450
451 cru: clock-controller@20200000 {
452 compatible = "rockchip,rv1108-cru";
453 reg = <0x20200000 0x1000>;
454 rockchip,grf = <&grf>;
455 #clock-cells = <1>;
456 #reset-cells = <1>;
457 };
458
459 emmc: dwmmc@30110000 {
460 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
461 reg = <0x30110000 0x4000>;
462 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
464 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
465 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
466 fifo-depth = <0x100>;
467 max-frequency = <150000000>;
468 status = "disabled";
469 };
470
471 sdio: dwmmc@30120000 {
472 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
473 reg = <0x30120000 0x4000>;
474 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
476 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
477 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
478 fifo-depth = <0x100>;
479 max-frequency = <150000000>;
480 status = "disabled";
481 };
482
483 sdmmc: dwmmc@30130000 {
484 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
485 reg = <0x30130000 0x4000>;
486 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
488 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
489 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
490 fifo-depth = <0x100>;
491 max-frequency = <100000000>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
494 status = "disabled";
495 };
496
497 usb_host_ehci: usb@30140000 {
498 compatible = "generic-ehci";
499 reg = <0x30140000 0x20000>;
500 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cru HCLK_HOST0>, <&u2phy>;
502 clock-names = "usbhost", "utmi";
503 phys = <&u2phy_host>;
504 phy-names = "usb";
505 status = "disabled";
506 };
507
508 usb_host_ohci: usb@30160000 {
509 compatible = "generic-ohci";
510 reg = <0x30160000 0x20000>;
511 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cru HCLK_HOST0>, <&u2phy>;
513 clock-names = "usbhost", "utmi";
514 phys = <&u2phy_host>;
515 phy-names = "usb";
516 status = "disabled";
517 };
518
519 usb_otg: usb@30180000 {
520 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
521 "snps,dwc2";
522 reg = <0x30180000 0x40000>;
523 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_OTG>;
525 clock-names = "otg";
526 dr_mode = "otg";
527 g-np-tx-fifo-size = <16>;
528 g-rx-fifo-size = <280>;
529 g-tx-fifo-size = <256 128 128 64 32 16>;
530 g-use-dma;
531 phys = <&u2phy_otg>;
532 phy-names = "usb2-phy";
533 status = "disabled";
534 };
535
536 gmac: eth@30200000 {
537 compatible = "rockchip,rv1108-gmac";
538 reg = <0x30200000 0x10000>;
539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "macirq", "eth_wake_irq";
542 clocks = <&cru SCLK_MAC>,
543 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
544 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
545 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
546 clock-names = "stmmaceth",
547 "mac_clk_rx", "mac_clk_tx",
548 "clk_mac_ref", "clk_mac_refout",
549 "aclk_mac", "pclk_mac";
550 /* rv1108 only supports an rmii interface */
551 phy-mode = "rmii";
552 pinctrl-names = "default";
553 pinctrl-0 = <&rmii_pins>;
554 rockchip,grf = <&grf>;
555 status = "disabled";
556 };
557
558 gic: interrupt-controller@32010000 {
559 compatible = "arm,gic-400";
560 interrupt-controller;
561 #interrupt-cells = <3>;
562 #address-cells = <0>;
563
564 reg = <0x32011000 0x1000>,
565 <0x32012000 0x2000>,
566 <0x32014000 0x2000>,
567 <0x32016000 0x2000>;
568 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
569 };
570
571 pinctrl: pinctrl {
572 compatible = "rockchip,rv1108-pinctrl";
573 rockchip,grf = <&grf>;
574 rockchip,pmu = <&pmugrf>;
575 #address-cells = <1>;
576 #size-cells = <1>;
577 ranges;
578
579 gpio0: gpio0@20030000 {
580 compatible = "rockchip,gpio-bank";
581 reg = <0x20030000 0x100>;
582 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cru PCLK_GPIO0_PMU>;
584
585 gpio-controller;
586 #gpio-cells = <2>;
587
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 };
591
592 gpio1: gpio1@10310000 {
593 compatible = "rockchip,gpio-bank";
594 reg = <0x10310000 0x100>;
595 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cru PCLK_GPIO1>;
597
598 gpio-controller;
599 #gpio-cells = <2>;
600
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 };
604
605 gpio2: gpio2@10320000 {
606 compatible = "rockchip,gpio-bank";
607 reg = <0x10320000 0x100>;
608 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&cru PCLK_GPIO2>;
610
611 gpio-controller;
612 #gpio-cells = <2>;
613
614 interrupt-controller;
615 #interrupt-cells = <2>;
616 };
617
618 gpio3: gpio3@10330000 {
619 compatible = "rockchip,gpio-bank";
620 reg = <0x10330000 0x100>;
621 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cru PCLK_GPIO3>;
623
624 gpio-controller;
625 #gpio-cells = <2>;
626
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 };
630
631 pcfg_pull_up: pcfg-pull-up {
632 bias-pull-up;
633 };
634
635 pcfg_pull_down: pcfg-pull-down {
636 bias-pull-down;
637 };
638
639 pcfg_pull_none: pcfg-pull-none {
640 bias-disable;
641 };
642
643 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
644 drive-strength = <8>;
645 };
646
647 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
648 drive-strength = <12>;
649 };
650
651 pcfg_pull_none_smt: pcfg-pull-none-smt {
652 bias-disable;
653 input-schmitt-enable;
654 };
655
656 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
657 bias-pull-up;
658 drive-strength = <8>;
659 };
660
661 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
662 drive-strength = <4>;
663 };
664
665 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
666 bias-pull-up;
667 drive-strength = <4>;
668 };
669
670 pcfg_output_high: pcfg-output-high {
671 output-high;
672 };
673
674 pcfg_output_low: pcfg-output-low {
675 output-low;
676 };
677
678 pcfg_input_high: pcfg-input-high {
679 bias-pull-up;
680 input-enable;
681 };
682
683 emmc {
684 emmc_bus8: emmc-bus8 {
685 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
686 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
687 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
688 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
689 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
690 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
691 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
692 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
693 };
694
695 emmc_clk: emmc-clk {
696 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
697 };
698
699 emmc_cmd: emmc-cmd {
700 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
701 };
702 };
703
704 gmac {
705 rmii_pins: rmii-pins {
706 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
707 <1 RK_PC3 2 &pcfg_pull_none>,
708 <1 RK_PC4 2 &pcfg_pull_none>,
709 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
710 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
711 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
712 <1 RK_PB5 3 &pcfg_pull_none>,
713 <1 RK_PB6 3 &pcfg_pull_none>,
714 <1 RK_PB7 3 &pcfg_pull_none>,
715 <1 RK_PC2 3 &pcfg_pull_none>;
716 };
717 };
718
719 i2c0 {
720 i2c0_xfer: i2c0-xfer {
721 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
722 <0 RK_PB2 1 &pcfg_pull_none_smt>;
723 };
724 };
725
726 i2c1 {
727 i2c1_xfer: i2c1-xfer {
728 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
729 <2 RK_PD4 1 &pcfg_pull_up>;
730 };
731 };
732
733 i2c2m1 {
734 i2c2m1_xfer: i2c2m1-xfer {
735 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
736 <0 RK_PC6 3 &pcfg_pull_none>;
737 };
738
739 i2c2m1_gpio: i2c2m1-gpio {
740 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
741 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
742 };
743 };
744
745 i2c2m05v {
746 i2c2m05v_xfer: i2c2m05v-xfer {
747 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
748 <1 RK_PD4 2 &pcfg_pull_none>;
749 };
750
751 i2c2m05v_gpio: i2c2m05v-gpio {
752 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
753 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
754 };
755 };
756
757 i2c3 {
758 i2c3_xfer: i2c3-xfer {
759 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
760 <0 RK_PC4 2 &pcfg_pull_none>;
761 };
762 };
763
764 pwm0 {
765 pwm0_pin: pwm0-pin {
766 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
767 };
768 };
769
770 pwm1 {
771 pwm1_pin: pwm1-pin {
772 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
773 };
774 };
775
776 pwm2 {
777 pwm2_pin: pwm2-pin {
778 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
779 };
780 };
781
782 pwm3 {
783 pwm3_pin: pwm3-pin {
784 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
785 };
786 };
787
788 pwm4 {
789 pwm4_pin: pwm4-pin {
790 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
791 };
792 };
793
794 pwm5 {
795 pwm5_pin: pwm5-pin {
796 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
797 };
798 };
799
800 pwm6 {
801 pwm6_pin: pwm6-pin {
802 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
803 };
804 };
805
806 pwm7 {
807 pwm7_pin: pwm7-pin {
808 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
809 };
810 };
811
812 sdmmc {
813 sdmmc_clk: sdmmc-clk {
814 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
815 };
816
817 sdmmc_cmd: sdmmc-cmd {
818 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
819 };
820
821 sdmmc_cd: sdmmc-cd {
822 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
823 };
824
825 sdmmc_bus1: sdmmc-bus1 {
826 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
827 };
828
829 sdmmc_bus4: sdmmc-bus4 {
830 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
831 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
832 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
833 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
834 };
835 };
836
837 spim0 {
838 spim0_clk: spim0-clk {
839 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
840 };
841
842 spim0_cs0: spim0-cs0 {
843 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
844 };
845
846 spim0_tx: spim0-tx {
847 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
848 };
849
850 spim0_rx: spim0-rx {
851 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
852 };
853 };
854
855 spim1 {
856 spim1_clk: spim1-clk {
857 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
858 };
859
860 spim1_cs0: spim1-cs0 {
861 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
862 };
863
864 spim1_rx: spim1-rx {
865 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
866 };
867
868 spim1_tx: spim1-tx {
869 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
870 };
871 };
872
873 tsadc {
874 otp_out: otp-out {
875 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
876 };
877
878 otp_gpio: otp-gpio {
879 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
880 };
881 };
882
883 uart0 {
884 uart0_xfer: uart0-xfer {
885 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
886 <3 RK_PA5 1 &pcfg_pull_none>;
887 };
888
889 uart0_cts: uart0-cts {
890 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
891 };
892
893 uart0_rts: uart0-rts {
894 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
895 };
896
897 uart0_rts_gpio: uart0-rts-gpio {
898 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
899 };
900 };
901
902 uart1 {
903 uart1_xfer: uart1-xfer {
904 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
905 <1 RK_PD2 1 &pcfg_pull_none>;
906 };
907
908 uart1_cts: uart1-cts {
909 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
910 };
911
912 uart1_rts: uart1-rts {
913 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
914 };
915 };
916
917 uart2m0 {
918 uart2m0_xfer: uart2m0-xfer {
919 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
920 <2 RK_PD1 1 &pcfg_pull_none>;
921 };
922 };
923
924 uart2m1 {
925 uart2m1_xfer: uart2m1-xfer {
926 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
927 <3 RK_PC2 2 &pcfg_pull_none>;
928 };
929 };
930
931 uart2_5v {
932 uart2_5v_cts: uart2_5v-cts {
933 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
934 };
935
936 uart2_5v_rts: uart2_5v-rts {
937 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
938 };
939 };
940 };
941};