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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mfd/qcom-rpm.h>
6#include <dt-bindings/clock/qcom,rpmcc.h>
7#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11#include <dt-bindings/soc/qcom,gsbi.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc0>;
32 qcom,saw = <&saw0>;
33 };
34
35 cpu1: cpu@1 {
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v1";
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L2>;
41 qcom,acc = <&acc1>;
42 qcom,saw = <&saw1>;
43 };
44
45 L2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 };
49 };
50
51 thermal-zones {
52 sensor0-thermal {
53 polling-delay-passive = <0>;
54 polling-delay = <0>;
55 thermal-sensors = <&tsens 0>;
56
57 trips {
58 cpu-critical {
59 temperature = <105000>;
60 hysteresis = <2000>;
61 type = "critical";
62 };
63
64 cpu-hot {
65 temperature = <95000>;
66 hysteresis = <2000>;
67 type = "hot";
68 };
69 };
70 };
71
72 sensor1-thermal {
73 polling-delay-passive = <0>;
74 polling-delay = <0>;
75 thermal-sensors = <&tsens 1>;
76
77 trips {
78 cpu-critical {
79 temperature = <105000>;
80 hysteresis = <2000>;
81 type = "critical";
82 };
83
84 cpu-hot {
85 temperature = <95000>;
86 hysteresis = <2000>;
87 type = "hot";
88 };
89 };
90 };
91
92 sensor2-thermal {
93 polling-delay-passive = <0>;
94 polling-delay = <0>;
95 thermal-sensors = <&tsens 2>;
96
97 trips {
98 cpu-critical {
99 temperature = <105000>;
100 hysteresis = <2000>;
101 type = "critical";
102 };
103
104 cpu-hot {
105 temperature = <95000>;
106 hysteresis = <2000>;
107 type = "hot";
108 };
109 };
110 };
111
112 sensor3-thermal {
113 polling-delay-passive = <0>;
114 polling-delay = <0>;
115 thermal-sensors = <&tsens 3>;
116
117 trips {
118 cpu-critical {
119 temperature = <105000>;
120 hysteresis = <2000>;
121 type = "critical";
122 };
123
124 cpu-hot {
125 temperature = <95000>;
126 hysteresis = <2000>;
127 type = "hot";
128 };
129 };
130 };
131
132 sensor4-thermal {
133 polling-delay-passive = <0>;
134 polling-delay = <0>;
135 thermal-sensors = <&tsens 4>;
136
137 trips {
138 cpu-critical {
139 temperature = <105000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143
144 cpu-hot {
145 temperature = <95000>;
146 hysteresis = <2000>;
147 type = "hot";
148 };
149 };
150 };
151
152 sensor5-thermal {
153 polling-delay-passive = <0>;
154 polling-delay = <0>;
155 thermal-sensors = <&tsens 5>;
156
157 trips {
158 cpu-critical {
159 temperature = <105000>;
160 hysteresis = <2000>;
161 type = "critical";
162 };
163
164 cpu-hot {
165 temperature = <95000>;
166 hysteresis = <2000>;
167 type = "hot";
168 };
169 };
170 };
171
172 sensor6-thermal {
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
175 thermal-sensors = <&tsens 6>;
176
177 trips {
178 cpu-critical {
179 temperature = <105000>;
180 hysteresis = <2000>;
181 type = "critical";
182 };
183
184 cpu-hot {
185 temperature = <95000>;
186 hysteresis = <2000>;
187 type = "hot";
188 };
189 };
190 };
191
192 sensor7-thermal {
193 polling-delay-passive = <0>;
194 polling-delay = <0>;
195 thermal-sensors = <&tsens 7>;
196
197 trips {
198 cpu-critical {
199 temperature = <105000>;
200 hysteresis = <2000>;
201 type = "critical";
202 };
203
204 cpu-hot {
205 temperature = <95000>;
206 hysteresis = <2000>;
207 type = "hot";
208 };
209 };
210 };
211
212 sensor8-thermal {
213 polling-delay-passive = <0>;
214 polling-delay = <0>;
215 thermal-sensors = <&tsens 8>;
216
217 trips {
218 cpu-critical {
219 temperature = <105000>;
220 hysteresis = <2000>;
221 type = "critical";
222 };
223
224 cpu-hot {
225 temperature = <95000>;
226 hysteresis = <2000>;
227 type = "hot";
228 };
229 };
230 };
231
232 sensor9-thermal {
233 polling-delay-passive = <0>;
234 polling-delay = <0>;
235 thermal-sensors = <&tsens 9>;
236
237 trips {
238 cpu-critical {
239 temperature = <105000>;
240 hysteresis = <2000>;
241 type = "critical";
242 };
243
244 cpu-hot {
245 temperature = <95000>;
246 hysteresis = <2000>;
247 type = "hot";
248 };
249 };
250 };
251
252 sensor10-thermal {
253 polling-delay-passive = <0>;
254 polling-delay = <0>;
255 thermal-sensors = <&tsens 10>;
256
257 trips {
258 cpu-critical {
259 temperature = <105000>;
260 hysteresis = <2000>;
261 type = "critical";
262 };
263
264 cpu-hot {
265 temperature = <95000>;
266 hysteresis = <2000>;
267 type = "hot";
268 };
269 };
270 };
271 };
272
273 memory {
274 device_type = "memory";
275 reg = <0x0 0x0>;
276 };
277
278 cpu-pmu {
279 compatible = "qcom,krait-pmu";
280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
281 IRQ_TYPE_LEVEL_HIGH)>;
282 };
283
284 reserved-memory {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 ranges;
288
289 nss@40000000 {
290 reg = <0x40000000 0x1000000>;
291 no-map;
292 };
293
294 smem: smem@41000000 {
295 compatible = "qcom,smem";
296 reg = <0x41000000 0x200000>;
297 no-map;
298
299 hwlocks = <&sfpb_mutex 3>;
300 };
301 };
302
303 clocks {
304 cxo_board: cxo_board {
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <25000000>;
308 };
309
310 pxo_board: pxo_board {
311 compatible = "fixed-clock";
312 #clock-cells = <0>;
313 clock-frequency = <25000000>;
314 };
315
316 sleep_clk: sleep_clk {
317 compatible = "fixed-clock";
318 clock-frequency = <32768>;
319 #clock-cells = <0>;
320 };
321 };
322
323 firmware {
324 scm {
325 compatible = "qcom,scm-ipq806x", "qcom,scm";
326 };
327 };
328
329 soc: soc {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 ranges;
333 compatible = "simple-bus";
334
335 stmmac_axi_setup: stmmac-axi-config {
336 snps,wr_osr_lmt = <7>;
337 snps,rd_osr_lmt = <7>;
338 snps,blen = <16 0 0 0 0 0 0>;
339 };
340
341 vsdcc_fixed: vsdcc-regulator {
342 compatible = "regulator-fixed";
343 regulator-name = "SDCC Power";
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
346 regulator-always-on;
347 };
348
349 rpm: rpm@108000 {
350 compatible = "qcom,rpm-ipq8064";
351 reg = <0x00108000 0x1000>;
352 qcom,ipc = <&l2cc 0x8 2>;
353
354 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
357 interrupt-names = "ack", "err", "wakeup";
358
359 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
360 clock-names = "ram";
361
362 rpmcc: clock-controller {
363 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
364 #clock-cells = <1>;
365 };
366 };
367
368 qcom,ssbi@500000 {
369 compatible = "qcom,ssbi";
370 reg = <0x00500000 0x1000>;
371 qcom,controller-type = "pmic-arbiter";
372 };
373
374 qfprom: qfprom@700000 {
375 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
376 reg = <0x00700000 0x1000>;
377 #address-cells = <1>;
378 #size-cells = <1>;
379 speedbin_efuse: speedbin@c0 {
380 reg = <0xc0 0x4>;
381 };
382 tsens_calib: calib@400 {
383 reg = <0x400 0xb>;
384 };
385 tsens_calib_backup: calib_backup@410 {
386 reg = <0x410 0xb>;
387 };
388 };
389
390 qcom_pinmux: pinmux@800000 {
391 compatible = "qcom,ipq8064-pinctrl";
392 reg = <0x00800000 0x4000>;
393
394 gpio-controller;
395 gpio-ranges = <&qcom_pinmux 0 0 69>;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
400
401 pcie0_pins: pcie0_pinmux {
402 mux {
403 pins = "gpio3";
404 function = "pcie1_rst";
405 drive-strength = <12>;
406 bias-disable;
407 };
408 };
409
410 pcie1_pins: pcie1_pinmux {
411 mux {
412 pins = "gpio48";
413 function = "pcie2_rst";
414 drive-strength = <12>;
415 bias-disable;
416 };
417 };
418
419 pcie2_pins: pcie2_pinmux {
420 mux {
421 pins = "gpio63";
422 function = "pcie3_rst";
423 drive-strength = <12>;
424 bias-disable;
425 };
426 };
427
428 i2c4_pins: i2c4-default {
429 pins = "gpio12", "gpio13";
430 function = "gsbi4";
431 drive-strength = <12>;
432 bias-disable;
433 };
434
435 spi_pins: spi_pins {
436 mux {
437 pins = "gpio18", "gpio19", "gpio21";
438 function = "gsbi5";
439 drive-strength = <10>;
440 bias-none;
441 };
442 };
443
444 leds_pins: leds_pins {
445 mux {
446 pins = "gpio7", "gpio8", "gpio9",
447 "gpio26", "gpio53";
448 function = "gpio";
449 drive-strength = <2>;
450 bias-pull-down;
451 output-low;
452 };
453 };
454
455 buttons_pins: buttons_pins {
456 mux {
457 pins = "gpio54";
458 drive-strength = <2>;
459 bias-pull-up;
460 };
461 };
462
463 nand_pins: nand_pins {
464 mux {
465 pins = "gpio34", "gpio35", "gpio36",
466 "gpio37", "gpio38", "gpio39",
467 "gpio40", "gpio41", "gpio42",
468 "gpio43", "gpio44", "gpio45",
469 "gpio46", "gpio47";
470 function = "nand";
471 drive-strength = <10>;
472 bias-disable;
473 };
474
475 pullups {
476 pins = "gpio39";
477 function = "nand";
478 drive-strength = <10>;
479 bias-pull-up;
480 };
481
482 hold {
483 pins = "gpio40", "gpio41", "gpio42",
484 "gpio43", "gpio44", "gpio45",
485 "gpio46", "gpio47";
486 function = "nand";
487 drive-strength = <10>;
488 bias-bus-hold;
489 };
490 };
491
492 mdio0_pins: mdio0-pins {
493 mux {
494 pins = "gpio0", "gpio1";
495 function = "mdio";
496 drive-strength = <8>;
497 bias-disable;
498 };
499 };
500
501 rgmii2_pins: rgmii2-pins {
502 mux {
503 pins = "gpio27", "gpio28", "gpio29",
504 "gpio30", "gpio31", "gpio32",
505 "gpio51", "gpio52", "gpio59",
506 "gpio60", "gpio61", "gpio62";
507 function = "rgmii2";
508 drive-strength = <8>;
509 bias-disable;
510 };
511 };
512 };
513
514 gcc: clock-controller@900000 {
515 compatible = "qcom,gcc-ipq8064", "syscon";
516 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
517 clock-names = "pxo", "cxo", "pll4";
518 reg = <0x00900000 0x4000>;
519 #clock-cells = <1>;
520 #reset-cells = <1>;
521 #power-domain-cells = <1>;
522
523 tsens: thermal-sensor@900000 {
524 compatible = "qcom,ipq8064-tsens";
525
526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
527 nvmem-cell-names = "calib", "calib_backup";
528 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
529 interrupt-names = "uplow";
530
531 #qcom,sensors = <11>;
532 #thermal-sensor-cells = <1>;
533 };
534 };
535
536 sfpb_mutex: hwlock@1200600 {
537 compatible = "qcom,sfpb-mutex";
538 reg = <0x01200600 0x100>;
539
540 #hwlock-cells = <1>;
541 };
542
543 intc: interrupt-controller@2000000 {
544 compatible = "qcom,msm-qgic2";
545 interrupt-controller;
546 #interrupt-cells = <3>;
547 reg = <0x02000000 0x1000>,
548 <0x02002000 0x1000>;
549 };
550
551 timer@200a000 {
552 compatible = "qcom,kpss-timer",
553 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
554 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
555 IRQ_TYPE_EDGE_RISING)>,
556 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
557 IRQ_TYPE_EDGE_RISING)>,
558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
559 IRQ_TYPE_EDGE_RISING)>,
560 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
561 IRQ_TYPE_EDGE_RISING)>,
562 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
563 IRQ_TYPE_EDGE_RISING)>;
564 reg = <0x0200a000 0x100>;
565 clock-frequency = <25000000>,
566 <32768>;
567 clocks = <&sleep_clk>;
568 clock-names = "sleep";
569 cpu-offset = <0x80000>;
570 };
571
572 l2cc: clock-controller@2011000 {
573 compatible = "qcom,kpss-gcc", "syscon";
574 reg = <0x02011000 0x1000>;
575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
576 clock-names = "pll8_vote", "pxo";
577 clock-output-names = "acpu_l2_aux";
578 };
579
580 acc0: clock-controller@2088000 {
581 compatible = "qcom,kpss-acc-v1";
582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
583 };
584
585 saw0: regulator@2089000 {
586 compatible = "qcom,saw2";
587 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
588 regulator;
589 };
590
591 acc1: clock-controller@2098000 {
592 compatible = "qcom,kpss-acc-v1";
593 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
594 };
595
596 saw1: regulator@2099000 {
597 compatible = "qcom,saw2";
598 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
599 regulator;
600 };
601
602 nss_common: syscon@03000000 {
603 compatible = "syscon";
604 reg = <0x03000000 0x0000FFFF>;
605 };
606
607 usb3_0: usb3@100f8800 {
608 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 reg = <0x100f8800 0x8000>;
612 clocks = <&gcc USB30_0_MASTER_CLK>;
613 clock-names = "core";
614
615 ranges;
616
617 resets = <&gcc USB30_0_MASTER_RESET>;
618 reset-names = "master";
619
620 status = "disabled";
621
622 dwc3_0: dwc3@10000000 {
623 compatible = "snps,dwc3";
624 reg = <0x10000000 0xcd00>;
625 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
626 phys = <&hs_phy_0>, <&ss_phy_0>;
627 phy-names = "usb2-phy", "usb3-phy";
628 dr_mode = "host";
629 snps,dis_u3_susphy_quirk;
630 };
631 };
632
633 hs_phy_0: phy@100f8800 {
634 compatible = "qcom,ipq806x-usb-phy-hs";
635 reg = <0x100f8800 0x30>;
636 clocks = <&gcc USB30_0_UTMI_CLK>;
637 clock-names = "ref";
638 #phy-cells = <0>;
639
640 status = "disabled";
641 };
642
643 ss_phy_0: phy@100f8830 {
644 compatible = "qcom,ipq806x-usb-phy-ss";
645 reg = <0x100f8830 0x30>;
646 clocks = <&gcc USB30_0_MASTER_CLK>;
647 clock-names = "ref";
648 #phy-cells = <0>;
649
650 status = "disabled";
651 };
652
653 usb3_1: usb3@110f8800 {
654 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
655 #address-cells = <1>;
656 #size-cells = <1>;
657 reg = <0x110f8800 0x8000>;
658 clocks = <&gcc USB30_1_MASTER_CLK>;
659 clock-names = "core";
660
661 ranges;
662
663 resets = <&gcc USB30_1_MASTER_RESET>;
664 reset-names = "master";
665
666 status = "disabled";
667
668 dwc3_1: dwc3@11000000 {
669 compatible = "snps,dwc3";
670 reg = <0x11000000 0xcd00>;
671 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
672 phys = <&hs_phy_1>, <&ss_phy_1>;
673 phy-names = "usb2-phy", "usb3-phy";
674 dr_mode = "host";
675 snps,dis_u3_susphy_quirk;
676 };
677 };
678
679 hs_phy_1: phy@110f8800 {
680 compatible = "qcom,ipq806x-usb-phy-hs";
681 reg = <0x110f8800 0x30>;
682 clocks = <&gcc USB30_1_UTMI_CLK>;
683 clock-names = "ref";
684 #phy-cells = <0>;
685
686 status = "disabled";
687 };
688
689 ss_phy_1: phy@110f8830 {
690 compatible = "qcom,ipq806x-usb-phy-ss";
691 reg = <0x110f8830 0x30>;
692 clocks = <&gcc USB30_1_MASTER_CLK>;
693 clock-names = "ref";
694 #phy-cells = <0>;
695
696 status = "disabled";
697 };
698
699 sdcc3bam: dma-controller@12182000 {
700 compatible = "qcom,bam-v1.3.0";
701 reg = <0x12182000 0x8000>;
702 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&gcc SDC3_H_CLK>;
704 clock-names = "bam_clk";
705 #dma-cells = <1>;
706 qcom,ee = <0>;
707 };
708
709 sdcc1bam: dma-controller@12402000 {
710 compatible = "qcom,bam-v1.3.0";
711 reg = <0x12402000 0x8000>;
712 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&gcc SDC1_H_CLK>;
714 clock-names = "bam_clk";
715 #dma-cells = <1>;
716 qcom,ee = <0>;
717 };
718
719 amba: amba {
720 compatible = "simple-bus";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 ranges;
724
725 sdcc3: mmc@12180000 {
726 compatible = "arm,pl18x", "arm,primecell";
727 arm,primecell-periphid = <0x00051180>;
728 status = "disabled";
729 reg = <0x12180000 0x2000>;
730 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
732 clock-names = "mclk", "apb_pclk";
733 bus-width = <8>;
734 cap-sd-highspeed;
735 cap-mmc-highspeed;
736 max-frequency = <192000000>;
737 sd-uhs-sdr104;
738 sd-uhs-ddr50;
739 vqmmc-supply = <&vsdcc_fixed>;
740 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
741 dma-names = "tx", "rx";
742 };
743
744 sdcc1: mmc@12400000 {
745 status = "disabled";
746 compatible = "arm,pl18x", "arm,primecell";
747 arm,primecell-periphid = <0x00051180>;
748 reg = <0x12400000 0x2000>;
749 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
751 clock-names = "mclk", "apb_pclk";
752 bus-width = <8>;
753 max-frequency = <96000000>;
754 non-removable;
755 cap-sd-highspeed;
756 cap-mmc-highspeed;
757 vmmc-supply = <&vsdcc_fixed>;
758 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
759 dma-names = "tx", "rx";
760 };
761 };
762
763 gsbi1: gsbi@12440000 {
764 compatible = "qcom,gsbi-v1.0.0";
765 reg = <0x12440000 0x100>;
766 cell-index = <1>;
767 clocks = <&gcc GSBI1_H_CLK>;
768 clock-names = "iface";
769 #address-cells = <1>;
770 #size-cells = <1>;
771 ranges;
772
773 syscon-tcsr = <&tcsr>;
774
775 status = "disabled";
776
777 gsbi1_serial: serial@12450000 {
778 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
779 reg = <0x12450000 0x100>,
780 <0x12400000 0x03>;
781 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
783 clock-names = "core", "iface";
784
785 status = "disabled";
786 };
787
788 gsbi1_i2c: i2c@12460000 {
789 compatible = "qcom,i2c-qup-v1.1.1";
790 reg = <0x12460000 0x1000>;
791 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
793 clock-names = "core", "iface";
794 #address-cells = <1>;
795 #size-cells = <0>;
796
797 status = "disabled";
798 };
799 };
800
801 gsbi2: gsbi@12480000 {
802 compatible = "qcom,gsbi-v1.0.0";
803 cell-index = <2>;
804 reg = <0x12480000 0x100>;
805 clocks = <&gcc GSBI2_H_CLK>;
806 clock-names = "iface";
807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges;
810 status = "disabled";
811
812 syscon-tcsr = <&tcsr>;
813
814 gsbi2_serial: serial@12490000 {
815 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
816 reg = <0x12490000 0x1000>,
817 <0x12480000 0x1000>;
818 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
820 clock-names = "core", "iface";
821 status = "disabled";
822 };
823
824 gsbi2_i2c: i2c@124a0000 {
825 compatible = "qcom,i2c-qup-v1.1.1";
826 reg = <0x124a0000 0x1000>;
827 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
828
829 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
830 clock-names = "core", "iface";
831 status = "disabled";
832
833 #address-cells = <1>;
834 #size-cells = <0>;
835 };
836 };
837
838 gsbi4: gsbi@16300000 {
839 compatible = "qcom,gsbi-v1.0.0";
840 cell-index = <4>;
841 reg = <0x16300000 0x100>;
842 clocks = <&gcc GSBI4_H_CLK>;
843 clock-names = "iface";
844 #address-cells = <1>;
845 #size-cells = <1>;
846 ranges;
847 status = "disabled";
848
849 syscon-tcsr = <&tcsr>;
850
851 gsbi4_serial: serial@16340000 {
852 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
853 reg = <0x16340000 0x1000>,
854 <0x16300000 0x1000>;
855 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
857 clock-names = "core", "iface";
858 status = "disabled";
859 };
860
861 i2c@16380000 {
862 compatible = "qcom,i2c-qup-v1.1.1";
863 reg = <0x16380000 0x1000>;
864 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
865
866 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
867 clock-names = "core", "iface";
868 status = "disabled";
869
870 #address-cells = <1>;
871 #size-cells = <0>;
872 };
873 };
874
875 gsbi6: gsbi@16500000 {
876 compatible = "qcom,gsbi-v1.0.0";
877 reg = <0x16500000 0x100>;
878 cell-index = <6>;
879 clocks = <&gcc GSBI6_H_CLK>;
880 clock-names = "iface";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 ranges;
884
885 syscon-tcsr = <&tcsr>;
886
887 status = "disabled";
888
889 gsbi6_i2c: i2c@16580000 {
890 compatible = "qcom,i2c-qup-v1.1.1";
891 reg = <0x16580000 0x1000>;
892 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
893
894 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
895 clock-names = "core", "iface";
896
897 #address-cells = <1>;
898 #size-cells = <0>;
899
900 status = "disabled";
901 };
902
903 gsbi6_spi: spi@16580000 {
904 compatible = "qcom,spi-qup-v1.1.1";
905 reg = <0x16580000 0x1000>;
906 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
907
908 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
909 clock-names = "core", "iface";
910
911 #address-cells = <1>;
912 #size-cells = <0>;
913
914 status = "disabled";
915 };
916 };
917
918 gsbi7: gsbi@16600000 {
919 status = "disabled";
920 compatible = "qcom,gsbi-v1.0.0";
921 cell-index = <7>;
922 reg = <0x16600000 0x100>;
923 clocks = <&gcc GSBI7_H_CLK>;
924 clock-names = "iface";
925 #address-cells = <1>;
926 #size-cells = <1>;
927 ranges;
928 syscon-tcsr = <&tcsr>;
929
930 gsbi7_serial: serial@16640000 {
931 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
932 reg = <0x16640000 0x1000>,
933 <0x16600000 0x1000>;
934 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
936 clock-names = "core", "iface";
937 status = "disabled";
938 };
939
940 gsbi7_i2c: i2c@16680000 {
941 compatible = "qcom,i2c-qup-v1.1.1";
942 reg = <0x16680000 0x1000>;
943 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
944
945 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
946 clock-names = "core", "iface";
947
948 #address-cells = <1>;
949 #size-cells = <0>;
950
951 status = "disabled";
952 };
953 };
954
955 adm_dma: dma-controller@18300000 {
956 compatible = "qcom,adm";
957 reg = <0x18300000 0x100000>;
958 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
959 #dma-cells = <1>;
960
961 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
962 clock-names = "core", "iface";
963
964 resets = <&gcc ADM0_RESET>,
965 <&gcc ADM0_PBUS_RESET>,
966 <&gcc ADM0_C0_RESET>,
967 <&gcc ADM0_C1_RESET>,
968 <&gcc ADM0_C2_RESET>;
969 reset-names = "clk", "pbus", "c0", "c1", "c2";
970 qcom,ee = <0>;
971
972 status = "disabled";
973 };
974
975 gsbi5: gsbi@1a200000 {
976 compatible = "qcom,gsbi-v1.0.0";
977 cell-index = <5>;
978 reg = <0x1a200000 0x100>;
979 clocks = <&gcc GSBI5_H_CLK>;
980 clock-names = "iface";
981 #address-cells = <1>;
982
983 #size-cells = <1>;
984 ranges;
985 status = "disabled";
986
987 syscon-tcsr = <&tcsr>;
988
989 gsbi5_serial: serial@1a240000 {
990 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
991 reg = <0x1a240000 0x1000>,
992 <0x1a200000 0x1000>;
993 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
995 clock-names = "core", "iface";
996 status = "disabled";
997 };
998
999 i2c@1a280000 {
1000 compatible = "qcom,i2c-qup-v1.1.1";
1001 reg = <0x1a280000 0x1000>;
1002 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1003
1004 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1005 clock-names = "core", "iface";
1006 status = "disabled";
1007
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010 };
1011
1012 spi@1a280000 {
1013 compatible = "qcom,spi-qup-v1.1.1";
1014 reg = <0x1a280000 0x1000>;
1015 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1016
1017 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1018 clock-names = "core", "iface";
1019 status = "disabled";
1020
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024 };
1025
1026 tcsr: syscon@1a400000 {
1027 compatible = "qcom,tcsr-ipq8064", "syscon";
1028 reg = <0x1a400000 0x100>;
1029 };
1030
1031 rng@1a500000 {
1032 compatible = "qcom,prng";
1033 reg = <0x1a500000 0x200>;
1034 clocks = <&gcc PRNG_CLK>;
1035 clock-names = "core";
1036 };
1037
1038 nand: nand-controller@1ac00000 {
1039 compatible = "qcom,ipq806x-nand";
1040 reg = <0x1ac00000 0x800>;
1041
1042 pinctrl-0 = <&nand_pins>;
1043 pinctrl-names = "default";
1044
1045 clocks = <&gcc EBI2_CLK>,
1046 <&gcc EBI2_AON_CLK>;
1047 clock-names = "core", "aon";
1048
1049 dmas = <&adm_dma 3>;
1050 dma-names = "rxtx";
1051 qcom,cmd-crci = <15>;
1052 qcom,data-crci = <3>;
1053
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056
1057 status = "disabled";
1058 };
1059
1060 sata_phy: sata-phy@1b400000 {
1061 compatible = "qcom,ipq806x-sata-phy";
1062 reg = <0x1b400000 0x200>;
1063
1064 clocks = <&gcc SATA_PHY_CFG_CLK>;
1065 clock-names = "cfg";
1066
1067 #phy-cells = <0>;
1068 status = "disabled";
1069 };
1070
1071 pcie0: pci@1b500000 {
1072 compatible = "qcom,pcie-ipq8064";
1073 reg = <0x1b500000 0x1000
1074 0x1b502000 0x80
1075 0x1b600000 0x100
1076 0x0ff00000 0x100000>;
1077 reg-names = "dbi", "elbi", "parf", "config";
1078 device_type = "pci";
1079 linux,pci-domain = <0>;
1080 bus-range = <0x00 0xff>;
1081 num-lanes = <1>;
1082 #address-cells = <3>;
1083 #size-cells = <2>;
1084
1085 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
1086 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1087
1088 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1089 interrupt-names = "msi";
1090 #interrupt-cells = <1>;
1091 interrupt-map-mask = <0 0 0 0x7>;
1092 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1093 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1094 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1095 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1096
1097 clocks = <&gcc PCIE_A_CLK>,
1098 <&gcc PCIE_H_CLK>,
1099 <&gcc PCIE_PHY_CLK>,
1100 <&gcc PCIE_AUX_CLK>,
1101 <&gcc PCIE_ALT_REF_CLK>;
1102 clock-names = "core", "iface", "phy", "aux", "ref";
1103
1104 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1105 assigned-clock-rates = <100000000>;
1106
1107 resets = <&gcc PCIE_ACLK_RESET>,
1108 <&gcc PCIE_HCLK_RESET>,
1109 <&gcc PCIE_POR_RESET>,
1110 <&gcc PCIE_PCI_RESET>,
1111 <&gcc PCIE_PHY_RESET>,
1112 <&gcc PCIE_EXT_RESET>;
1113 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1114
1115 pinctrl-0 = <&pcie0_pins>;
1116 pinctrl-names = "default";
1117
1118 status = "disabled";
1119 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1120 };
1121
1122 pcie1: pci@1b700000 {
1123 compatible = "qcom,pcie-ipq8064";
1124 reg = <0x1b700000 0x1000
1125 0x1b702000 0x80
1126 0x1b800000 0x100
1127 0x31f00000 0x100000>;
1128 reg-names = "dbi", "elbi", "parf", "config";
1129 device_type = "pci";
1130 linux,pci-domain = <1>;
1131 bus-range = <0x00 0xff>;
1132 num-lanes = <1>;
1133 #address-cells = <3>;
1134 #size-cells = <2>;
1135
1136 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
1137 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1138
1139 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-names = "msi";
1141 #interrupt-cells = <1>;
1142 interrupt-map-mask = <0 0 0 0x7>;
1143 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1144 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1145 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1146 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1147
1148 clocks = <&gcc PCIE_1_A_CLK>,
1149 <&gcc PCIE_1_H_CLK>,
1150 <&gcc PCIE_1_PHY_CLK>,
1151 <&gcc PCIE_1_AUX_CLK>,
1152 <&gcc PCIE_1_ALT_REF_CLK>;
1153 clock-names = "core", "iface", "phy", "aux", "ref";
1154
1155 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1156 assigned-clock-rates = <100000000>;
1157
1158 resets = <&gcc PCIE_1_ACLK_RESET>,
1159 <&gcc PCIE_1_HCLK_RESET>,
1160 <&gcc PCIE_1_POR_RESET>,
1161 <&gcc PCIE_1_PCI_RESET>,
1162 <&gcc PCIE_1_PHY_RESET>,
1163 <&gcc PCIE_1_EXT_RESET>;
1164 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1165
1166 pinctrl-0 = <&pcie1_pins>;
1167 pinctrl-names = "default";
1168
1169 status = "disabled";
1170 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1171 };
1172
1173 pcie2: pci@1b900000 {
1174 compatible = "qcom,pcie-ipq8064";
1175 reg = <0x1b900000 0x1000
1176 0x1b902000 0x80
1177 0x1ba00000 0x100
1178 0x35f00000 0x100000>;
1179 reg-names = "dbi", "elbi", "parf", "config";
1180 device_type = "pci";
1181 linux,pci-domain = <2>;
1182 bus-range = <0x00 0xff>;
1183 num-lanes = <1>;
1184 #address-cells = <3>;
1185 #size-cells = <2>;
1186
1187 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
1188 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1189
1190 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1191 interrupt-names = "msi";
1192 #interrupt-cells = <1>;
1193 interrupt-map-mask = <0 0 0 0x7>;
1194 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1195 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1196 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1197 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1198
1199 clocks = <&gcc PCIE_2_A_CLK>,
1200 <&gcc PCIE_2_H_CLK>,
1201 <&gcc PCIE_2_PHY_CLK>,
1202 <&gcc PCIE_2_AUX_CLK>,
1203 <&gcc PCIE_2_ALT_REF_CLK>;
1204 clock-names = "core", "iface", "phy", "aux", "ref";
1205
1206 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1207 assigned-clock-rates = <100000000>;
1208
1209 resets = <&gcc PCIE_2_ACLK_RESET>,
1210 <&gcc PCIE_2_HCLK_RESET>,
1211 <&gcc PCIE_2_POR_RESET>,
1212 <&gcc PCIE_2_PCI_RESET>,
1213 <&gcc PCIE_2_PHY_RESET>,
1214 <&gcc PCIE_2_EXT_RESET>;
1215 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1216
1217 pinctrl-0 = <&pcie2_pins>;
1218 pinctrl-names = "default";
1219
1220 status = "disabled";
1221 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1222 };
1223
1224 qsgmii_csr: syscon@1bb00000 {
1225 compatible = "syscon";
1226 reg = <0x1bb00000 0x000001FF>;
1227 };
1228
1229 lcc: clock-controller@28000000 {
1230 compatible = "qcom,lcc-ipq8064";
1231 reg = <0x28000000 0x1000>;
1232 #clock-cells = <1>;
1233 #reset-cells = <1>;
1234 };
1235
1236 lpass@28100000 {
1237 compatible = "qcom,lpass-cpu";
1238 status = "disabled";
1239 clocks = <&lcc AHBIX_CLK>,
1240 <&lcc MI2S_OSR_CLK>,
1241 <&lcc MI2S_BIT_CLK>;
1242 clock-names = "ahbix-clk",
1243 "mi2s-osr-clk",
1244 "mi2s-bit-clk";
1245 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1246 interrupt-names = "lpass-irq-lpaif";
1247 reg = <0x28100000 0x10000>;
1248 reg-names = "lpass-lpaif";
1249 };
1250
1251 sata: sata@29000000 {
1252 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1253 reg = <0x29000000 0x180>;
1254
1255 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1256
1257 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1258 <&gcc SATA_H_CLK>,
1259 <&gcc SATA_A_CLK>,
1260 <&gcc SATA_RXOOB_CLK>,
1261 <&gcc SATA_PMALIVE_CLK>;
1262 clock-names = "slave_face", "iface", "core",
1263 "rxoob", "pmalive";
1264
1265 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1266 assigned-clock-rates = <100000000>, <100000000>;
1267
1268 phys = <&sata_phy>;
1269 phy-names = "sata-phy";
1270 status = "disabled";
1271 };
1272
1273 gmac0: ethernet@37000000 {
1274 device_type = "network";
1275 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1276 reg = <0x37000000 0x200000>;
1277 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1278 interrupt-names = "macirq";
1279
1280 snps,axi-config = <&stmmac_axi_setup>;
1281 snps,pbl = <32>;
1282 snps,aal;
1283
1284 qcom,nss-common = <&nss_common>;
1285 qcom,qsgmii-csr = <&qsgmii_csr>;
1286
1287 clocks = <&gcc GMAC_CORE1_CLK>;
1288 clock-names = "stmmaceth";
1289
1290 resets = <&gcc GMAC_CORE1_RESET>,
1291 <&gcc GMAC_AHB_RESET>;
1292 reset-names = "stmmaceth", "ahb";
1293
1294 status = "disabled";
1295 };
1296
1297 gmac1: ethernet@37200000 {
1298 device_type = "network";
1299 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1300 reg = <0x37200000 0x200000>;
1301 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1302 interrupt-names = "macirq";
1303
1304 snps,axi-config = <&stmmac_axi_setup>;
1305 snps,pbl = <32>;
1306 snps,aal;
1307
1308 qcom,nss-common = <&nss_common>;
1309 qcom,qsgmii-csr = <&qsgmii_csr>;
1310
1311 clocks = <&gcc GMAC_CORE2_CLK>;
1312 clock-names = "stmmaceth";
1313
1314 resets = <&gcc GMAC_CORE2_RESET>,
1315 <&gcc GMAC_AHB_RESET>;
1316 reset-names = "stmmaceth", "ahb";
1317
1318 status = "disabled";
1319 };
1320
1321 gmac2: ethernet@37400000 {
1322 device_type = "network";
1323 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1324 reg = <0x37400000 0x200000>;
1325 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1326 interrupt-names = "macirq";
1327
1328 snps,axi-config = <&stmmac_axi_setup>;
1329 snps,pbl = <32>;
1330 snps,aal;
1331
1332 qcom,nss-common = <&nss_common>;
1333 qcom,qsgmii-csr = <&qsgmii_csr>;
1334
1335 clocks = <&gcc GMAC_CORE3_CLK>;
1336 clock-names = "stmmaceth";
1337
1338 resets = <&gcc GMAC_CORE3_RESET>,
1339 <&gcc GMAC_AHB_RESET>;
1340 reset-names = "stmmaceth", "ahb";
1341
1342 status = "disabled";
1343 };
1344
1345 gmac3: ethernet@37600000 {
1346 device_type = "network";
1347 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1348 reg = <0x37600000 0x200000>;
1349 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "macirq";
1351
1352 snps,axi-config = <&stmmac_axi_setup>;
1353 snps,pbl = <32>;
1354 snps,aal;
1355
1356 qcom,nss-common = <&nss_common>;
1357 qcom,qsgmii-csr = <&qsgmii_csr>;
1358
1359 clocks = <&gcc GMAC_CORE4_CLK>;
1360 clock-names = "stmmaceth";
1361
1362 resets = <&gcc GMAC_CORE4_RESET>,
1363 <&gcc GMAC_AHB_RESET>;
1364 reset-names = "stmmaceth", "ahb";
1365
1366 status = "disabled";
1367 };
1368 };
1369};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm IPQ8064";
16 compatible = "qcom,ipq8064";
17 interrupt-parent = <&intc>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "qcom,krait";
25 enable-method = "qcom,kpss-acc-v1";
26 device_type = "cpu";
27 reg = <0>;
28 next-level-cache = <&L2>;
29 qcom,acc = <&acc0>;
30 qcom,saw = <&saw0>;
31 };
32
33 cpu@1 {
34 compatible = "qcom,krait";
35 enable-method = "qcom,kpss-acc-v1";
36 device_type = "cpu";
37 reg = <1>;
38 next-level-cache = <&L2>;
39 qcom,acc = <&acc1>;
40 qcom,saw = <&saw1>;
41 };
42
43 L2: l2-cache {
44 compatible = "cache";
45 cache-level = <2>;
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x0 0x0>;
52 };
53
54 cpu-pmu {
55 compatible = "qcom,krait-pmu";
56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
57 IRQ_TYPE_LEVEL_HIGH)>;
58 };
59
60 reserved-memory {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 nss@40000000 {
66 reg = <0x40000000 0x1000000>;
67 no-map;
68 };
69
70 smem@41000000 {
71 reg = <0x41000000 0x200000>;
72 no-map;
73 };
74 };
75
76 clocks {
77 cxo_board {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <25000000>;
81 };
82
83 pxo_board {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <25000000>;
87 };
88
89 sleep_clk: sleep_clk {
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 #clock-cells = <0>;
93 };
94 };
95
96 soc: soc {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100 compatible = "simple-bus";
101
102 lpass@28100000 {
103 compatible = "qcom,lpass-cpu";
104 status = "disabled";
105 clocks = <&lcc AHBIX_CLK>,
106 <&lcc MI2S_OSR_CLK>,
107 <&lcc MI2S_BIT_CLK>;
108 clock-names = "ahbix-clk",
109 "mi2s-osr-clk",
110 "mi2s-bit-clk";
111 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
112 interrupt-names = "lpass-irq-lpaif";
113 reg = <0x28100000 0x10000>;
114 reg-names = "lpass-lpaif";
115 };
116
117 qcom_pinmux: pinmux@800000 {
118 compatible = "qcom,ipq8064-pinctrl";
119 reg = <0x800000 0x4000>;
120
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
126
127 pcie0_pins: pcie0_pinmux {
128 mux {
129 pins = "gpio3";
130 function = "pcie1_rst";
131 drive-strength = <12>;
132 bias-disable;
133 };
134 };
135
136 pcie1_pins: pcie1_pinmux {
137 mux {
138 pins = "gpio48";
139 function = "pcie2_rst";
140 drive-strength = <12>;
141 bias-disable;
142 };
143 };
144
145 pcie2_pins: pcie2_pinmux {
146 mux {
147 pins = "gpio63";
148 function = "pcie3_rst";
149 drive-strength = <12>;
150 bias-disable;
151 };
152 };
153
154 spi_pins: spi_pins {
155 mux {
156 pins = "gpio18", "gpio19", "gpio21";
157 function = "gsbi5";
158 drive-strength = <10>;
159 bias-none;
160 };
161 };
162
163 leds_pins: leds_pins {
164 mux {
165 pins = "gpio7", "gpio8", "gpio9",
166 "gpio26", "gpio53";
167 function = "gpio";
168 drive-strength = <2>;
169 bias-pull-down;
170 output-low;
171 };
172 };
173
174 buttons_pins: buttons_pins {
175 mux {
176 pins = "gpio54";
177 drive-strength = <2>;
178 bias-pull-up;
179 };
180 };
181 };
182
183 intc: interrupt-controller@2000000 {
184 compatible = "qcom,msm-qgic2";
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 reg = <0x02000000 0x1000>,
188 <0x02002000 0x1000>;
189 };
190
191 timer@200a000 {
192 compatible = "qcom,kpss-timer",
193 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
194 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
195 IRQ_TYPE_EDGE_RISING)>,
196 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
197 IRQ_TYPE_EDGE_RISING)>,
198 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
199 IRQ_TYPE_EDGE_RISING)>,
200 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
201 IRQ_TYPE_EDGE_RISING)>,
202 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
203 IRQ_TYPE_EDGE_RISING)>;
204 reg = <0x0200a000 0x100>;
205 clock-frequency = <25000000>,
206 <32768>;
207 clocks = <&sleep_clk>;
208 clock-names = "sleep";
209 cpu-offset = <0x80000>;
210 };
211
212 acc0: clock-controller@2088000 {
213 compatible = "qcom,kpss-acc-v1";
214 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
215 };
216
217 acc1: clock-controller@2098000 {
218 compatible = "qcom,kpss-acc-v1";
219 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
220 };
221
222 saw0: regulator@2089000 {
223 compatible = "qcom,saw2";
224 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
225 regulator;
226 };
227
228 saw1: regulator@2099000 {
229 compatible = "qcom,saw2";
230 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
231 regulator;
232 };
233
234 gsbi2: gsbi@12480000 {
235 compatible = "qcom,gsbi-v1.0.0";
236 cell-index = <2>;
237 reg = <0x12480000 0x100>;
238 clocks = <&gcc GSBI2_H_CLK>;
239 clock-names = "iface";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges;
243 status = "disabled";
244
245 syscon-tcsr = <&tcsr>;
246
247 serial@12490000 {
248 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
249 reg = <0x12490000 0x1000>,
250 <0x12480000 0x1000>;
251 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
253 clock-names = "core", "iface";
254 status = "disabled";
255 };
256
257 i2c@124a0000 {
258 compatible = "qcom,i2c-qup-v1.1.1";
259 reg = <0x124a0000 0x1000>;
260 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
261
262 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
263 clock-names = "core", "iface";
264 status = "disabled";
265
266 #address-cells = <1>;
267 #size-cells = <0>;
268 };
269
270 };
271
272 gsbi4: gsbi@16300000 {
273 compatible = "qcom,gsbi-v1.0.0";
274 cell-index = <4>;
275 reg = <0x16300000 0x100>;
276 clocks = <&gcc GSBI4_H_CLK>;
277 clock-names = "iface";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 ranges;
281 status = "disabled";
282
283 syscon-tcsr = <&tcsr>;
284
285 gsbi4_serial: serial@16340000 {
286 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
287 reg = <0x16340000 0x1000>,
288 <0x16300000 0x1000>;
289 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
291 clock-names = "core", "iface";
292 status = "disabled";
293 };
294
295 i2c@16380000 {
296 compatible = "qcom,i2c-qup-v1.1.1";
297 reg = <0x16380000 0x1000>;
298 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
299
300 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
301 clock-names = "core", "iface";
302 status = "disabled";
303
304 #address-cells = <1>;
305 #size-cells = <0>;
306 };
307 };
308
309 gsbi5: gsbi@1a200000 {
310 compatible = "qcom,gsbi-v1.0.0";
311 cell-index = <5>;
312 reg = <0x1a200000 0x100>;
313 clocks = <&gcc GSBI5_H_CLK>;
314 clock-names = "iface";
315 #address-cells = <1>;
316 #size-cells = <1>;
317 ranges;
318 status = "disabled";
319
320 syscon-tcsr = <&tcsr>;
321
322 serial@1a240000 {
323 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
324 reg = <0x1a240000 0x1000>,
325 <0x1a200000 0x1000>;
326 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
328 clock-names = "core", "iface";
329 status = "disabled";
330 };
331
332 i2c@1a280000 {
333 compatible = "qcom,i2c-qup-v1.1.1";
334 reg = <0x1a280000 0x1000>;
335 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
336
337 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
338 clock-names = "core", "iface";
339 status = "disabled";
340
341 #address-cells = <1>;
342 #size-cells = <0>;
343 };
344
345 spi@1a280000 {
346 compatible = "qcom,spi-qup-v1.1.1";
347 reg = <0x1a280000 0x1000>;
348 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
349
350 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
351 clock-names = "core", "iface";
352 status = "disabled";
353
354 #address-cells = <1>;
355 #size-cells = <0>;
356 };
357 };
358
359 gsbi7: gsbi@16600000 {
360 status = "disabled";
361 compatible = "qcom,gsbi-v1.0.0";
362 cell-index = <7>;
363 reg = <0x16600000 0x100>;
364 clocks = <&gcc GSBI7_H_CLK>;
365 clock-names = "iface";
366 #address-cells = <1>;
367 #size-cells = <1>;
368 ranges;
369 syscon-tcsr = <&tcsr>;
370
371 gsbi7_serial: serial@16640000 {
372 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
373 reg = <0x16640000 0x1000>,
374 <0x16600000 0x1000>;
375 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
377 clock-names = "core", "iface";
378 status = "disabled";
379 };
380 };
381
382 sata_phy: sata-phy@1b400000 {
383 compatible = "qcom,ipq806x-sata-phy";
384 reg = <0x1b400000 0x200>;
385
386 clocks = <&gcc SATA_PHY_CFG_CLK>;
387 clock-names = "cfg";
388
389 #phy-cells = <0>;
390 status = "disabled";
391 };
392
393 sata@29000000 {
394 compatible = "qcom,ipq806x-ahci", "generic-ahci";
395 reg = <0x29000000 0x180>;
396
397 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
398
399 clocks = <&gcc SFAB_SATA_S_H_CLK>,
400 <&gcc SATA_H_CLK>,
401 <&gcc SATA_A_CLK>,
402 <&gcc SATA_RXOOB_CLK>,
403 <&gcc SATA_PMALIVE_CLK>;
404 clock-names = "slave_face", "iface", "core",
405 "rxoob", "pmalive";
406
407 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
408 assigned-clock-rates = <100000000>, <100000000>;
409
410 phys = <&sata_phy>;
411 phy-names = "sata-phy";
412 status = "disabled";
413 };
414
415 qcom,ssbi@500000 {
416 compatible = "qcom,ssbi";
417 reg = <0x00500000 0x1000>;
418 qcom,controller-type = "pmic-arbiter";
419 };
420
421 gcc: clock-controller@900000 {
422 compatible = "qcom,gcc-ipq8064";
423 reg = <0x00900000 0x4000>;
424 #clock-cells = <1>;
425 #reset-cells = <1>;
426 };
427
428 tcsr: syscon@1a400000 {
429 compatible = "qcom,tcsr-ipq8064", "syscon";
430 reg = <0x1a400000 0x100>;
431 };
432
433 lcc: clock-controller@28000000 {
434 compatible = "qcom,lcc-ipq8064";
435 reg = <0x28000000 0x1000>;
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 };
439
440 pcie0: pci@1b500000 {
441 compatible = "qcom,pcie-ipq8064";
442 reg = <0x1b500000 0x1000
443 0x1b502000 0x80
444 0x1b600000 0x100
445 0x0ff00000 0x100000>;
446 reg-names = "dbi", "elbi", "parf", "config";
447 device_type = "pci";
448 linux,pci-domain = <0>;
449 bus-range = <0x00 0xff>;
450 num-lanes = <1>;
451 #address-cells = <3>;
452 #size-cells = <2>;
453
454 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
455 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
456
457 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "msi";
459 #interrupt-cells = <1>;
460 interrupt-map-mask = <0 0 0 0x7>;
461 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
462 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
463 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
464 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
465
466 clocks = <&gcc PCIE_A_CLK>,
467 <&gcc PCIE_H_CLK>,
468 <&gcc PCIE_PHY_CLK>,
469 <&gcc PCIE_AUX_CLK>,
470 <&gcc PCIE_ALT_REF_CLK>;
471 clock-names = "core", "iface", "phy", "aux", "ref";
472
473 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
474 assigned-clock-rates = <100000000>;
475
476 resets = <&gcc PCIE_ACLK_RESET>,
477 <&gcc PCIE_HCLK_RESET>,
478 <&gcc PCIE_POR_RESET>,
479 <&gcc PCIE_PCI_RESET>,
480 <&gcc PCIE_PHY_RESET>,
481 <&gcc PCIE_EXT_RESET>;
482 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
483
484 pinctrl-0 = <&pcie0_pins>;
485 pinctrl-names = "default";
486
487 status = "disabled";
488 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
489 };
490
491 pcie1: pci@1b700000 {
492 compatible = "qcom,pcie-ipq8064";
493 reg = <0x1b700000 0x1000
494 0x1b702000 0x80
495 0x1b800000 0x100
496 0x31f00000 0x100000>;
497 reg-names = "dbi", "elbi", "parf", "config";
498 device_type = "pci";
499 linux,pci-domain = <1>;
500 bus-range = <0x00 0xff>;
501 num-lanes = <1>;
502 #address-cells = <3>;
503 #size-cells = <2>;
504
505 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
506 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
507
508 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "msi";
510 #interrupt-cells = <1>;
511 interrupt-map-mask = <0 0 0 0x7>;
512 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
513 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
514 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
515 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
516
517 clocks = <&gcc PCIE_1_A_CLK>,
518 <&gcc PCIE_1_H_CLK>,
519 <&gcc PCIE_1_PHY_CLK>,
520 <&gcc PCIE_1_AUX_CLK>,
521 <&gcc PCIE_1_ALT_REF_CLK>;
522 clock-names = "core", "iface", "phy", "aux", "ref";
523
524 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
525 assigned-clock-rates = <100000000>;
526
527 resets = <&gcc PCIE_1_ACLK_RESET>,
528 <&gcc PCIE_1_HCLK_RESET>,
529 <&gcc PCIE_1_POR_RESET>,
530 <&gcc PCIE_1_PCI_RESET>,
531 <&gcc PCIE_1_PHY_RESET>,
532 <&gcc PCIE_1_EXT_RESET>;
533 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
534
535 pinctrl-0 = <&pcie1_pins>;
536 pinctrl-names = "default";
537
538 status = "disabled";
539 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
540 };
541
542 pcie2: pci@1b900000 {
543 compatible = "qcom,pcie-ipq8064";
544 reg = <0x1b900000 0x1000
545 0x1b902000 0x80
546 0x1ba00000 0x100
547 0x35f00000 0x100000>;
548 reg-names = "dbi", "elbi", "parf", "config";
549 device_type = "pci";
550 linux,pci-domain = <2>;
551 bus-range = <0x00 0xff>;
552 num-lanes = <1>;
553 #address-cells = <3>;
554 #size-cells = <2>;
555
556 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
557 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
558
559 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 interrupt-names = "msi";
561 #interrupt-cells = <1>;
562 interrupt-map-mask = <0 0 0 0x7>;
563 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
564 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
565 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
566 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
567
568 clocks = <&gcc PCIE_2_A_CLK>,
569 <&gcc PCIE_2_H_CLK>,
570 <&gcc PCIE_2_PHY_CLK>,
571 <&gcc PCIE_2_AUX_CLK>,
572 <&gcc PCIE_2_ALT_REF_CLK>;
573 clock-names = "core", "iface", "phy", "aux", "ref";
574
575 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
576 assigned-clock-rates = <100000000>;
577
578 resets = <&gcc PCIE_2_ACLK_RESET>,
579 <&gcc PCIE_2_HCLK_RESET>,
580 <&gcc PCIE_2_POR_RESET>,
581 <&gcc PCIE_2_PCI_RESET>,
582 <&gcc PCIE_2_PHY_RESET>,
583 <&gcc PCIE_2_EXT_RESET>;
584 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
585
586 pinctrl-0 = <&pcie2_pins>;
587 pinctrl-names = "default";
588
589 status = "disabled";
590 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
591 };
592
593 vsdcc_fixed: vsdcc-regulator {
594 compatible = "regulator-fixed";
595 regulator-name = "SDCC Power";
596 regulator-min-microvolt = <3300000>;
597 regulator-max-microvolt = <3300000>;
598 regulator-always-on;
599 };
600
601 sdcc1bam:dma@12402000 {
602 compatible = "qcom,bam-v1.3.0";
603 reg = <0x12402000 0x8000>;
604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&gcc SDC1_H_CLK>;
606 clock-names = "bam_clk";
607 #dma-cells = <1>;
608 qcom,ee = <0>;
609 };
610
611 sdcc3bam:dma@12182000 {
612 compatible = "qcom,bam-v1.3.0";
613 reg = <0x12182000 0x8000>;
614 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&gcc SDC3_H_CLK>;
616 clock-names = "bam_clk";
617 #dma-cells = <1>;
618 qcom,ee = <0>;
619 };
620
621 amba {
622 compatible = "simple-bus";
623 #address-cells = <1>;
624 #size-cells = <1>;
625 ranges;
626
627 sdcc@12400000 {
628 status = "disabled";
629 compatible = "arm,pl18x", "arm,primecell";
630 arm,primecell-periphid = <0x00051180>;
631 reg = <0x12400000 0x2000>;
632 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
633 interrupt-names = "cmd_irq";
634 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
635 clock-names = "mclk", "apb_pclk";
636 bus-width = <8>;
637 max-frequency = <96000000>;
638 non-removable;
639 cap-sd-highspeed;
640 cap-mmc-highspeed;
641 mmc-ddr-1_8v;
642 vmmc-supply = <&vsdcc_fixed>;
643 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
644 dma-names = "tx", "rx";
645 };
646
647 sdcc@12180000 {
648 compatible = "arm,pl18x", "arm,primecell";
649 arm,primecell-periphid = <0x00051180>;
650 status = "disabled";
651 reg = <0x12180000 0x2000>;
652 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
653 interrupt-names = "cmd_irq";
654 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
655 clock-names = "mclk", "apb_pclk";
656 bus-width = <8>;
657 cap-sd-highspeed;
658 cap-mmc-highspeed;
659 max-frequency = <192000000>;
660 #mmc-ddr-1_8v;
661 sd-uhs-sdr104;
662 sd-uhs-ddr50;
663 vqmmc-supply = <&vsdcc_fixed>;
664 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
665 dma-names = "tx", "rx";
666 };
667 };
668 };
669};