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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 */
4#include <linux/bits.h>
5#include <linux/clk.h>
6#include <linux/delay.h>
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/watchdog.h>
14#include <linux/of_device.h>
15
16enum wdt_reg {
17 WDT_RST,
18 WDT_EN,
19 WDT_STS,
20 WDT_BARK_TIME,
21 WDT_BITE_TIME,
22};
23
24#define QCOM_WDT_ENABLE BIT(0)
25
26static const u32 reg_offset_data_apcs_tmr[] = {
27 [WDT_RST] = 0x38,
28 [WDT_EN] = 0x40,
29 [WDT_STS] = 0x44,
30 [WDT_BARK_TIME] = 0x4C,
31 [WDT_BITE_TIME] = 0x5C,
32};
33
34static const u32 reg_offset_data_kpss[] = {
35 [WDT_RST] = 0x4,
36 [WDT_EN] = 0x8,
37 [WDT_STS] = 0xC,
38 [WDT_BARK_TIME] = 0x10,
39 [WDT_BITE_TIME] = 0x14,
40};
41
42struct qcom_wdt_match_data {
43 const u32 *offset;
44 bool pretimeout;
45};
46
47struct qcom_wdt {
48 struct watchdog_device wdd;
49 unsigned long rate;
50 void __iomem *base;
51 const u32 *layout;
52};
53
54static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
55{
56 return wdt->base + wdt->layout[reg];
57}
58
59static inline
60struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
61{
62 return container_of(wdd, struct qcom_wdt, wdd);
63}
64
65static irqreturn_t qcom_wdt_isr(int irq, void *arg)
66{
67 struct watchdog_device *wdd = arg;
68
69 watchdog_notify_pretimeout(wdd);
70
71 return IRQ_HANDLED;
72}
73
74static int qcom_wdt_start(struct watchdog_device *wdd)
75{
76 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
77 unsigned int bark = wdd->timeout - wdd->pretimeout;
78
79 writel(0, wdt_addr(wdt, WDT_EN));
80 writel(1, wdt_addr(wdt, WDT_RST));
81 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
82 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
83 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
84 return 0;
85}
86
87static int qcom_wdt_stop(struct watchdog_device *wdd)
88{
89 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
90
91 writel(0, wdt_addr(wdt, WDT_EN));
92 return 0;
93}
94
95static int qcom_wdt_ping(struct watchdog_device *wdd)
96{
97 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
98
99 writel(1, wdt_addr(wdt, WDT_RST));
100 return 0;
101}
102
103static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
104 unsigned int timeout)
105{
106 wdd->timeout = timeout;
107 return qcom_wdt_start(wdd);
108}
109
110static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
111 unsigned int timeout)
112{
113 wdd->pretimeout = timeout;
114 return qcom_wdt_start(wdd);
115}
116
117static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
118 void *data)
119{
120 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
121 u32 timeout;
122
123 /*
124 * Trigger watchdog bite:
125 * Setup BITE_TIME to be 128ms, and enable WDT.
126 */
127 timeout = 128 * wdt->rate / 1000;
128
129 writel(0, wdt_addr(wdt, WDT_EN));
130 writel(1, wdt_addr(wdt, WDT_RST));
131 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
132 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
133 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
134
135 /*
136 * Actually make sure the above sequence hits hardware before sleeping.
137 */
138 wmb();
139
140 mdelay(150);
141 return 0;
142}
143
144static int qcom_wdt_is_running(struct watchdog_device *wdd)
145{
146 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
147
148 return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
149}
150
151static const struct watchdog_ops qcom_wdt_ops = {
152 .start = qcom_wdt_start,
153 .stop = qcom_wdt_stop,
154 .ping = qcom_wdt_ping,
155 .set_timeout = qcom_wdt_set_timeout,
156 .set_pretimeout = qcom_wdt_set_pretimeout,
157 .restart = qcom_wdt_restart,
158 .owner = THIS_MODULE,
159};
160
161static const struct watchdog_info qcom_wdt_info = {
162 .options = WDIOF_KEEPALIVEPING
163 | WDIOF_MAGICCLOSE
164 | WDIOF_SETTIMEOUT
165 | WDIOF_CARDRESET,
166 .identity = KBUILD_MODNAME,
167};
168
169static const struct watchdog_info qcom_wdt_pt_info = {
170 .options = WDIOF_KEEPALIVEPING
171 | WDIOF_MAGICCLOSE
172 | WDIOF_SETTIMEOUT
173 | WDIOF_PRETIMEOUT
174 | WDIOF_CARDRESET,
175 .identity = KBUILD_MODNAME,
176};
177
178static void qcom_clk_disable_unprepare(void *data)
179{
180 clk_disable_unprepare(data);
181}
182
183static const struct qcom_wdt_match_data match_data_apcs_tmr = {
184 .offset = reg_offset_data_apcs_tmr,
185 .pretimeout = false,
186};
187
188static const struct qcom_wdt_match_data match_data_kpss = {
189 .offset = reg_offset_data_kpss,
190 .pretimeout = true,
191};
192
193static int qcom_wdt_probe(struct platform_device *pdev)
194{
195 struct device *dev = &pdev->dev;
196 struct qcom_wdt *wdt;
197 struct resource *res;
198 struct device_node *np = dev->of_node;
199 const struct qcom_wdt_match_data *data;
200 u32 percpu_offset;
201 int irq, ret;
202 struct clk *clk;
203
204 data = of_device_get_match_data(dev);
205 if (!data) {
206 dev_err(dev, "Unsupported QCOM WDT module\n");
207 return -ENODEV;
208 }
209
210 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
211 if (!wdt)
212 return -ENOMEM;
213
214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 if (!res)
216 return -ENOMEM;
217
218 /* We use CPU0's DGT for the watchdog */
219 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
220 percpu_offset = 0;
221
222 res->start += percpu_offset;
223 res->end += percpu_offset;
224
225 wdt->base = devm_ioremap_resource(dev, res);
226 if (IS_ERR(wdt->base))
227 return PTR_ERR(wdt->base);
228
229 clk = devm_clk_get(dev, NULL);
230 if (IS_ERR(clk)) {
231 dev_err(dev, "failed to get input clock\n");
232 return PTR_ERR(clk);
233 }
234
235 ret = clk_prepare_enable(clk);
236 if (ret) {
237 dev_err(dev, "failed to setup clock\n");
238 return ret;
239 }
240 ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
241 if (ret)
242 return ret;
243
244 /*
245 * We use the clock rate to calculate the max timeout, so ensure it's
246 * not zero to avoid a divide-by-zero exception.
247 *
248 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
249 * that it would bite before a second elapses it's usefulness is
250 * limited. Bail if this is the case.
251 */
252 wdt->rate = clk_get_rate(clk);
253 if (wdt->rate == 0 ||
254 wdt->rate > 0x10000000U) {
255 dev_err(dev, "invalid clock rate\n");
256 return -EINVAL;
257 }
258
259 /* check if there is pretimeout support */
260 irq = platform_get_irq_optional(pdev, 0);
261 if (data->pretimeout && irq > 0) {
262 ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
263 "wdt_bark", &wdt->wdd);
264 if (ret)
265 return ret;
266
267 wdt->wdd.info = &qcom_wdt_pt_info;
268 wdt->wdd.pretimeout = 1;
269 } else {
270 if (irq == -EPROBE_DEFER)
271 return -EPROBE_DEFER;
272
273 wdt->wdd.info = &qcom_wdt_info;
274 }
275
276 wdt->wdd.ops = &qcom_wdt_ops;
277 wdt->wdd.min_timeout = 1;
278 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
279 wdt->wdd.parent = dev;
280 wdt->layout = data->offset;
281
282 if (readl(wdt_addr(wdt, WDT_STS)) & 1)
283 wdt->wdd.bootstatus = WDIOF_CARDRESET;
284
285 /*
286 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
287 * default, unless the max timeout is less than 30 seconds, then use
288 * the max instead.
289 */
290 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
291 watchdog_init_timeout(&wdt->wdd, 0, dev);
292
293 /*
294 * If WDT is already running, call WDT start which
295 * will stop the WDT, set timeouts as bootloader
296 * might use different ones and set running bit
297 * to inform the WDT subsystem to ping the WDT
298 */
299 if (qcom_wdt_is_running(&wdt->wdd)) {
300 qcom_wdt_start(&wdt->wdd);
301 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
302 }
303
304 ret = devm_watchdog_register_device(dev, &wdt->wdd);
305 if (ret)
306 return ret;
307
308 platform_set_drvdata(pdev, wdt);
309 return 0;
310}
311
312static int __maybe_unused qcom_wdt_suspend(struct device *dev)
313{
314 struct qcom_wdt *wdt = dev_get_drvdata(dev);
315
316 if (watchdog_active(&wdt->wdd))
317 qcom_wdt_stop(&wdt->wdd);
318
319 return 0;
320}
321
322static int __maybe_unused qcom_wdt_resume(struct device *dev)
323{
324 struct qcom_wdt *wdt = dev_get_drvdata(dev);
325
326 if (watchdog_active(&wdt->wdd))
327 qcom_wdt_start(&wdt->wdd);
328
329 return 0;
330}
331
332static const struct dev_pm_ops qcom_wdt_pm_ops = {
333 SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
334};
335
336static const struct of_device_id qcom_wdt_of_table[] = {
337 { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
338 { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
339 { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
340 { },
341};
342MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
343
344static struct platform_driver qcom_watchdog_driver = {
345 .probe = qcom_wdt_probe,
346 .driver = {
347 .name = KBUILD_MODNAME,
348 .of_match_table = qcom_wdt_of_table,
349 .pm = &qcom_wdt_pm_ops,
350 },
351};
352module_platform_driver(qcom_watchdog_driver);
353
354MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
355MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 */
4#include <linux/bits.h>
5#include <linux/clk.h>
6#include <linux/delay.h>
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/watchdog.h>
14#include <linux/of_device.h>
15
16enum wdt_reg {
17 WDT_RST,
18 WDT_EN,
19 WDT_STS,
20 WDT_BARK_TIME,
21 WDT_BITE_TIME,
22};
23
24#define QCOM_WDT_ENABLE BIT(0)
25#define QCOM_WDT_ENABLE_IRQ BIT(1)
26
27static const u32 reg_offset_data_apcs_tmr[] = {
28 [WDT_RST] = 0x38,
29 [WDT_EN] = 0x40,
30 [WDT_STS] = 0x44,
31 [WDT_BARK_TIME] = 0x4C,
32 [WDT_BITE_TIME] = 0x5C,
33};
34
35static const u32 reg_offset_data_kpss[] = {
36 [WDT_RST] = 0x4,
37 [WDT_EN] = 0x8,
38 [WDT_STS] = 0xC,
39 [WDT_BARK_TIME] = 0x10,
40 [WDT_BITE_TIME] = 0x14,
41};
42
43struct qcom_wdt {
44 struct watchdog_device wdd;
45 unsigned long rate;
46 void __iomem *base;
47 const u32 *layout;
48};
49
50static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
51{
52 return wdt->base + wdt->layout[reg];
53}
54
55static inline
56struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
57{
58 return container_of(wdd, struct qcom_wdt, wdd);
59}
60
61static inline int qcom_get_enable(struct watchdog_device *wdd)
62{
63 int enable = QCOM_WDT_ENABLE;
64
65 if (wdd->pretimeout)
66 enable |= QCOM_WDT_ENABLE_IRQ;
67
68 return enable;
69}
70
71static irqreturn_t qcom_wdt_isr(int irq, void *arg)
72{
73 struct watchdog_device *wdd = arg;
74
75 watchdog_notify_pretimeout(wdd);
76
77 return IRQ_HANDLED;
78}
79
80static int qcom_wdt_start(struct watchdog_device *wdd)
81{
82 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
83 unsigned int bark = wdd->timeout - wdd->pretimeout;
84
85 writel(0, wdt_addr(wdt, WDT_EN));
86 writel(1, wdt_addr(wdt, WDT_RST));
87 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
88 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
89 writel(qcom_get_enable(wdd), wdt_addr(wdt, WDT_EN));
90 return 0;
91}
92
93static int qcom_wdt_stop(struct watchdog_device *wdd)
94{
95 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
96
97 writel(0, wdt_addr(wdt, WDT_EN));
98 return 0;
99}
100
101static int qcom_wdt_ping(struct watchdog_device *wdd)
102{
103 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
104
105 writel(1, wdt_addr(wdt, WDT_RST));
106 return 0;
107}
108
109static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
110 unsigned int timeout)
111{
112 wdd->timeout = timeout;
113 return qcom_wdt_start(wdd);
114}
115
116static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
117 unsigned int timeout)
118{
119 wdd->pretimeout = timeout;
120 return qcom_wdt_start(wdd);
121}
122
123static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
124 void *data)
125{
126 struct qcom_wdt *wdt = to_qcom_wdt(wdd);
127 u32 timeout;
128
129 /*
130 * Trigger watchdog bite:
131 * Setup BITE_TIME to be 128ms, and enable WDT.
132 */
133 timeout = 128 * wdt->rate / 1000;
134
135 writel(0, wdt_addr(wdt, WDT_EN));
136 writel(1, wdt_addr(wdt, WDT_RST));
137 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
138 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
139 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
140
141 /*
142 * Actually make sure the above sequence hits hardware before sleeping.
143 */
144 wmb();
145
146 msleep(150);
147 return 0;
148}
149
150static const struct watchdog_ops qcom_wdt_ops = {
151 .start = qcom_wdt_start,
152 .stop = qcom_wdt_stop,
153 .ping = qcom_wdt_ping,
154 .set_timeout = qcom_wdt_set_timeout,
155 .set_pretimeout = qcom_wdt_set_pretimeout,
156 .restart = qcom_wdt_restart,
157 .owner = THIS_MODULE,
158};
159
160static const struct watchdog_info qcom_wdt_info = {
161 .options = WDIOF_KEEPALIVEPING
162 | WDIOF_MAGICCLOSE
163 | WDIOF_SETTIMEOUT
164 | WDIOF_CARDRESET,
165 .identity = KBUILD_MODNAME,
166};
167
168static const struct watchdog_info qcom_wdt_pt_info = {
169 .options = WDIOF_KEEPALIVEPING
170 | WDIOF_MAGICCLOSE
171 | WDIOF_SETTIMEOUT
172 | WDIOF_PRETIMEOUT
173 | WDIOF_CARDRESET,
174 .identity = KBUILD_MODNAME,
175};
176
177static void qcom_clk_disable_unprepare(void *data)
178{
179 clk_disable_unprepare(data);
180}
181
182static int qcom_wdt_probe(struct platform_device *pdev)
183{
184 struct device *dev = &pdev->dev;
185 struct qcom_wdt *wdt;
186 struct resource *res;
187 struct device_node *np = dev->of_node;
188 const u32 *regs;
189 u32 percpu_offset;
190 int irq, ret;
191 struct clk *clk;
192
193 regs = of_device_get_match_data(dev);
194 if (!regs) {
195 dev_err(dev, "Unsupported QCOM WDT module\n");
196 return -ENODEV;
197 }
198
199 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
200 if (!wdt)
201 return -ENOMEM;
202
203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
204 if (!res)
205 return -ENOMEM;
206
207 /* We use CPU0's DGT for the watchdog */
208 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
209 percpu_offset = 0;
210
211 res->start += percpu_offset;
212 res->end += percpu_offset;
213
214 wdt->base = devm_ioremap_resource(dev, res);
215 if (IS_ERR(wdt->base))
216 return PTR_ERR(wdt->base);
217
218 clk = devm_clk_get(dev, NULL);
219 if (IS_ERR(clk)) {
220 dev_err(dev, "failed to get input clock\n");
221 return PTR_ERR(clk);
222 }
223
224 ret = clk_prepare_enable(clk);
225 if (ret) {
226 dev_err(dev, "failed to setup clock\n");
227 return ret;
228 }
229 ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
230 if (ret)
231 return ret;
232
233 /*
234 * We use the clock rate to calculate the max timeout, so ensure it's
235 * not zero to avoid a divide-by-zero exception.
236 *
237 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
238 * that it would bite before a second elapses it's usefulness is
239 * limited. Bail if this is the case.
240 */
241 wdt->rate = clk_get_rate(clk);
242 if (wdt->rate == 0 ||
243 wdt->rate > 0x10000000U) {
244 dev_err(dev, "invalid clock rate\n");
245 return -EINVAL;
246 }
247
248 /* check if there is pretimeout support */
249 irq = platform_get_irq(pdev, 0);
250 if (irq > 0) {
251 ret = devm_request_irq(dev, irq, qcom_wdt_isr,
252 IRQF_TRIGGER_RISING,
253 "wdt_bark", &wdt->wdd);
254 if (ret)
255 return ret;
256
257 wdt->wdd.info = &qcom_wdt_pt_info;
258 wdt->wdd.pretimeout = 1;
259 } else {
260 if (irq == -EPROBE_DEFER)
261 return -EPROBE_DEFER;
262
263 wdt->wdd.info = &qcom_wdt_info;
264 }
265
266 wdt->wdd.ops = &qcom_wdt_ops;
267 wdt->wdd.min_timeout = 1;
268 wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
269 wdt->wdd.parent = dev;
270 wdt->layout = regs;
271
272 if (readl(wdt_addr(wdt, WDT_STS)) & 1)
273 wdt->wdd.bootstatus = WDIOF_CARDRESET;
274
275 /*
276 * If 'timeout-sec' unspecified in devicetree, assume a 30 second
277 * default, unless the max timeout is less than 30 seconds, then use
278 * the max instead.
279 */
280 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
281 watchdog_init_timeout(&wdt->wdd, 0, dev);
282
283 ret = devm_watchdog_register_device(dev, &wdt->wdd);
284 if (ret)
285 return ret;
286
287 platform_set_drvdata(pdev, wdt);
288 return 0;
289}
290
291static int __maybe_unused qcom_wdt_suspend(struct device *dev)
292{
293 struct qcom_wdt *wdt = dev_get_drvdata(dev);
294
295 if (watchdog_active(&wdt->wdd))
296 qcom_wdt_stop(&wdt->wdd);
297
298 return 0;
299}
300
301static int __maybe_unused qcom_wdt_resume(struct device *dev)
302{
303 struct qcom_wdt *wdt = dev_get_drvdata(dev);
304
305 if (watchdog_active(&wdt->wdd))
306 qcom_wdt_start(&wdt->wdd);
307
308 return 0;
309}
310
311static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
312
313static const struct of_device_id qcom_wdt_of_table[] = {
314 { .compatible = "qcom,kpss-timer", .data = reg_offset_data_apcs_tmr },
315 { .compatible = "qcom,scss-timer", .data = reg_offset_data_apcs_tmr },
316 { .compatible = "qcom,kpss-wdt", .data = reg_offset_data_kpss },
317 { },
318};
319MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
320
321static struct platform_driver qcom_watchdog_driver = {
322 .probe = qcom_wdt_probe,
323 .driver = {
324 .name = KBUILD_MODNAME,
325 .of_match_table = qcom_wdt_of_table,
326 .pm = &qcom_wdt_pm_ops,
327 },
328};
329module_platform_driver(qcom_watchdog_driver);
330
331MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
332MODULE_LICENSE("GPL v2");