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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 MediaTek Inc.
4 *
5 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/iopoll.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/platform_device.h>
15#include <linux/pm_wakeirq.h>
16#include <linux/reset.h>
17
18#include "mtu3.h"
19#include "mtu3_dr.h"
20#include "mtu3_debug.h"
21
22/* u2-port0 should be powered on and enabled; */
23int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
24{
25 void __iomem *ibase = ssusb->ippc_base;
26 u32 value, check_val;
27 int ret;
28
29 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
30 SSUSB_REF_RST_B_STS;
31
32 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
33 (check_val == (value & check_val)), 100, 20000);
34 if (ret) {
35 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
36 return ret;
37 }
38
39 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
40 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
41 if (ret) {
42 dev_err(ssusb->dev, "mac2 clock is not stable\n");
43 return ret;
44 }
45
46 return 0;
47}
48
49static int wait_for_ip_sleep(struct ssusb_mtk *ssusb)
50{
51 bool sleep_check = true;
52 u32 value;
53 int ret;
54
55 if (!ssusb->is_host)
56 sleep_check = ssusb_gadget_ip_sleep_check(ssusb);
57
58 if (!sleep_check)
59 return 0;
60
61 /* wait for ip enter sleep mode */
62 ret = readl_poll_timeout(ssusb->ippc_base + U3D_SSUSB_IP_PW_STS1, value,
63 (value & SSUSB_IP_SLEEP_STS), 100, 100000);
64 if (ret) {
65 dev_err(ssusb->dev, "ip sleep failed!!!\n");
66 ret = -EBUSY;
67 } else {
68 /* workaround: avoid wrong wakeup signal latch for some soc */
69 usleep_range(100, 200);
70 }
71
72 return ret;
73}
74
75static int ssusb_phy_init(struct ssusb_mtk *ssusb)
76{
77 int i;
78 int ret;
79
80 for (i = 0; i < ssusb->num_phys; i++) {
81 ret = phy_init(ssusb->phys[i]);
82 if (ret)
83 goto exit_phy;
84 }
85 return 0;
86
87exit_phy:
88 for (; i > 0; i--)
89 phy_exit(ssusb->phys[i - 1]);
90
91 return ret;
92}
93
94static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
95{
96 int i;
97
98 for (i = 0; i < ssusb->num_phys; i++)
99 phy_exit(ssusb->phys[i]);
100
101 return 0;
102}
103
104static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
105{
106 int i;
107 int ret;
108
109 for (i = 0; i < ssusb->num_phys; i++) {
110 ret = phy_power_on(ssusb->phys[i]);
111 if (ret)
112 goto power_off_phy;
113 }
114 return 0;
115
116power_off_phy:
117 for (; i > 0; i--)
118 phy_power_off(ssusb->phys[i - 1]);
119
120 return ret;
121}
122
123static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
124{
125 unsigned int i;
126
127 for (i = 0; i < ssusb->num_phys; i++)
128 phy_power_off(ssusb->phys[i]);
129}
130
131static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
132{
133 int ret = 0;
134
135 ret = regulator_enable(ssusb->vusb33);
136 if (ret) {
137 dev_err(ssusb->dev, "failed to enable vusb33\n");
138 goto vusb33_err;
139 }
140
141 ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
142 if (ret)
143 goto clks_err;
144
145 ret = ssusb_phy_init(ssusb);
146 if (ret) {
147 dev_err(ssusb->dev, "failed to init phy\n");
148 goto phy_init_err;
149 }
150
151 ret = ssusb_phy_power_on(ssusb);
152 if (ret) {
153 dev_err(ssusb->dev, "failed to power on phy\n");
154 goto phy_err;
155 }
156
157 return 0;
158
159phy_err:
160 ssusb_phy_exit(ssusb);
161phy_init_err:
162 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
163clks_err:
164 regulator_disable(ssusb->vusb33);
165vusb33_err:
166 return ret;
167}
168
169static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
170{
171 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
172 regulator_disable(ssusb->vusb33);
173 ssusb_phy_power_off(ssusb);
174 ssusb_phy_exit(ssusb);
175}
176
177static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
178{
179 /* reset whole ip (xhci & u3d) */
180 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
181 udelay(1);
182 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
183
184 /*
185 * device ip may be powered on in firmware/BROM stage before entering
186 * kernel stage;
187 * power down device ip, otherwise ip-sleep will fail when working as
188 * host only mode
189 */
190 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
191}
192
193static void ssusb_u3_drd_check(struct ssusb_mtk *ssusb)
194{
195 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
196 u32 dev_u3p_num;
197 u32 host_u3p_num;
198 u32 value;
199
200 /* u3 port0 is disabled */
201 if (ssusb->u3p_dis_msk & BIT(0)) {
202 otg_sx->is_u3_drd = false;
203 goto out;
204 }
205
206 value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_DEV_CAP);
207 dev_u3p_num = SSUSB_IP_DEV_U3_PORT_NUM(value);
208
209 value = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
210 host_u3p_num = SSUSB_IP_XHCI_U3_PORT_NUM(value);
211
212 otg_sx->is_u3_drd = !!(dev_u3p_num && host_u3p_num);
213
214out:
215 dev_info(ssusb->dev, "usb3-drd: %d\n", otg_sx->is_u3_drd);
216}
217
218static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
219{
220 struct device_node *node = pdev->dev.of_node;
221 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
222 struct clk_bulk_data *clks = ssusb->clks;
223 struct device *dev = &pdev->dev;
224 int i;
225 int ret;
226
227 ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
228 if (IS_ERR(ssusb->vusb33)) {
229 dev_err(dev, "failed to get vusb33\n");
230 return PTR_ERR(ssusb->vusb33);
231 }
232
233 clks[0].id = "sys_ck";
234 clks[1].id = "ref_ck";
235 clks[2].id = "mcu_ck";
236 clks[3].id = "dma_ck";
237 ret = devm_clk_bulk_get_optional(dev, BULK_CLKS_CNT, clks);
238 if (ret)
239 return ret;
240
241 ssusb->num_phys = of_count_phandle_with_args(node,
242 "phys", "#phy-cells");
243 if (ssusb->num_phys > 0) {
244 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
245 sizeof(*ssusb->phys), GFP_KERNEL);
246 if (!ssusb->phys)
247 return -ENOMEM;
248 } else {
249 ssusb->num_phys = 0;
250 }
251
252 for (i = 0; i < ssusb->num_phys; i++) {
253 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
254 if (IS_ERR(ssusb->phys[i])) {
255 dev_err(dev, "failed to get phy-%d\n", i);
256 return PTR_ERR(ssusb->phys[i]);
257 }
258 }
259
260 ssusb->ippc_base = devm_platform_ioremap_resource_byname(pdev, "ippc");
261 if (IS_ERR(ssusb->ippc_base))
262 return PTR_ERR(ssusb->ippc_base);
263
264 ssusb->wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
265 if (ssusb->wakeup_irq == -EPROBE_DEFER)
266 return ssusb->wakeup_irq;
267
268 ssusb->dr_mode = usb_get_dr_mode(dev);
269 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
270 ssusb->dr_mode = USB_DR_MODE_OTG;
271
272 of_property_read_u32(node, "mediatek,u3p-dis-msk", &ssusb->u3p_dis_msk);
273
274 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
275 goto out;
276
277 /* if host role is supported */
278 ret = ssusb_wakeup_of_property_parse(ssusb, node);
279 if (ret) {
280 dev_err(dev, "failed to parse uwk property\n");
281 return ret;
282 }
283
284 /* optional property, ignore the error if it does not exist */
285 of_property_read_u32(node, "mediatek,u2p-dis-msk",
286 &ssusb->u2p_dis_msk);
287
288 otg_sx->vbus = devm_regulator_get(dev, "vbus");
289 if (IS_ERR(otg_sx->vbus)) {
290 dev_err(dev, "failed to get vbus\n");
291 return PTR_ERR(otg_sx->vbus);
292 }
293
294 if (ssusb->dr_mode == USB_DR_MODE_HOST)
295 goto out;
296
297 /* if dual-role mode is supported */
298 otg_sx->manual_drd_enabled =
299 of_property_read_bool(node, "enable-manual-drd");
300 otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
301
302 /* can't disable port0 when use dual-role mode */
303 ssusb->u2p_dis_msk &= ~0x1;
304
305 if (otg_sx->role_sw_used || otg_sx->manual_drd_enabled)
306 goto out;
307
308 if (of_property_read_bool(node, "extcon")) {
309 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
310 if (IS_ERR(otg_sx->edev)) {
311 return dev_err_probe(dev, PTR_ERR(otg_sx->edev),
312 "couldn't get extcon device\n");
313 }
314 }
315
316out:
317 dev_info(dev, "dr_mode: %d, drd: %s\n", ssusb->dr_mode,
318 otg_sx->manual_drd_enabled ? "manual" : "auto");
319 dev_info(dev, "u2p_dis_msk: %x, u3p_dis_msk: %x\n",
320 ssusb->u2p_dis_msk, ssusb->u3p_dis_msk);
321
322 return 0;
323}
324
325static int mtu3_probe(struct platform_device *pdev)
326{
327 struct device_node *node = pdev->dev.of_node;
328 struct device *dev = &pdev->dev;
329 struct ssusb_mtk *ssusb;
330 int ret = -ENOMEM;
331
332 /* all elements are set to ZERO as default value */
333 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
334 if (!ssusb)
335 return -ENOMEM;
336
337 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
338 if (ret) {
339 dev_err(dev, "No suitable DMA config available\n");
340 return -ENOTSUPP;
341 }
342
343 platform_set_drvdata(pdev, ssusb);
344 ssusb->dev = dev;
345
346 ret = get_ssusb_rscs(pdev, ssusb);
347 if (ret)
348 return ret;
349
350 ssusb_debugfs_create_root(ssusb);
351
352 /* enable power domain */
353 pm_runtime_set_active(dev);
354 pm_runtime_use_autosuspend(dev);
355 pm_runtime_set_autosuspend_delay(dev, 4000);
356 pm_runtime_enable(dev);
357 pm_runtime_get_sync(dev);
358
359 device_init_wakeup(dev, true);
360
361 ret = ssusb_rscs_init(ssusb);
362 if (ret)
363 goto comm_init_err;
364
365 if (ssusb->wakeup_irq > 0) {
366 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, ssusb->wakeup_irq);
367 if (ret) {
368 dev_err(dev, "failed to set wakeup irq %d\n", ssusb->wakeup_irq);
369 goto comm_exit;
370 }
371 dev_info(dev, "wakeup irq %d\n", ssusb->wakeup_irq);
372 }
373
374 ret = device_reset_optional(dev);
375 if (ret) {
376 dev_err_probe(dev, ret, "failed to reset controller\n");
377 goto comm_exit;
378 }
379
380 ssusb_ip_sw_reset(ssusb);
381 ssusb_u3_drd_check(ssusb);
382
383 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
384 ssusb->dr_mode = USB_DR_MODE_HOST;
385 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
386 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
387
388 /* default as host */
389 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
390
391 switch (ssusb->dr_mode) {
392 case USB_DR_MODE_PERIPHERAL:
393 ret = ssusb_gadget_init(ssusb);
394 if (ret) {
395 dev_err(dev, "failed to initialize gadget\n");
396 goto comm_exit;
397 }
398 break;
399 case USB_DR_MODE_HOST:
400 ret = ssusb_host_init(ssusb, node);
401 if (ret) {
402 dev_err(dev, "failed to initialize host\n");
403 goto comm_exit;
404 }
405 break;
406 case USB_DR_MODE_OTG:
407 ret = ssusb_gadget_init(ssusb);
408 if (ret) {
409 dev_err(dev, "failed to initialize gadget\n");
410 goto comm_exit;
411 }
412
413 ret = ssusb_host_init(ssusb, node);
414 if (ret) {
415 dev_err(dev, "failed to initialize host\n");
416 goto gadget_exit;
417 }
418
419 ret = ssusb_otg_switch_init(ssusb);
420 if (ret) {
421 dev_err(dev, "failed to initialize switch\n");
422 goto host_exit;
423 }
424 break;
425 default:
426 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
427 ret = -EINVAL;
428 goto comm_exit;
429 }
430
431 device_enable_async_suspend(dev);
432 pm_runtime_mark_last_busy(dev);
433 pm_runtime_put_autosuspend(dev);
434 pm_runtime_forbid(dev);
435
436 return 0;
437
438host_exit:
439 ssusb_host_exit(ssusb);
440gadget_exit:
441 ssusb_gadget_exit(ssusb);
442comm_exit:
443 ssusb_rscs_exit(ssusb);
444comm_init_err:
445 pm_runtime_put_noidle(dev);
446 pm_runtime_disable(dev);
447 ssusb_debugfs_remove_root(ssusb);
448
449 return ret;
450}
451
452static int mtu3_remove(struct platform_device *pdev)
453{
454 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
455
456 pm_runtime_get_sync(&pdev->dev);
457
458 switch (ssusb->dr_mode) {
459 case USB_DR_MODE_PERIPHERAL:
460 ssusb_gadget_exit(ssusb);
461 break;
462 case USB_DR_MODE_HOST:
463 ssusb_host_exit(ssusb);
464 break;
465 case USB_DR_MODE_OTG:
466 ssusb_otg_switch_exit(ssusb);
467 ssusb_gadget_exit(ssusb);
468 ssusb_host_exit(ssusb);
469 break;
470 default:
471 return -EINVAL;
472 }
473
474 ssusb_rscs_exit(ssusb);
475 ssusb_debugfs_remove_root(ssusb);
476 pm_runtime_disable(&pdev->dev);
477 pm_runtime_put_noidle(&pdev->dev);
478 pm_runtime_set_suspended(&pdev->dev);
479
480 return 0;
481}
482
483static int resume_ip_and_ports(struct ssusb_mtk *ssusb, pm_message_t msg)
484{
485 switch (ssusb->dr_mode) {
486 case USB_DR_MODE_PERIPHERAL:
487 ssusb_gadget_resume(ssusb, msg);
488 break;
489 case USB_DR_MODE_HOST:
490 ssusb_host_resume(ssusb, false);
491 break;
492 case USB_DR_MODE_OTG:
493 ssusb_host_resume(ssusb, !ssusb->is_host);
494 if (!ssusb->is_host)
495 ssusb_gadget_resume(ssusb, msg);
496
497 break;
498 default:
499 return -EINVAL;
500 }
501
502 return 0;
503}
504
505static int mtu3_suspend_common(struct device *dev, pm_message_t msg)
506{
507 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
508 int ret = 0;
509
510 dev_dbg(dev, "%s\n", __func__);
511
512 switch (ssusb->dr_mode) {
513 case USB_DR_MODE_PERIPHERAL:
514 ret = ssusb_gadget_suspend(ssusb, msg);
515 if (ret)
516 goto err;
517
518 break;
519 case USB_DR_MODE_HOST:
520 ssusb_host_suspend(ssusb);
521 break;
522 case USB_DR_MODE_OTG:
523 if (!ssusb->is_host) {
524 ret = ssusb_gadget_suspend(ssusb, msg);
525 if (ret)
526 goto err;
527 }
528 ssusb_host_suspend(ssusb);
529 break;
530 default:
531 return -EINVAL;
532 }
533
534 ret = wait_for_ip_sleep(ssusb);
535 if (ret)
536 goto sleep_err;
537
538 ssusb_phy_power_off(ssusb);
539 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
540 ssusb_wakeup_set(ssusb, true);
541 return 0;
542
543sleep_err:
544 resume_ip_and_ports(ssusb, msg);
545err:
546 return ret;
547}
548
549static int mtu3_resume_common(struct device *dev, pm_message_t msg)
550{
551 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
552 int ret;
553
554 dev_dbg(dev, "%s\n", __func__);
555
556 ssusb_wakeup_set(ssusb, false);
557 ret = clk_bulk_prepare_enable(BULK_CLKS_CNT, ssusb->clks);
558 if (ret)
559 goto clks_err;
560
561 ret = ssusb_phy_power_on(ssusb);
562 if (ret)
563 goto phy_err;
564
565 return resume_ip_and_ports(ssusb, msg);
566
567phy_err:
568 clk_bulk_disable_unprepare(BULK_CLKS_CNT, ssusb->clks);
569clks_err:
570 return ret;
571}
572
573static int __maybe_unused mtu3_suspend(struct device *dev)
574{
575 return mtu3_suspend_common(dev, PMSG_SUSPEND);
576}
577
578static int __maybe_unused mtu3_resume(struct device *dev)
579{
580 return mtu3_resume_common(dev, PMSG_SUSPEND);
581}
582
583static int __maybe_unused mtu3_runtime_suspend(struct device *dev)
584{
585 if (!device_may_wakeup(dev))
586 return 0;
587
588 return mtu3_suspend_common(dev, PMSG_AUTO_SUSPEND);
589}
590
591static int __maybe_unused mtu3_runtime_resume(struct device *dev)
592{
593 if (!device_may_wakeup(dev))
594 return 0;
595
596 return mtu3_resume_common(dev, PMSG_AUTO_SUSPEND);
597}
598
599static const struct dev_pm_ops mtu3_pm_ops = {
600 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
601 SET_RUNTIME_PM_OPS(mtu3_runtime_suspend,
602 mtu3_runtime_resume, NULL)
603};
604
605#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
606
607static const struct of_device_id mtu3_of_match[] = {
608 {.compatible = "mediatek,mt8173-mtu3",},
609 {.compatible = "mediatek,mtu3",},
610 {},
611};
612MODULE_DEVICE_TABLE(of, mtu3_of_match);
613
614static struct platform_driver mtu3_driver = {
615 .probe = mtu3_probe,
616 .remove = mtu3_remove,
617 .driver = {
618 .name = MTU3_DRIVER_NAME,
619 .pm = DEV_PM_OPS,
620 .of_match_table = mtu3_of_match,
621 },
622};
623module_platform_driver(mtu3_driver);
624
625MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
626MODULE_LICENSE("GPL v2");
627MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 MediaTek Inc.
4 *
5 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
6 */
7
8#include <linux/clk.h>
9#include <linux/dma-mapping.h>
10#include <linux/iopoll.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/platform_device.h>
16
17#include "mtu3.h"
18#include "mtu3_dr.h"
19#include "mtu3_debug.h"
20
21/* u2-port0 should be powered on and enabled; */
22int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
23{
24 void __iomem *ibase = ssusb->ippc_base;
25 u32 value, check_val;
26 int ret;
27
28 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
29 SSUSB_REF_RST_B_STS;
30
31 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
32 (check_val == (value & check_val)), 100, 20000);
33 if (ret) {
34 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
35 return ret;
36 }
37
38 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
39 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
40 if (ret) {
41 dev_err(ssusb->dev, "mac2 clock is not stable\n");
42 return ret;
43 }
44
45 return 0;
46}
47
48static int ssusb_phy_init(struct ssusb_mtk *ssusb)
49{
50 int i;
51 int ret;
52
53 for (i = 0; i < ssusb->num_phys; i++) {
54 ret = phy_init(ssusb->phys[i]);
55 if (ret)
56 goto exit_phy;
57 }
58 return 0;
59
60exit_phy:
61 for (; i > 0; i--)
62 phy_exit(ssusb->phys[i - 1]);
63
64 return ret;
65}
66
67static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
68{
69 int i;
70
71 for (i = 0; i < ssusb->num_phys; i++)
72 phy_exit(ssusb->phys[i]);
73
74 return 0;
75}
76
77static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
78{
79 int i;
80 int ret;
81
82 for (i = 0; i < ssusb->num_phys; i++) {
83 ret = phy_power_on(ssusb->phys[i]);
84 if (ret)
85 goto power_off_phy;
86 }
87 return 0;
88
89power_off_phy:
90 for (; i > 0; i--)
91 phy_power_off(ssusb->phys[i - 1]);
92
93 return ret;
94}
95
96static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
97{
98 unsigned int i;
99
100 for (i = 0; i < ssusb->num_phys; i++)
101 phy_power_off(ssusb->phys[i]);
102}
103
104static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
105{
106 int ret;
107
108 ret = clk_prepare_enable(ssusb->sys_clk);
109 if (ret) {
110 dev_err(ssusb->dev, "failed to enable sys_clk\n");
111 goto sys_clk_err;
112 }
113
114 ret = clk_prepare_enable(ssusb->ref_clk);
115 if (ret) {
116 dev_err(ssusb->dev, "failed to enable ref_clk\n");
117 goto ref_clk_err;
118 }
119
120 ret = clk_prepare_enable(ssusb->mcu_clk);
121 if (ret) {
122 dev_err(ssusb->dev, "failed to enable mcu_clk\n");
123 goto mcu_clk_err;
124 }
125
126 ret = clk_prepare_enable(ssusb->dma_clk);
127 if (ret) {
128 dev_err(ssusb->dev, "failed to enable dma_clk\n");
129 goto dma_clk_err;
130 }
131
132 return 0;
133
134dma_clk_err:
135 clk_disable_unprepare(ssusb->mcu_clk);
136mcu_clk_err:
137 clk_disable_unprepare(ssusb->ref_clk);
138ref_clk_err:
139 clk_disable_unprepare(ssusb->sys_clk);
140sys_clk_err:
141 return ret;
142}
143
144static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
145{
146 clk_disable_unprepare(ssusb->dma_clk);
147 clk_disable_unprepare(ssusb->mcu_clk);
148 clk_disable_unprepare(ssusb->ref_clk);
149 clk_disable_unprepare(ssusb->sys_clk);
150}
151
152static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
153{
154 int ret = 0;
155
156 ret = regulator_enable(ssusb->vusb33);
157 if (ret) {
158 dev_err(ssusb->dev, "failed to enable vusb33\n");
159 goto vusb33_err;
160 }
161
162 ret = ssusb_clks_enable(ssusb);
163 if (ret)
164 goto clks_err;
165
166 ret = ssusb_phy_init(ssusb);
167 if (ret) {
168 dev_err(ssusb->dev, "failed to init phy\n");
169 goto phy_init_err;
170 }
171
172 ret = ssusb_phy_power_on(ssusb);
173 if (ret) {
174 dev_err(ssusb->dev, "failed to power on phy\n");
175 goto phy_err;
176 }
177
178 return 0;
179
180phy_err:
181 ssusb_phy_exit(ssusb);
182phy_init_err:
183 ssusb_clks_disable(ssusb);
184clks_err:
185 regulator_disable(ssusb->vusb33);
186vusb33_err:
187 return ret;
188}
189
190static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
191{
192 ssusb_clks_disable(ssusb);
193 regulator_disable(ssusb->vusb33);
194 ssusb_phy_power_off(ssusb);
195 ssusb_phy_exit(ssusb);
196}
197
198static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
199{
200 /* reset whole ip (xhci & u3d) */
201 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
202 udelay(1);
203 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
204
205 /*
206 * device ip may be powered on in firmware/BROM stage before entering
207 * kernel stage;
208 * power down device ip, otherwise ip-sleep will fail when working as
209 * host only mode
210 */
211 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
212}
213
214static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
215{
216 struct device_node *node = pdev->dev.of_node;
217 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
218 struct device *dev = &pdev->dev;
219 struct resource *res;
220 int i;
221 int ret;
222
223 ssusb->vusb33 = devm_regulator_get(dev, "vusb33");
224 if (IS_ERR(ssusb->vusb33)) {
225 dev_err(dev, "failed to get vusb33\n");
226 return PTR_ERR(ssusb->vusb33);
227 }
228
229 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
230 if (IS_ERR(ssusb->sys_clk)) {
231 dev_err(dev, "failed to get sys clock\n");
232 return PTR_ERR(ssusb->sys_clk);
233 }
234
235 ssusb->ref_clk = devm_clk_get_optional(dev, "ref_ck");
236 if (IS_ERR(ssusb->ref_clk))
237 return PTR_ERR(ssusb->ref_clk);
238
239 ssusb->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
240 if (IS_ERR(ssusb->mcu_clk))
241 return PTR_ERR(ssusb->mcu_clk);
242
243 ssusb->dma_clk = devm_clk_get_optional(dev, "dma_ck");
244 if (IS_ERR(ssusb->dma_clk))
245 return PTR_ERR(ssusb->dma_clk);
246
247 ssusb->num_phys = of_count_phandle_with_args(node,
248 "phys", "#phy-cells");
249 if (ssusb->num_phys > 0) {
250 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
251 sizeof(*ssusb->phys), GFP_KERNEL);
252 if (!ssusb->phys)
253 return -ENOMEM;
254 } else {
255 ssusb->num_phys = 0;
256 }
257
258 for (i = 0; i < ssusb->num_phys; i++) {
259 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
260 if (IS_ERR(ssusb->phys[i])) {
261 dev_err(dev, "failed to get phy-%d\n", i);
262 return PTR_ERR(ssusb->phys[i]);
263 }
264 }
265
266 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
267 ssusb->ippc_base = devm_ioremap_resource(dev, res);
268 if (IS_ERR(ssusb->ippc_base))
269 return PTR_ERR(ssusb->ippc_base);
270
271 ssusb->dr_mode = usb_get_dr_mode(dev);
272 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
273 ssusb->dr_mode = USB_DR_MODE_OTG;
274
275 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
276 goto out;
277
278 /* if host role is supported */
279 ret = ssusb_wakeup_of_property_parse(ssusb, node);
280 if (ret) {
281 dev_err(dev, "failed to parse uwk property\n");
282 return ret;
283 }
284
285 /* optional property, ignore the error if it does not exist */
286 of_property_read_u32(node, "mediatek,u3p-dis-msk",
287 &ssusb->u3p_dis_msk);
288
289 otg_sx->vbus = devm_regulator_get(dev, "vbus");
290 if (IS_ERR(otg_sx->vbus)) {
291 dev_err(dev, "failed to get vbus\n");
292 return PTR_ERR(otg_sx->vbus);
293 }
294
295 if (ssusb->dr_mode == USB_DR_MODE_HOST)
296 goto out;
297
298 /* if dual-role mode is supported */
299 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
300 otg_sx->manual_drd_enabled =
301 of_property_read_bool(node, "enable-manual-drd");
302 otg_sx->role_sw_used = of_property_read_bool(node, "usb-role-switch");
303
304 if (!otg_sx->role_sw_used && of_property_read_bool(node, "extcon")) {
305 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
306 if (IS_ERR(otg_sx->edev)) {
307 dev_err(ssusb->dev, "couldn't get extcon device\n");
308 return PTR_ERR(otg_sx->edev);
309 }
310 }
311
312out:
313 dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
314 ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
315 otg_sx->manual_drd_enabled ? "manual" : "auto");
316
317 return 0;
318}
319
320static int mtu3_probe(struct platform_device *pdev)
321{
322 struct device_node *node = pdev->dev.of_node;
323 struct device *dev = &pdev->dev;
324 struct ssusb_mtk *ssusb;
325 int ret = -ENOMEM;
326
327 /* all elements are set to ZERO as default value */
328 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
329 if (!ssusb)
330 return -ENOMEM;
331
332 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
333 if (ret) {
334 dev_err(dev, "No suitable DMA config available\n");
335 return -ENOTSUPP;
336 }
337
338 platform_set_drvdata(pdev, ssusb);
339 ssusb->dev = dev;
340
341 ret = get_ssusb_rscs(pdev, ssusb);
342 if (ret)
343 return ret;
344
345 ssusb_debugfs_create_root(ssusb);
346
347 /* enable power domain */
348 pm_runtime_enable(dev);
349 pm_runtime_get_sync(dev);
350 device_enable_async_suspend(dev);
351
352 ret = ssusb_rscs_init(ssusb);
353 if (ret)
354 goto comm_init_err;
355
356 ssusb_ip_sw_reset(ssusb);
357
358 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
359 ssusb->dr_mode = USB_DR_MODE_HOST;
360 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
361 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
362
363 /* default as host */
364 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
365
366 switch (ssusb->dr_mode) {
367 case USB_DR_MODE_PERIPHERAL:
368 ret = ssusb_gadget_init(ssusb);
369 if (ret) {
370 dev_err(dev, "failed to initialize gadget\n");
371 goto comm_exit;
372 }
373 break;
374 case USB_DR_MODE_HOST:
375 ret = ssusb_host_init(ssusb, node);
376 if (ret) {
377 dev_err(dev, "failed to initialize host\n");
378 goto comm_exit;
379 }
380 break;
381 case USB_DR_MODE_OTG:
382 ret = ssusb_gadget_init(ssusb);
383 if (ret) {
384 dev_err(dev, "failed to initialize gadget\n");
385 goto comm_exit;
386 }
387
388 ret = ssusb_host_init(ssusb, node);
389 if (ret) {
390 dev_err(dev, "failed to initialize host\n");
391 goto gadget_exit;
392 }
393
394 ret = ssusb_otg_switch_init(ssusb);
395 if (ret) {
396 dev_err(dev, "failed to initialize switch\n");
397 goto host_exit;
398 }
399 break;
400 default:
401 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
402 ret = -EINVAL;
403 goto comm_exit;
404 }
405
406 return 0;
407
408host_exit:
409 ssusb_host_exit(ssusb);
410gadget_exit:
411 ssusb_gadget_exit(ssusb);
412comm_exit:
413 ssusb_rscs_exit(ssusb);
414comm_init_err:
415 pm_runtime_put_sync(dev);
416 pm_runtime_disable(dev);
417 ssusb_debugfs_remove_root(ssusb);
418
419 return ret;
420}
421
422static int mtu3_remove(struct platform_device *pdev)
423{
424 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
425
426 switch (ssusb->dr_mode) {
427 case USB_DR_MODE_PERIPHERAL:
428 ssusb_gadget_exit(ssusb);
429 break;
430 case USB_DR_MODE_HOST:
431 ssusb_host_exit(ssusb);
432 break;
433 case USB_DR_MODE_OTG:
434 ssusb_otg_switch_exit(ssusb);
435 ssusb_gadget_exit(ssusb);
436 ssusb_host_exit(ssusb);
437 break;
438 default:
439 return -EINVAL;
440 }
441
442 ssusb_rscs_exit(ssusb);
443 pm_runtime_put_sync(&pdev->dev);
444 pm_runtime_disable(&pdev->dev);
445 ssusb_debugfs_remove_root(ssusb);
446
447 return 0;
448}
449
450/*
451 * when support dual-role mode, we reject suspend when
452 * it works as device mode;
453 */
454static int __maybe_unused mtu3_suspend(struct device *dev)
455{
456 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
457
458 dev_dbg(dev, "%s\n", __func__);
459
460 /* REVISIT: disconnect it for only device mode? */
461 if (!ssusb->is_host)
462 return 0;
463
464 ssusb_host_disable(ssusb, true);
465 ssusb_phy_power_off(ssusb);
466 ssusb_clks_disable(ssusb);
467 ssusb_wakeup_set(ssusb, true);
468
469 return 0;
470}
471
472static int __maybe_unused mtu3_resume(struct device *dev)
473{
474 struct ssusb_mtk *ssusb = dev_get_drvdata(dev);
475 int ret;
476
477 dev_dbg(dev, "%s\n", __func__);
478
479 if (!ssusb->is_host)
480 return 0;
481
482 ssusb_wakeup_set(ssusb, false);
483 ret = ssusb_clks_enable(ssusb);
484 if (ret)
485 goto clks_err;
486
487 ret = ssusb_phy_power_on(ssusb);
488 if (ret)
489 goto phy_err;
490
491 ssusb_host_enable(ssusb);
492
493 return 0;
494
495phy_err:
496 ssusb_clks_disable(ssusb);
497clks_err:
498 return ret;
499}
500
501static const struct dev_pm_ops mtu3_pm_ops = {
502 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
503};
504
505#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
506
507#ifdef CONFIG_OF
508
509static const struct of_device_id mtu3_of_match[] = {
510 {.compatible = "mediatek,mt8173-mtu3",},
511 {.compatible = "mediatek,mtu3",},
512 {},
513};
514
515MODULE_DEVICE_TABLE(of, mtu3_of_match);
516
517#endif
518
519static struct platform_driver mtu3_driver = {
520 .probe = mtu3_probe,
521 .remove = mtu3_remove,
522 .driver = {
523 .name = MTU3_DRIVER_NAME,
524 .pm = DEV_PM_OPS,
525 .of_match_table = of_match_ptr(mtu3_of_match),
526 },
527};
528module_platform_driver(mtu3_driver);
529
530MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
531MODULE_LICENSE("GPL v2");
532MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");