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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI bus driver for the Topcliff PCH used by Intel SoCs
4 *
5 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
6 */
7
8#include <linux/delay.h>
9#include <linux/pci.h>
10#include <linux/wait.h>
11#include <linux/spi/spi.h>
12#include <linux/interrupt.h>
13#include <linux/sched.h>
14#include <linux/spi/spidev.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18
19#include <linux/dmaengine.h>
20#include <linux/pch_dma.h>
21
22/* Register offsets */
23#define PCH_SPCR 0x00 /* SPI control register */
24#define PCH_SPBRR 0x04 /* SPI baud rate register */
25#define PCH_SPSR 0x08 /* SPI status register */
26#define PCH_SPDWR 0x0C /* SPI write data register */
27#define PCH_SPDRR 0x10 /* SPI read data register */
28#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
29#define PCH_SRST 0x1C /* SPI reset register */
30#define PCH_ADDRESS_SIZE 0x20
31
32#define PCH_SPSR_TFD 0x000007C0
33#define PCH_SPSR_RFD 0x0000F800
34
35#define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
36#define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
37
38#define PCH_RX_THOLD 7
39#define PCH_RX_THOLD_MAX 15
40
41#define PCH_TX_THOLD 2
42
43#define PCH_MAX_BAUDRATE 5000000
44#define PCH_MAX_FIFO_DEPTH 16
45
46#define STATUS_RUNNING 1
47#define STATUS_EXITING 2
48#define PCH_SLEEP_TIME 10
49
50#define SSN_LOW 0x02U
51#define SSN_HIGH 0x03U
52#define SSN_NO_CONTROL 0x00U
53#define PCH_MAX_CS 0xFF
54#define PCI_DEVICE_ID_GE_SPI 0x8816
55
56#define SPCR_SPE_BIT (1 << 0)
57#define SPCR_MSTR_BIT (1 << 1)
58#define SPCR_LSBF_BIT (1 << 4)
59#define SPCR_CPHA_BIT (1 << 5)
60#define SPCR_CPOL_BIT (1 << 6)
61#define SPCR_TFIE_BIT (1 << 8)
62#define SPCR_RFIE_BIT (1 << 9)
63#define SPCR_FIE_BIT (1 << 10)
64#define SPCR_ORIE_BIT (1 << 11)
65#define SPCR_MDFIE_BIT (1 << 12)
66#define SPCR_FICLR_BIT (1 << 24)
67#define SPSR_TFI_BIT (1 << 0)
68#define SPSR_RFI_BIT (1 << 1)
69#define SPSR_FI_BIT (1 << 2)
70#define SPSR_ORF_BIT (1 << 3)
71#define SPBRR_SIZE_BIT (1 << 10)
72
73#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
74 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
75
76#define SPCR_RFIC_FIELD 20
77#define SPCR_TFIC_FIELD 16
78
79#define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
80#define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
81#define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
82
83#define PCH_CLOCK_HZ 50000000
84#define PCH_MAX_SPBR 1023
85
86/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
87#define PCI_DEVICE_ID_ML7213_SPI 0x802c
88#define PCI_DEVICE_ID_ML7223_SPI 0x800F
89#define PCI_DEVICE_ID_ML7831_SPI 0x8816
90
91/*
92 * Set the number of SPI instance max
93 * Intel EG20T PCH : 1ch
94 * LAPIS Semiconductor ML7213 IOH : 2ch
95 * LAPIS Semiconductor ML7223 IOH : 1ch
96 * LAPIS Semiconductor ML7831 IOH : 1ch
97*/
98#define PCH_SPI_MAX_DEV 2
99
100#define PCH_BUF_SIZE 4096
101#define PCH_DMA_TRANS_SIZE 12
102
103static int use_dma = 1;
104
105struct pch_spi_dma_ctrl {
106 struct pci_dev *dma_dev;
107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx;
109 struct pch_dma_slave param_tx;
110 struct pch_dma_slave param_rx;
111 struct dma_chan *chan_tx;
112 struct dma_chan *chan_rx;
113 struct scatterlist *sg_tx_p;
114 struct scatterlist *sg_rx_p;
115 struct scatterlist sg_tx;
116 struct scatterlist sg_rx;
117 int nent;
118 void *tx_buf_virt;
119 void *rx_buf_virt;
120 dma_addr_t tx_buf_dma;
121 dma_addr_t rx_buf_dma;
122};
123/**
124 * struct pch_spi_data - Holds the SPI channel specific details
125 * @io_remap_addr: The remapped PCI base address
126 * @io_base_addr: Base address
127 * @master: Pointer to the SPI master structure
128 * @work: Reference to work queue handler
129 * @wait: Wait queue for waking up upon receiving an
130 * interrupt.
131 * @transfer_complete: Status of SPI Transfer
132 * @bcurrent_msg_processing: Status flag for message processing
133 * @lock: Lock for protecting this structure
134 * @queue: SPI Message queue
135 * @status: Status of the SPI driver
136 * @bpw_len: Length of data to be transferred in bits per
137 * word
138 * @transfer_active: Flag showing active transfer
139 * @tx_index: Transmit data count; for bookkeeping during
140 * transfer
141 * @rx_index: Receive data count; for bookkeeping during
142 * transfer
143 * @pkt_tx_buff: Buffer for data to be transmitted
144 * @pkt_rx_buff: Buffer for received data
145 * @n_curnt_chip: The chip number that this SPI driver currently
146 * operates on
147 * @current_chip: Reference to the current chip that this SPI
148 * driver currently operates on
149 * @current_msg: The current message that this SPI driver is
150 * handling
151 * @cur_trans: The current transfer that this SPI driver is
152 * handling
153 * @board_dat: Reference to the SPI device data structure
154 * @plat_dev: platform_device structure
155 * @ch: SPI channel number
156 * @dma: Local DMA information
157 * @use_dma: True if DMA is to be used
158 * @irq_reg_sts: Status of IRQ registration
159 * @save_total_len: Save length while data is being transferred
160 */
161struct pch_spi_data {
162 void __iomem *io_remap_addr;
163 unsigned long io_base_addr;
164 struct spi_master *master;
165 struct work_struct work;
166 wait_queue_head_t wait;
167 u8 transfer_complete;
168 u8 bcurrent_msg_processing;
169 spinlock_t lock;
170 struct list_head queue;
171 u8 status;
172 u32 bpw_len;
173 u8 transfer_active;
174 u32 tx_index;
175 u32 rx_index;
176 u16 *pkt_tx_buff;
177 u16 *pkt_rx_buff;
178 u8 n_curnt_chip;
179 struct spi_device *current_chip;
180 struct spi_message *current_msg;
181 struct spi_transfer *cur_trans;
182 struct pch_spi_board_data *board_dat;
183 struct platform_device *plat_dev;
184 int ch;
185 struct pch_spi_dma_ctrl dma;
186 int use_dma;
187 u8 irq_reg_sts;
188 int save_total_len;
189};
190
191/**
192 * struct pch_spi_board_data - Holds the SPI device specific details
193 * @pdev: Pointer to the PCI device
194 * @suspend_sts: Status of suspend
195 * @num: The number of SPI device instance
196 */
197struct pch_spi_board_data {
198 struct pci_dev *pdev;
199 u8 suspend_sts;
200 int num;
201};
202
203struct pch_pd_dev_save {
204 int num;
205 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
206 struct pch_spi_board_data *board_dat;
207};
208
209static const struct pci_device_id pch_spi_pcidev_id[] = {
210 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
211 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
212 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
213 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
214 { }
215};
216
217/**
218 * pch_spi_writereg() - Performs register writes
219 * @master: Pointer to struct spi_master.
220 * @idx: Register offset.
221 * @val: Value to be written to register.
222 */
223static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
224{
225 struct pch_spi_data *data = spi_master_get_devdata(master);
226 iowrite32(val, (data->io_remap_addr + idx));
227}
228
229/**
230 * pch_spi_readreg() - Performs register reads
231 * @master: Pointer to struct spi_master.
232 * @idx: Register offset.
233 */
234static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
235{
236 struct pch_spi_data *data = spi_master_get_devdata(master);
237 return ioread32(data->io_remap_addr + idx);
238}
239
240static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
241 u32 set, u32 clr)
242{
243 u32 tmp = pch_spi_readreg(master, idx);
244 tmp = (tmp & ~clr) | set;
245 pch_spi_writereg(master, idx, tmp);
246}
247
248static void pch_spi_set_master_mode(struct spi_master *master)
249{
250 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
251}
252
253/**
254 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
255 * @master: Pointer to struct spi_master.
256 */
257static void pch_spi_clear_fifo(struct spi_master *master)
258{
259 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
260 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
261}
262
263static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
264 void __iomem *io_remap_addr)
265{
266 u32 n_read, tx_index, rx_index, bpw_len;
267 u16 *pkt_rx_buffer, *pkt_tx_buff;
268 int read_cnt;
269 u32 reg_spcr_val;
270 void __iomem *spsr;
271 void __iomem *spdrr;
272 void __iomem *spdwr;
273
274 spsr = io_remap_addr + PCH_SPSR;
275 iowrite32(reg_spsr_val, spsr);
276
277 if (data->transfer_active) {
278 rx_index = data->rx_index;
279 tx_index = data->tx_index;
280 bpw_len = data->bpw_len;
281 pkt_rx_buffer = data->pkt_rx_buff;
282 pkt_tx_buff = data->pkt_tx_buff;
283
284 spdrr = io_remap_addr + PCH_SPDRR;
285 spdwr = io_remap_addr + PCH_SPDWR;
286
287 n_read = PCH_READABLE(reg_spsr_val);
288
289 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
290 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
291 if (tx_index < bpw_len)
292 iowrite32(pkt_tx_buff[tx_index++], spdwr);
293 }
294
295 /* disable RFI if not needed */
296 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
297 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
298 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
299
300 /* reset rx threshold */
301 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
302 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
303
304 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
305 }
306
307 /* update counts */
308 data->tx_index = tx_index;
309 data->rx_index = rx_index;
310
311 /* if transfer complete interrupt */
312 if (reg_spsr_val & SPSR_FI_BIT) {
313 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
314 /* disable interrupts */
315 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
316 PCH_ALL);
317
318 /* transfer is completed;
319 inform pch_spi_process_messages */
320 data->transfer_complete = true;
321 data->transfer_active = false;
322 wake_up(&data->wait);
323 } else {
324 dev_vdbg(&data->master->dev,
325 "%s : Transfer is not completed",
326 __func__);
327 }
328 }
329 }
330}
331
332/**
333 * pch_spi_handler() - Interrupt handler
334 * @irq: The interrupt number.
335 * @dev_id: Pointer to struct pch_spi_board_data.
336 */
337static irqreturn_t pch_spi_handler(int irq, void *dev_id)
338{
339 u32 reg_spsr_val;
340 void __iomem *spsr;
341 void __iomem *io_remap_addr;
342 irqreturn_t ret = IRQ_NONE;
343 struct pch_spi_data *data = dev_id;
344 struct pch_spi_board_data *board_dat = data->board_dat;
345
346 if (board_dat->suspend_sts) {
347 dev_dbg(&board_dat->pdev->dev,
348 "%s returning due to suspend\n", __func__);
349 return IRQ_NONE;
350 }
351
352 io_remap_addr = data->io_remap_addr;
353 spsr = io_remap_addr + PCH_SPSR;
354
355 reg_spsr_val = ioread32(spsr);
356
357 if (reg_spsr_val & SPSR_ORF_BIT) {
358 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
359 if (data->current_msg->complete) {
360 data->transfer_complete = true;
361 data->current_msg->status = -EIO;
362 data->current_msg->complete(data->current_msg->context);
363 data->bcurrent_msg_processing = false;
364 data->current_msg = NULL;
365 data->cur_trans = NULL;
366 }
367 }
368
369 if (data->use_dma)
370 return IRQ_NONE;
371
372 /* Check if the interrupt is for SPI device */
373 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
374 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
375 ret = IRQ_HANDLED;
376 }
377
378 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
379 __func__, ret);
380
381 return ret;
382}
383
384/**
385 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
386 * @master: Pointer to struct spi_master.
387 * @speed_hz: Baud rate.
388 */
389static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
390{
391 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
392
393 /* if baud rate is less than we can support limit it */
394 if (n_spbr > PCH_MAX_SPBR)
395 n_spbr = PCH_MAX_SPBR;
396
397 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
398}
399
400/**
401 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
402 * @master: Pointer to struct spi_master.
403 * @bits_per_word: Bits per word for SPI transfer.
404 */
405static void pch_spi_set_bits_per_word(struct spi_master *master,
406 u8 bits_per_word)
407{
408 if (bits_per_word == 8)
409 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
410 else
411 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
412}
413
414/**
415 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
416 * @spi: Pointer to struct spi_device.
417 */
418static void pch_spi_setup_transfer(struct spi_device *spi)
419{
420 u32 flags = 0;
421
422 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
423 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
424 spi->max_speed_hz);
425 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
426
427 /* set bits per word */
428 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
429
430 if (!(spi->mode & SPI_LSB_FIRST))
431 flags |= SPCR_LSBF_BIT;
432 if (spi->mode & SPI_CPOL)
433 flags |= SPCR_CPOL_BIT;
434 if (spi->mode & SPI_CPHA)
435 flags |= SPCR_CPHA_BIT;
436 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
437 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
438
439 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
440 pch_spi_clear_fifo(spi->master);
441}
442
443/**
444 * pch_spi_reset() - Clears SPI registers
445 * @master: Pointer to struct spi_master.
446 */
447static void pch_spi_reset(struct spi_master *master)
448{
449 /* write 1 to reset SPI */
450 pch_spi_writereg(master, PCH_SRST, 0x1);
451
452 /* clear reset */
453 pch_spi_writereg(master, PCH_SRST, 0x0);
454}
455
456static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
457{
458 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
459 int retval;
460 unsigned long flags;
461
462 /* We won't process any messages if we have been asked to terminate */
463 if (data->status == STATUS_EXITING) {
464 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
465 retval = -ESHUTDOWN;
466 goto err_out;
467 }
468
469 /* If suspended ,return -EINVAL */
470 if (data->board_dat->suspend_sts) {
471 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
472 retval = -EINVAL;
473 goto err_out;
474 }
475
476 /* set status of message */
477 pmsg->actual_length = 0;
478 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
479
480 pmsg->status = -EINPROGRESS;
481 spin_lock_irqsave(&data->lock, flags);
482 /* add message to queue */
483 list_add_tail(&pmsg->queue, &data->queue);
484 spin_unlock_irqrestore(&data->lock, flags);
485
486 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
487
488 schedule_work(&data->work);
489 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
490
491 retval = 0;
492
493err_out:
494 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
495 return retval;
496}
497
498static inline void pch_spi_select_chip(struct pch_spi_data *data,
499 struct spi_device *pspi)
500{
501 if (data->current_chip != NULL) {
502 if (pspi->chip_select != data->n_curnt_chip) {
503 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
504 data->current_chip = NULL;
505 }
506 }
507
508 data->current_chip = pspi;
509
510 data->n_curnt_chip = data->current_chip->chip_select;
511
512 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
513 pch_spi_setup_transfer(pspi);
514}
515
516static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
517{
518 int size;
519 u32 n_writes;
520 int j;
521 struct spi_message *pmsg, *tmp;
522 const u8 *tx_buf;
523 const u16 *tx_sbuf;
524
525 /* set baud rate if needed */
526 if (data->cur_trans->speed_hz) {
527 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
528 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
529 }
530
531 /* set bits per word if needed */
532 if (data->cur_trans->bits_per_word &&
533 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
534 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
535 pch_spi_set_bits_per_word(data->master,
536 data->cur_trans->bits_per_word);
537 *bpw = data->cur_trans->bits_per_word;
538 } else {
539 *bpw = data->current_msg->spi->bits_per_word;
540 }
541
542 /* reset Tx/Rx index */
543 data->tx_index = 0;
544 data->rx_index = 0;
545
546 data->bpw_len = data->cur_trans->len / (*bpw / 8);
547
548 /* find alloc size */
549 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
550
551 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
552 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
553 if (data->pkt_tx_buff != NULL) {
554 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
555 if (!data->pkt_rx_buff) {
556 kfree(data->pkt_tx_buff);
557 data->pkt_tx_buff = NULL;
558 }
559 }
560
561 if (!data->pkt_rx_buff) {
562 /* flush queue and set status of all transfers to -ENOMEM */
563 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
564 pmsg->status = -ENOMEM;
565
566 if (pmsg->complete)
567 pmsg->complete(pmsg->context);
568
569 /* delete from queue */
570 list_del_init(&pmsg->queue);
571 }
572 return;
573 }
574
575 /* copy Tx Data */
576 if (data->cur_trans->tx_buf != NULL) {
577 if (*bpw == 8) {
578 tx_buf = data->cur_trans->tx_buf;
579 for (j = 0; j < data->bpw_len; j++)
580 data->pkt_tx_buff[j] = *tx_buf++;
581 } else {
582 tx_sbuf = data->cur_trans->tx_buf;
583 for (j = 0; j < data->bpw_len; j++)
584 data->pkt_tx_buff[j] = *tx_sbuf++;
585 }
586 }
587
588 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
589 n_writes = data->bpw_len;
590 if (n_writes > PCH_MAX_FIFO_DEPTH)
591 n_writes = PCH_MAX_FIFO_DEPTH;
592
593 dev_dbg(&data->master->dev,
594 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
595 __func__);
596 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
597
598 for (j = 0; j < n_writes; j++)
599 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
600
601 /* update tx_index */
602 data->tx_index = j;
603
604 /* reset transfer complete flag */
605 data->transfer_complete = false;
606 data->transfer_active = true;
607}
608
609static void pch_spi_nomore_transfer(struct pch_spi_data *data)
610{
611 struct spi_message *pmsg, *tmp;
612 dev_dbg(&data->master->dev, "%s called\n", __func__);
613 /* Invoke complete callback
614 * [To the spi core..indicating end of transfer] */
615 data->current_msg->status = 0;
616
617 if (data->current_msg->complete) {
618 dev_dbg(&data->master->dev,
619 "%s:Invoking callback of SPI core\n", __func__);
620 data->current_msg->complete(data->current_msg->context);
621 }
622
623 /* update status in global variable */
624 data->bcurrent_msg_processing = false;
625
626 dev_dbg(&data->master->dev,
627 "%s:data->bcurrent_msg_processing = false\n", __func__);
628
629 data->current_msg = NULL;
630 data->cur_trans = NULL;
631
632 /* check if we have items in list and not suspending
633 * return 1 if list empty */
634 if ((list_empty(&data->queue) == 0) &&
635 (!data->board_dat->suspend_sts) &&
636 (data->status != STATUS_EXITING)) {
637 /* We have some more work to do (either there is more tranint
638 * bpw;sfer requests in the current message or there are
639 *more messages)
640 */
641 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
642 schedule_work(&data->work);
643 } else if (data->board_dat->suspend_sts ||
644 data->status == STATUS_EXITING) {
645 dev_dbg(&data->master->dev,
646 "%s suspend/remove initiated, flushing queue\n",
647 __func__);
648 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
649 pmsg->status = -EIO;
650
651 if (pmsg->complete)
652 pmsg->complete(pmsg->context);
653
654 /* delete from queue */
655 list_del_init(&pmsg->queue);
656 }
657 }
658}
659
660static void pch_spi_set_ir(struct pch_spi_data *data)
661{
662 /* enable interrupts, set threshold, enable SPI */
663 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
664 /* set receive threshold to PCH_RX_THOLD */
665 pch_spi_setclr_reg(data->master, PCH_SPCR,
666 PCH_RX_THOLD << SPCR_RFIC_FIELD |
667 SPCR_FIE_BIT | SPCR_RFIE_BIT |
668 SPCR_ORIE_BIT | SPCR_SPE_BIT,
669 MASK_RFIC_SPCR_BITS | PCH_ALL);
670 else
671 /* set receive threshold to maximum */
672 pch_spi_setclr_reg(data->master, PCH_SPCR,
673 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
674 SPCR_FIE_BIT | SPCR_ORIE_BIT |
675 SPCR_SPE_BIT,
676 MASK_RFIC_SPCR_BITS | PCH_ALL);
677
678 /* Wait until the transfer completes; go to sleep after
679 initiating the transfer. */
680 dev_dbg(&data->master->dev,
681 "%s:waiting for transfer to get over\n", __func__);
682
683 wait_event_interruptible(data->wait, data->transfer_complete);
684
685 /* clear all interrupts */
686 pch_spi_writereg(data->master, PCH_SPSR,
687 pch_spi_readreg(data->master, PCH_SPSR));
688 /* Disable interrupts and SPI transfer */
689 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
690 /* clear FIFO */
691 pch_spi_clear_fifo(data->master);
692}
693
694static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
695{
696 int j;
697 u8 *rx_buf;
698 u16 *rx_sbuf;
699
700 /* copy Rx Data */
701 if (!data->cur_trans->rx_buf)
702 return;
703
704 if (bpw == 8) {
705 rx_buf = data->cur_trans->rx_buf;
706 for (j = 0; j < data->bpw_len; j++)
707 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
708 } else {
709 rx_sbuf = data->cur_trans->rx_buf;
710 for (j = 0; j < data->bpw_len; j++)
711 *rx_sbuf++ = data->pkt_rx_buff[j];
712 }
713}
714
715static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
716{
717 int j;
718 u8 *rx_buf;
719 u16 *rx_sbuf;
720 const u8 *rx_dma_buf;
721 const u16 *rx_dma_sbuf;
722
723 /* copy Rx Data */
724 if (!data->cur_trans->rx_buf)
725 return;
726
727 if (bpw == 8) {
728 rx_buf = data->cur_trans->rx_buf;
729 rx_dma_buf = data->dma.rx_buf_virt;
730 for (j = 0; j < data->bpw_len; j++)
731 *rx_buf++ = *rx_dma_buf++ & 0xFF;
732 data->cur_trans->rx_buf = rx_buf;
733 } else {
734 rx_sbuf = data->cur_trans->rx_buf;
735 rx_dma_sbuf = data->dma.rx_buf_virt;
736 for (j = 0; j < data->bpw_len; j++)
737 *rx_sbuf++ = *rx_dma_sbuf++;
738 data->cur_trans->rx_buf = rx_sbuf;
739 }
740}
741
742static int pch_spi_start_transfer(struct pch_spi_data *data)
743{
744 struct pch_spi_dma_ctrl *dma;
745 unsigned long flags;
746 int rtn;
747
748 dma = &data->dma;
749
750 spin_lock_irqsave(&data->lock, flags);
751
752 /* disable interrupts, SPI set enable */
753 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
754
755 spin_unlock_irqrestore(&data->lock, flags);
756
757 /* Wait until the transfer completes; go to sleep after
758 initiating the transfer. */
759 dev_dbg(&data->master->dev,
760 "%s:waiting for transfer to get over\n", __func__);
761 rtn = wait_event_interruptible_timeout(data->wait,
762 data->transfer_complete,
763 msecs_to_jiffies(2 * HZ));
764 if (!rtn)
765 dev_err(&data->master->dev,
766 "%s wait-event timeout\n", __func__);
767
768 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
769 DMA_FROM_DEVICE);
770
771 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
772 DMA_FROM_DEVICE);
773 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
774
775 async_tx_ack(dma->desc_rx);
776 async_tx_ack(dma->desc_tx);
777 kfree(dma->sg_tx_p);
778 kfree(dma->sg_rx_p);
779
780 spin_lock_irqsave(&data->lock, flags);
781
782 /* clear fifo threshold, disable interrupts, disable SPI transfer */
783 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
784 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
785 SPCR_SPE_BIT);
786 /* clear all interrupts */
787 pch_spi_writereg(data->master, PCH_SPSR,
788 pch_spi_readreg(data->master, PCH_SPSR));
789 /* clear FIFO */
790 pch_spi_clear_fifo(data->master);
791
792 spin_unlock_irqrestore(&data->lock, flags);
793
794 return rtn;
795}
796
797static void pch_dma_rx_complete(void *arg)
798{
799 struct pch_spi_data *data = arg;
800
801 /* transfer is completed;inform pch_spi_process_messages_dma */
802 data->transfer_complete = true;
803 wake_up_interruptible(&data->wait);
804}
805
806static bool pch_spi_filter(struct dma_chan *chan, void *slave)
807{
808 struct pch_dma_slave *param = slave;
809
810 if ((chan->chan_id == param->chan_id) &&
811 (param->dma_dev == chan->device->dev)) {
812 chan->private = param;
813 return true;
814 } else {
815 return false;
816 }
817}
818
819static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
820{
821 dma_cap_mask_t mask;
822 struct dma_chan *chan;
823 struct pci_dev *dma_dev;
824 struct pch_dma_slave *param;
825 struct pch_spi_dma_ctrl *dma;
826 unsigned int width;
827
828 if (bpw == 8)
829 width = PCH_DMA_WIDTH_1_BYTE;
830 else
831 width = PCH_DMA_WIDTH_2_BYTES;
832
833 dma = &data->dma;
834 dma_cap_zero(mask);
835 dma_cap_set(DMA_SLAVE, mask);
836
837 /* Get DMA's dev information */
838 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
839 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
840
841 /* Set Tx DMA */
842 param = &dma->param_tx;
843 param->dma_dev = &dma_dev->dev;
844 param->chan_id = data->ch * 2; /* Tx = 0, 2 */
845 param->tx_reg = data->io_base_addr + PCH_SPDWR;
846 param->width = width;
847 chan = dma_request_channel(mask, pch_spi_filter, param);
848 if (!chan) {
849 dev_err(&data->master->dev,
850 "ERROR: dma_request_channel FAILS(Tx)\n");
851 goto out;
852 }
853 dma->chan_tx = chan;
854
855 /* Set Rx DMA */
856 param = &dma->param_rx;
857 param->dma_dev = &dma_dev->dev;
858 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */
859 param->rx_reg = data->io_base_addr + PCH_SPDRR;
860 param->width = width;
861 chan = dma_request_channel(mask, pch_spi_filter, param);
862 if (!chan) {
863 dev_err(&data->master->dev,
864 "ERROR: dma_request_channel FAILS(Rx)\n");
865 dma_release_channel(dma->chan_tx);
866 dma->chan_tx = NULL;
867 goto out;
868 }
869 dma->chan_rx = chan;
870
871 dma->dma_dev = dma_dev;
872 return;
873out:
874 pci_dev_put(dma_dev);
875 data->use_dma = 0;
876}
877
878static void pch_spi_release_dma(struct pch_spi_data *data)
879{
880 struct pch_spi_dma_ctrl *dma;
881
882 dma = &data->dma;
883 if (dma->chan_tx) {
884 dma_release_channel(dma->chan_tx);
885 dma->chan_tx = NULL;
886 }
887 if (dma->chan_rx) {
888 dma_release_channel(dma->chan_rx);
889 dma->chan_rx = NULL;
890 }
891
892 pci_dev_put(dma->dma_dev);
893}
894
895static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
896{
897 const u8 *tx_buf;
898 const u16 *tx_sbuf;
899 u8 *tx_dma_buf;
900 u16 *tx_dma_sbuf;
901 struct scatterlist *sg;
902 struct dma_async_tx_descriptor *desc_tx;
903 struct dma_async_tx_descriptor *desc_rx;
904 int num;
905 int i;
906 int size;
907 int rem;
908 int head;
909 unsigned long flags;
910 struct pch_spi_dma_ctrl *dma;
911
912 dma = &data->dma;
913
914 /* set baud rate if needed */
915 if (data->cur_trans->speed_hz) {
916 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
917 spin_lock_irqsave(&data->lock, flags);
918 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
919 spin_unlock_irqrestore(&data->lock, flags);
920 }
921
922 /* set bits per word if needed */
923 if (data->cur_trans->bits_per_word &&
924 (data->current_msg->spi->bits_per_word !=
925 data->cur_trans->bits_per_word)) {
926 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
927 spin_lock_irqsave(&data->lock, flags);
928 pch_spi_set_bits_per_word(data->master,
929 data->cur_trans->bits_per_word);
930 spin_unlock_irqrestore(&data->lock, flags);
931 *bpw = data->cur_trans->bits_per_word;
932 } else {
933 *bpw = data->current_msg->spi->bits_per_word;
934 }
935 data->bpw_len = data->cur_trans->len / (*bpw / 8);
936
937 if (data->bpw_len > PCH_BUF_SIZE) {
938 data->bpw_len = PCH_BUF_SIZE;
939 data->cur_trans->len -= PCH_BUF_SIZE;
940 }
941
942 /* copy Tx Data */
943 if (data->cur_trans->tx_buf != NULL) {
944 if (*bpw == 8) {
945 tx_buf = data->cur_trans->tx_buf;
946 tx_dma_buf = dma->tx_buf_virt;
947 for (i = 0; i < data->bpw_len; i++)
948 *tx_dma_buf++ = *tx_buf++;
949 } else {
950 tx_sbuf = data->cur_trans->tx_buf;
951 tx_dma_sbuf = dma->tx_buf_virt;
952 for (i = 0; i < data->bpw_len; i++)
953 *tx_dma_sbuf++ = *tx_sbuf++;
954 }
955 }
956
957 /* Calculate Rx parameter for DMA transmitting */
958 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
959 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
960 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
961 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
962 } else {
963 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
964 rem = PCH_DMA_TRANS_SIZE;
965 }
966 size = PCH_DMA_TRANS_SIZE;
967 } else {
968 num = 1;
969 size = data->bpw_len;
970 rem = data->bpw_len;
971 }
972 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
973 __func__, num, size, rem);
974 spin_lock_irqsave(&data->lock, flags);
975
976 /* set receive fifo threshold and transmit fifo threshold */
977 pch_spi_setclr_reg(data->master, PCH_SPCR,
978 ((size - 1) << SPCR_RFIC_FIELD) |
979 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
980 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
981
982 spin_unlock_irqrestore(&data->lock, flags);
983
984 /* RX */
985 dma->sg_rx_p = kmalloc_array(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
986 if (!dma->sg_rx_p)
987 return;
988
989 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
990 /* offset, length setting */
991 sg = dma->sg_rx_p;
992 for (i = 0; i < num; i++, sg++) {
993 if (i == (num - 2)) {
994 sg->offset = size * i;
995 sg->offset = sg->offset * (*bpw / 8);
996 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
997 sg->offset);
998 sg_dma_len(sg) = rem;
999 } else if (i == (num - 1)) {
1000 sg->offset = size * (i - 1) + rem;
1001 sg->offset = sg->offset * (*bpw / 8);
1002 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1003 sg->offset);
1004 sg_dma_len(sg) = size;
1005 } else {
1006 sg->offset = size * i;
1007 sg->offset = sg->offset * (*bpw / 8);
1008 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1009 sg->offset);
1010 sg_dma_len(sg) = size;
1011 }
1012 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1013 }
1014 sg = dma->sg_rx_p;
1015 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1016 num, DMA_DEV_TO_MEM,
1017 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1018 if (!desc_rx) {
1019 dev_err(&data->master->dev,
1020 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1021 return;
1022 }
1023 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1024 desc_rx->callback = pch_dma_rx_complete;
1025 desc_rx->callback_param = data;
1026 dma->nent = num;
1027 dma->desc_rx = desc_rx;
1028
1029 /* Calculate Tx parameter for DMA transmitting */
1030 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1031 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1032 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1033 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1034 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1035 } else {
1036 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1037 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1038 PCH_DMA_TRANS_SIZE - head;
1039 }
1040 size = PCH_DMA_TRANS_SIZE;
1041 } else {
1042 num = 1;
1043 size = data->bpw_len;
1044 rem = data->bpw_len;
1045 head = 0;
1046 }
1047
1048 dma->sg_tx_p = kmalloc_array(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1049 if (!dma->sg_tx_p)
1050 return;
1051
1052 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1053 /* offset, length setting */
1054 sg = dma->sg_tx_p;
1055 for (i = 0; i < num; i++, sg++) {
1056 if (i == 0) {
1057 sg->offset = 0;
1058 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1059 sg->offset);
1060 sg_dma_len(sg) = size + head;
1061 } else if (i == (num - 1)) {
1062 sg->offset = head + size * i;
1063 sg->offset = sg->offset * (*bpw / 8);
1064 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1065 sg->offset);
1066 sg_dma_len(sg) = rem;
1067 } else {
1068 sg->offset = head + size * i;
1069 sg->offset = sg->offset * (*bpw / 8);
1070 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1071 sg->offset);
1072 sg_dma_len(sg) = size;
1073 }
1074 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1075 }
1076 sg = dma->sg_tx_p;
1077 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1078 sg, num, DMA_MEM_TO_DEV,
1079 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1080 if (!desc_tx) {
1081 dev_err(&data->master->dev,
1082 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1083 return;
1084 }
1085 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1086 desc_tx->callback = NULL;
1087 desc_tx->callback_param = data;
1088 dma->nent = num;
1089 dma->desc_tx = desc_tx;
1090
1091 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1092
1093 spin_lock_irqsave(&data->lock, flags);
1094 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1095 desc_rx->tx_submit(desc_rx);
1096 desc_tx->tx_submit(desc_tx);
1097 spin_unlock_irqrestore(&data->lock, flags);
1098
1099 /* reset transfer complete flag */
1100 data->transfer_complete = false;
1101}
1102
1103static void pch_spi_process_messages(struct work_struct *pwork)
1104{
1105 struct spi_message *pmsg, *tmp;
1106 struct pch_spi_data *data;
1107 int bpw;
1108
1109 data = container_of(pwork, struct pch_spi_data, work);
1110 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1111
1112 spin_lock(&data->lock);
1113 /* check if suspend has been initiated;if yes flush queue */
1114 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1115 dev_dbg(&data->master->dev,
1116 "%s suspend/remove initiated, flushing queue\n", __func__);
1117 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1118 pmsg->status = -EIO;
1119
1120 if (pmsg->complete) {
1121 spin_unlock(&data->lock);
1122 pmsg->complete(pmsg->context);
1123 spin_lock(&data->lock);
1124 }
1125
1126 /* delete from queue */
1127 list_del_init(&pmsg->queue);
1128 }
1129
1130 spin_unlock(&data->lock);
1131 return;
1132 }
1133
1134 data->bcurrent_msg_processing = true;
1135 dev_dbg(&data->master->dev,
1136 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1137
1138 /* Get the message from the queue and delete it from there. */
1139 data->current_msg = list_entry(data->queue.next, struct spi_message,
1140 queue);
1141
1142 list_del_init(&data->current_msg->queue);
1143
1144 data->current_msg->status = 0;
1145
1146 pch_spi_select_chip(data, data->current_msg->spi);
1147
1148 spin_unlock(&data->lock);
1149
1150 if (data->use_dma)
1151 pch_spi_request_dma(data,
1152 data->current_msg->spi->bits_per_word);
1153 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1154 do {
1155 int cnt;
1156 /* If we are already processing a message get the next
1157 transfer structure from the message otherwise retrieve
1158 the 1st transfer request from the message. */
1159 spin_lock(&data->lock);
1160 if (data->cur_trans == NULL) {
1161 data->cur_trans =
1162 list_entry(data->current_msg->transfers.next,
1163 struct spi_transfer, transfer_list);
1164 dev_dbg(&data->master->dev,
1165 "%s :Getting 1st transfer message\n",
1166 __func__);
1167 } else {
1168 data->cur_trans =
1169 list_entry(data->cur_trans->transfer_list.next,
1170 struct spi_transfer, transfer_list);
1171 dev_dbg(&data->master->dev,
1172 "%s :Getting next transfer message\n",
1173 __func__);
1174 }
1175 spin_unlock(&data->lock);
1176
1177 if (!data->cur_trans->len)
1178 goto out;
1179 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1180 data->save_total_len = data->cur_trans->len;
1181 if (data->use_dma) {
1182 int i;
1183 char *save_rx_buf = data->cur_trans->rx_buf;
1184
1185 for (i = 0; i < cnt; i++) {
1186 pch_spi_handle_dma(data, &bpw);
1187 if (!pch_spi_start_transfer(data)) {
1188 data->transfer_complete = true;
1189 data->current_msg->status = -EIO;
1190 data->current_msg->complete
1191 (data->current_msg->context);
1192 data->bcurrent_msg_processing = false;
1193 data->current_msg = NULL;
1194 data->cur_trans = NULL;
1195 goto out;
1196 }
1197 pch_spi_copy_rx_data_for_dma(data, bpw);
1198 }
1199 data->cur_trans->rx_buf = save_rx_buf;
1200 } else {
1201 pch_spi_set_tx(data, &bpw);
1202 pch_spi_set_ir(data);
1203 pch_spi_copy_rx_data(data, bpw);
1204 kfree(data->pkt_rx_buff);
1205 data->pkt_rx_buff = NULL;
1206 kfree(data->pkt_tx_buff);
1207 data->pkt_tx_buff = NULL;
1208 }
1209 /* increment message count */
1210 data->cur_trans->len = data->save_total_len;
1211 data->current_msg->actual_length += data->cur_trans->len;
1212
1213 dev_dbg(&data->master->dev,
1214 "%s:data->current_msg->actual_length=%d\n",
1215 __func__, data->current_msg->actual_length);
1216
1217 spi_transfer_delay_exec(data->cur_trans);
1218
1219 spin_lock(&data->lock);
1220
1221 /* No more transfer in this message. */
1222 if ((data->cur_trans->transfer_list.next) ==
1223 &(data->current_msg->transfers)) {
1224 pch_spi_nomore_transfer(data);
1225 }
1226
1227 spin_unlock(&data->lock);
1228
1229 } while (data->cur_trans != NULL);
1230
1231out:
1232 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1233 if (data->use_dma)
1234 pch_spi_release_dma(data);
1235}
1236
1237static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1238 struct pch_spi_data *data)
1239{
1240 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1241
1242 flush_work(&data->work);
1243}
1244
1245static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1246 struct pch_spi_data *data)
1247{
1248 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1249
1250 /* reset PCH SPI h/w */
1251 pch_spi_reset(data->master);
1252 dev_dbg(&board_dat->pdev->dev,
1253 "%s pch_spi_reset invoked successfully\n", __func__);
1254
1255 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1256
1257 return 0;
1258}
1259
1260static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1261 struct pch_spi_data *data)
1262{
1263 struct pch_spi_dma_ctrl *dma;
1264
1265 dma = &data->dma;
1266 if (dma->tx_buf_dma)
1267 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1268 dma->tx_buf_virt, dma->tx_buf_dma);
1269 if (dma->rx_buf_dma)
1270 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1271 dma->rx_buf_virt, dma->rx_buf_dma);
1272}
1273
1274static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1275 struct pch_spi_data *data)
1276{
1277 struct pch_spi_dma_ctrl *dma;
1278 int ret;
1279
1280 dma = &data->dma;
1281 ret = 0;
1282 /* Get Consistent memory for Tx DMA */
1283 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1284 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1285 if (!dma->tx_buf_virt)
1286 ret = -ENOMEM;
1287
1288 /* Get Consistent memory for Rx DMA */
1289 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1290 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1291 if (!dma->rx_buf_virt)
1292 ret = -ENOMEM;
1293
1294 return ret;
1295}
1296
1297static int pch_spi_pd_probe(struct platform_device *plat_dev)
1298{
1299 int ret;
1300 struct spi_master *master;
1301 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1302 struct pch_spi_data *data;
1303
1304 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1305
1306 master = spi_alloc_master(&board_dat->pdev->dev,
1307 sizeof(struct pch_spi_data));
1308 if (!master) {
1309 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1310 plat_dev->id);
1311 return -ENOMEM;
1312 }
1313
1314 data = spi_master_get_devdata(master);
1315 data->master = master;
1316
1317 platform_set_drvdata(plat_dev, data);
1318
1319 /* baseaddress + address offset) */
1320 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1321 PCH_ADDRESS_SIZE * plat_dev->id;
1322 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1323 if (!data->io_remap_addr) {
1324 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1325 ret = -ENOMEM;
1326 goto err_pci_iomap;
1327 }
1328 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1329
1330 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1331 plat_dev->id, data->io_remap_addr);
1332
1333 /* initialize members of SPI master */
1334 master->num_chipselect = PCH_MAX_CS;
1335 master->transfer = pch_spi_transfer;
1336 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1337 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1338 master->max_speed_hz = PCH_MAX_BAUDRATE;
1339 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1340
1341 data->board_dat = board_dat;
1342 data->plat_dev = plat_dev;
1343 data->n_curnt_chip = 255;
1344 data->status = STATUS_RUNNING;
1345 data->ch = plat_dev->id;
1346 data->use_dma = use_dma;
1347
1348 INIT_LIST_HEAD(&data->queue);
1349 spin_lock_init(&data->lock);
1350 INIT_WORK(&data->work, pch_spi_process_messages);
1351 init_waitqueue_head(&data->wait);
1352
1353 ret = pch_spi_get_resources(board_dat, data);
1354 if (ret) {
1355 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1356 goto err_spi_get_resources;
1357 }
1358
1359 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1360 IRQF_SHARED, KBUILD_MODNAME, data);
1361 if (ret) {
1362 dev_err(&plat_dev->dev,
1363 "%s request_irq failed\n", __func__);
1364 goto err_request_irq;
1365 }
1366 data->irq_reg_sts = true;
1367
1368 pch_spi_set_master_mode(master);
1369
1370 if (use_dma) {
1371 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1372 ret = pch_alloc_dma_buf(board_dat, data);
1373 if (ret)
1374 goto err_spi_register_master;
1375 }
1376
1377 ret = spi_register_master(master);
1378 if (ret != 0) {
1379 dev_err(&plat_dev->dev,
1380 "%s spi_register_master FAILED\n", __func__);
1381 goto err_spi_register_master;
1382 }
1383
1384 return 0;
1385
1386err_spi_register_master:
1387 pch_free_dma_buf(board_dat, data);
1388 free_irq(board_dat->pdev->irq, data);
1389err_request_irq:
1390 pch_spi_free_resources(board_dat, data);
1391err_spi_get_resources:
1392 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1393err_pci_iomap:
1394 spi_master_put(master);
1395
1396 return ret;
1397}
1398
1399static int pch_spi_pd_remove(struct platform_device *plat_dev)
1400{
1401 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1402 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1403 int count;
1404 unsigned long flags;
1405
1406 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1407 __func__, plat_dev->id, board_dat->pdev->irq);
1408
1409 if (use_dma)
1410 pch_free_dma_buf(board_dat, data);
1411
1412 /* check for any pending messages; no action is taken if the queue
1413 * is still full; but at least we tried. Unload anyway */
1414 count = 500;
1415 spin_lock_irqsave(&data->lock, flags);
1416 data->status = STATUS_EXITING;
1417 while ((list_empty(&data->queue) == 0) && --count) {
1418 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1419 __func__);
1420 spin_unlock_irqrestore(&data->lock, flags);
1421 msleep(PCH_SLEEP_TIME);
1422 spin_lock_irqsave(&data->lock, flags);
1423 }
1424 spin_unlock_irqrestore(&data->lock, flags);
1425
1426 pch_spi_free_resources(board_dat, data);
1427 /* disable interrupts & free IRQ */
1428 if (data->irq_reg_sts) {
1429 /* disable interrupts */
1430 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1431 data->irq_reg_sts = false;
1432 free_irq(board_dat->pdev->irq, data);
1433 }
1434
1435 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1436 spi_unregister_master(data->master);
1437
1438 return 0;
1439}
1440#ifdef CONFIG_PM
1441static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1442 pm_message_t state)
1443{
1444 u8 count;
1445 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1446 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1447
1448 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1449
1450 if (!board_dat) {
1451 dev_err(&pd_dev->dev,
1452 "%s pci_get_drvdata returned NULL\n", __func__);
1453 return -EFAULT;
1454 }
1455
1456 /* check if the current message is processed:
1457 Only after thats done the transfer will be suspended */
1458 count = 255;
1459 while ((--count) > 0) {
1460 if (!(data->bcurrent_msg_processing))
1461 break;
1462 msleep(PCH_SLEEP_TIME);
1463 }
1464
1465 /* Free IRQ */
1466 if (data->irq_reg_sts) {
1467 /* disable all interrupts */
1468 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1469 pch_spi_reset(data->master);
1470 free_irq(board_dat->pdev->irq, data);
1471
1472 data->irq_reg_sts = false;
1473 dev_dbg(&pd_dev->dev,
1474 "%s free_irq invoked successfully.\n", __func__);
1475 }
1476
1477 return 0;
1478}
1479
1480static int pch_spi_pd_resume(struct platform_device *pd_dev)
1481{
1482 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1483 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1484 int retval;
1485
1486 if (!board_dat) {
1487 dev_err(&pd_dev->dev,
1488 "%s pci_get_drvdata returned NULL\n", __func__);
1489 return -EFAULT;
1490 }
1491
1492 if (!data->irq_reg_sts) {
1493 /* register IRQ */
1494 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1495 IRQF_SHARED, KBUILD_MODNAME, data);
1496 if (retval < 0) {
1497 dev_err(&pd_dev->dev,
1498 "%s request_irq failed\n", __func__);
1499 return retval;
1500 }
1501
1502 /* reset PCH SPI h/w */
1503 pch_spi_reset(data->master);
1504 pch_spi_set_master_mode(data->master);
1505 data->irq_reg_sts = true;
1506 }
1507 return 0;
1508}
1509#else
1510#define pch_spi_pd_suspend NULL
1511#define pch_spi_pd_resume NULL
1512#endif
1513
1514static struct platform_driver pch_spi_pd_driver = {
1515 .driver = {
1516 .name = "pch-spi",
1517 },
1518 .probe = pch_spi_pd_probe,
1519 .remove = pch_spi_pd_remove,
1520 .suspend = pch_spi_pd_suspend,
1521 .resume = pch_spi_pd_resume
1522};
1523
1524static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1525{
1526 struct pch_spi_board_data *board_dat;
1527 struct platform_device *pd_dev = NULL;
1528 int retval;
1529 int i;
1530 struct pch_pd_dev_save *pd_dev_save;
1531
1532 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1533 if (!pd_dev_save)
1534 return -ENOMEM;
1535
1536 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1537 if (!board_dat) {
1538 retval = -ENOMEM;
1539 goto err_no_mem;
1540 }
1541
1542 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1543 if (retval) {
1544 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1545 goto pci_request_regions;
1546 }
1547
1548 board_dat->pdev = pdev;
1549 board_dat->num = id->driver_data;
1550 pd_dev_save->num = id->driver_data;
1551 pd_dev_save->board_dat = board_dat;
1552
1553 retval = pci_enable_device(pdev);
1554 if (retval) {
1555 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1556 goto pci_enable_device;
1557 }
1558
1559 for (i = 0; i < board_dat->num; i++) {
1560 pd_dev = platform_device_alloc("pch-spi", i);
1561 if (!pd_dev) {
1562 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1563 retval = -ENOMEM;
1564 goto err_platform_device;
1565 }
1566 pd_dev_save->pd_save[i] = pd_dev;
1567 pd_dev->dev.parent = &pdev->dev;
1568
1569 retval = platform_device_add_data(pd_dev, board_dat,
1570 sizeof(*board_dat));
1571 if (retval) {
1572 dev_err(&pdev->dev,
1573 "platform_device_add_data failed\n");
1574 platform_device_put(pd_dev);
1575 goto err_platform_device;
1576 }
1577
1578 retval = platform_device_add(pd_dev);
1579 if (retval) {
1580 dev_err(&pdev->dev, "platform_device_add failed\n");
1581 platform_device_put(pd_dev);
1582 goto err_platform_device;
1583 }
1584 }
1585
1586 pci_set_drvdata(pdev, pd_dev_save);
1587
1588 return 0;
1589
1590err_platform_device:
1591 while (--i >= 0)
1592 platform_device_unregister(pd_dev_save->pd_save[i]);
1593 pci_disable_device(pdev);
1594pci_enable_device:
1595 pci_release_regions(pdev);
1596pci_request_regions:
1597 kfree(board_dat);
1598err_no_mem:
1599 kfree(pd_dev_save);
1600
1601 return retval;
1602}
1603
1604static void pch_spi_remove(struct pci_dev *pdev)
1605{
1606 int i;
1607 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1608
1609 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1610
1611 for (i = 0; i < pd_dev_save->num; i++)
1612 platform_device_unregister(pd_dev_save->pd_save[i]);
1613
1614 pci_disable_device(pdev);
1615 pci_release_regions(pdev);
1616 kfree(pd_dev_save->board_dat);
1617 kfree(pd_dev_save);
1618}
1619
1620static int __maybe_unused pch_spi_suspend(struct device *dev)
1621{
1622 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1623
1624 dev_dbg(dev, "%s ENTRY\n", __func__);
1625
1626 pd_dev_save->board_dat->suspend_sts = true;
1627
1628 return 0;
1629}
1630
1631static int __maybe_unused pch_spi_resume(struct device *dev)
1632{
1633 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1634
1635 dev_dbg(dev, "%s ENTRY\n", __func__);
1636
1637 /* set suspend status to false */
1638 pd_dev_save->board_dat->suspend_sts = false;
1639
1640 return 0;
1641}
1642
1643static SIMPLE_DEV_PM_OPS(pch_spi_pm_ops, pch_spi_suspend, pch_spi_resume);
1644
1645static struct pci_driver pch_spi_pcidev_driver = {
1646 .name = "pch_spi",
1647 .id_table = pch_spi_pcidev_id,
1648 .probe = pch_spi_probe,
1649 .remove = pch_spi_remove,
1650 .driver.pm = &pch_spi_pm_ops,
1651};
1652
1653static int __init pch_spi_init(void)
1654{
1655 int ret;
1656 ret = platform_driver_register(&pch_spi_pd_driver);
1657 if (ret)
1658 return ret;
1659
1660 ret = pci_register_driver(&pch_spi_pcidev_driver);
1661 if (ret) {
1662 platform_driver_unregister(&pch_spi_pd_driver);
1663 return ret;
1664 }
1665
1666 return 0;
1667}
1668module_init(pch_spi_init);
1669
1670static void __exit pch_spi_exit(void)
1671{
1672 pci_unregister_driver(&pch_spi_pcidev_driver);
1673 platform_driver_unregister(&pch_spi_pd_driver);
1674}
1675module_exit(pch_spi_exit);
1676
1677module_param(use_dma, int, 0644);
1678MODULE_PARM_DESC(use_dma,
1679 "to use DMA for data transfers pass 1 else 0; default 1");
1680
1681MODULE_LICENSE("GPL");
1682MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1683MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1684
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI bus driver for the Topcliff PCH used by Intel SoCs
4 *
5 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
6 */
7
8#include <linux/delay.h>
9#include <linux/pci.h>
10#include <linux/wait.h>
11#include <linux/spi/spi.h>
12#include <linux/interrupt.h>
13#include <linux/sched.h>
14#include <linux/spi/spidev.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18
19#include <linux/dmaengine.h>
20#include <linux/pch_dma.h>
21
22/* Register offsets */
23#define PCH_SPCR 0x00 /* SPI control register */
24#define PCH_SPBRR 0x04 /* SPI baud rate register */
25#define PCH_SPSR 0x08 /* SPI status register */
26#define PCH_SPDWR 0x0C /* SPI write data register */
27#define PCH_SPDRR 0x10 /* SPI read data register */
28#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
29#define PCH_SRST 0x1C /* SPI reset register */
30#define PCH_ADDRESS_SIZE 0x20
31
32#define PCH_SPSR_TFD 0x000007C0
33#define PCH_SPSR_RFD 0x0000F800
34
35#define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
36#define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
37
38#define PCH_RX_THOLD 7
39#define PCH_RX_THOLD_MAX 15
40
41#define PCH_TX_THOLD 2
42
43#define PCH_MAX_BAUDRATE 5000000
44#define PCH_MAX_FIFO_DEPTH 16
45
46#define STATUS_RUNNING 1
47#define STATUS_EXITING 2
48#define PCH_SLEEP_TIME 10
49
50#define SSN_LOW 0x02U
51#define SSN_HIGH 0x03U
52#define SSN_NO_CONTROL 0x00U
53#define PCH_MAX_CS 0xFF
54#define PCI_DEVICE_ID_GE_SPI 0x8816
55
56#define SPCR_SPE_BIT (1 << 0)
57#define SPCR_MSTR_BIT (1 << 1)
58#define SPCR_LSBF_BIT (1 << 4)
59#define SPCR_CPHA_BIT (1 << 5)
60#define SPCR_CPOL_BIT (1 << 6)
61#define SPCR_TFIE_BIT (1 << 8)
62#define SPCR_RFIE_BIT (1 << 9)
63#define SPCR_FIE_BIT (1 << 10)
64#define SPCR_ORIE_BIT (1 << 11)
65#define SPCR_MDFIE_BIT (1 << 12)
66#define SPCR_FICLR_BIT (1 << 24)
67#define SPSR_TFI_BIT (1 << 0)
68#define SPSR_RFI_BIT (1 << 1)
69#define SPSR_FI_BIT (1 << 2)
70#define SPSR_ORF_BIT (1 << 3)
71#define SPBRR_SIZE_BIT (1 << 10)
72
73#define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
74 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
75
76#define SPCR_RFIC_FIELD 20
77#define SPCR_TFIC_FIELD 16
78
79#define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
80#define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
81#define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
82
83#define PCH_CLOCK_HZ 50000000
84#define PCH_MAX_SPBR 1023
85
86/* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
87#define PCI_DEVICE_ID_ML7213_SPI 0x802c
88#define PCI_DEVICE_ID_ML7223_SPI 0x800F
89#define PCI_DEVICE_ID_ML7831_SPI 0x8816
90
91/*
92 * Set the number of SPI instance max
93 * Intel EG20T PCH : 1ch
94 * LAPIS Semiconductor ML7213 IOH : 2ch
95 * LAPIS Semiconductor ML7223 IOH : 1ch
96 * LAPIS Semiconductor ML7831 IOH : 1ch
97*/
98#define PCH_SPI_MAX_DEV 2
99
100#define PCH_BUF_SIZE 4096
101#define PCH_DMA_TRANS_SIZE 12
102
103static int use_dma = 1;
104
105struct pch_spi_dma_ctrl {
106 struct dma_async_tx_descriptor *desc_tx;
107 struct dma_async_tx_descriptor *desc_rx;
108 struct pch_dma_slave param_tx;
109 struct pch_dma_slave param_rx;
110 struct dma_chan *chan_tx;
111 struct dma_chan *chan_rx;
112 struct scatterlist *sg_tx_p;
113 struct scatterlist *sg_rx_p;
114 struct scatterlist sg_tx;
115 struct scatterlist sg_rx;
116 int nent;
117 void *tx_buf_virt;
118 void *rx_buf_virt;
119 dma_addr_t tx_buf_dma;
120 dma_addr_t rx_buf_dma;
121};
122/**
123 * struct pch_spi_data - Holds the SPI channel specific details
124 * @io_remap_addr: The remapped PCI base address
125 * @master: Pointer to the SPI master structure
126 * @work: Reference to work queue handler
127 * @wait: Wait queue for waking up upon receiving an
128 * interrupt.
129 * @transfer_complete: Status of SPI Transfer
130 * @bcurrent_msg_processing: Status flag for message processing
131 * @lock: Lock for protecting this structure
132 * @queue: SPI Message queue
133 * @status: Status of the SPI driver
134 * @bpw_len: Length of data to be transferred in bits per
135 * word
136 * @transfer_active: Flag showing active transfer
137 * @tx_index: Transmit data count; for bookkeeping during
138 * transfer
139 * @rx_index: Receive data count; for bookkeeping during
140 * transfer
141 * @tx_buff: Buffer for data to be transmitted
142 * @rx_index: Buffer for Received data
143 * @n_curnt_chip: The chip number that this SPI driver currently
144 * operates on
145 * @current_chip: Reference to the current chip that this SPI
146 * driver currently operates on
147 * @current_msg: The current message that this SPI driver is
148 * handling
149 * @cur_trans: The current transfer that this SPI driver is
150 * handling
151 * @board_dat: Reference to the SPI device data structure
152 * @plat_dev: platform_device structure
153 * @ch: SPI channel number
154 * @irq_reg_sts: Status of IRQ registration
155 */
156struct pch_spi_data {
157 void __iomem *io_remap_addr;
158 unsigned long io_base_addr;
159 struct spi_master *master;
160 struct work_struct work;
161 wait_queue_head_t wait;
162 u8 transfer_complete;
163 u8 bcurrent_msg_processing;
164 spinlock_t lock;
165 struct list_head queue;
166 u8 status;
167 u32 bpw_len;
168 u8 transfer_active;
169 u32 tx_index;
170 u32 rx_index;
171 u16 *pkt_tx_buff;
172 u16 *pkt_rx_buff;
173 u8 n_curnt_chip;
174 struct spi_device *current_chip;
175 struct spi_message *current_msg;
176 struct spi_transfer *cur_trans;
177 struct pch_spi_board_data *board_dat;
178 struct platform_device *plat_dev;
179 int ch;
180 struct pch_spi_dma_ctrl dma;
181 int use_dma;
182 u8 irq_reg_sts;
183 int save_total_len;
184};
185
186/**
187 * struct pch_spi_board_data - Holds the SPI device specific details
188 * @pdev: Pointer to the PCI device
189 * @suspend_sts: Status of suspend
190 * @num: The number of SPI device instance
191 */
192struct pch_spi_board_data {
193 struct pci_dev *pdev;
194 u8 suspend_sts;
195 int num;
196};
197
198struct pch_pd_dev_save {
199 int num;
200 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
201 struct pch_spi_board_data *board_dat;
202};
203
204static const struct pci_device_id pch_spi_pcidev_id[] = {
205 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
206 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
207 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
208 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
209 { }
210};
211
212/**
213 * pch_spi_writereg() - Performs register writes
214 * @master: Pointer to struct spi_master.
215 * @idx: Register offset.
216 * @val: Value to be written to register.
217 */
218static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
219{
220 struct pch_spi_data *data = spi_master_get_devdata(master);
221 iowrite32(val, (data->io_remap_addr + idx));
222}
223
224/**
225 * pch_spi_readreg() - Performs register reads
226 * @master: Pointer to struct spi_master.
227 * @idx: Register offset.
228 */
229static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
230{
231 struct pch_spi_data *data = spi_master_get_devdata(master);
232 return ioread32(data->io_remap_addr + idx);
233}
234
235static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
236 u32 set, u32 clr)
237{
238 u32 tmp = pch_spi_readreg(master, idx);
239 tmp = (tmp & ~clr) | set;
240 pch_spi_writereg(master, idx, tmp);
241}
242
243static void pch_spi_set_master_mode(struct spi_master *master)
244{
245 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
246}
247
248/**
249 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
250 * @master: Pointer to struct spi_master.
251 */
252static void pch_spi_clear_fifo(struct spi_master *master)
253{
254 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
255 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
256}
257
258static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
259 void __iomem *io_remap_addr)
260{
261 u32 n_read, tx_index, rx_index, bpw_len;
262 u16 *pkt_rx_buffer, *pkt_tx_buff;
263 int read_cnt;
264 u32 reg_spcr_val;
265 void __iomem *spsr;
266 void __iomem *spdrr;
267 void __iomem *spdwr;
268
269 spsr = io_remap_addr + PCH_SPSR;
270 iowrite32(reg_spsr_val, spsr);
271
272 if (data->transfer_active) {
273 rx_index = data->rx_index;
274 tx_index = data->tx_index;
275 bpw_len = data->bpw_len;
276 pkt_rx_buffer = data->pkt_rx_buff;
277 pkt_tx_buff = data->pkt_tx_buff;
278
279 spdrr = io_remap_addr + PCH_SPDRR;
280 spdwr = io_remap_addr + PCH_SPDWR;
281
282 n_read = PCH_READABLE(reg_spsr_val);
283
284 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
285 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
286 if (tx_index < bpw_len)
287 iowrite32(pkt_tx_buff[tx_index++], spdwr);
288 }
289
290 /* disable RFI if not needed */
291 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
292 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
293 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
294
295 /* reset rx threshold */
296 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
297 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
298
299 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
300 }
301
302 /* update counts */
303 data->tx_index = tx_index;
304 data->rx_index = rx_index;
305
306 /* if transfer complete interrupt */
307 if (reg_spsr_val & SPSR_FI_BIT) {
308 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
309 /* disable interrupts */
310 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
311 PCH_ALL);
312
313 /* transfer is completed;
314 inform pch_spi_process_messages */
315 data->transfer_complete = true;
316 data->transfer_active = false;
317 wake_up(&data->wait);
318 } else {
319 dev_vdbg(&data->master->dev,
320 "%s : Transfer is not completed",
321 __func__);
322 }
323 }
324 }
325}
326
327/**
328 * pch_spi_handler() - Interrupt handler
329 * @irq: The interrupt number.
330 * @dev_id: Pointer to struct pch_spi_board_data.
331 */
332static irqreturn_t pch_spi_handler(int irq, void *dev_id)
333{
334 u32 reg_spsr_val;
335 void __iomem *spsr;
336 void __iomem *io_remap_addr;
337 irqreturn_t ret = IRQ_NONE;
338 struct pch_spi_data *data = dev_id;
339 struct pch_spi_board_data *board_dat = data->board_dat;
340
341 if (board_dat->suspend_sts) {
342 dev_dbg(&board_dat->pdev->dev,
343 "%s returning due to suspend\n", __func__);
344 return IRQ_NONE;
345 }
346
347 io_remap_addr = data->io_remap_addr;
348 spsr = io_remap_addr + PCH_SPSR;
349
350 reg_spsr_val = ioread32(spsr);
351
352 if (reg_spsr_val & SPSR_ORF_BIT) {
353 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
354 if (data->current_msg->complete) {
355 data->transfer_complete = true;
356 data->current_msg->status = -EIO;
357 data->current_msg->complete(data->current_msg->context);
358 data->bcurrent_msg_processing = false;
359 data->current_msg = NULL;
360 data->cur_trans = NULL;
361 }
362 }
363
364 if (data->use_dma)
365 return IRQ_NONE;
366
367 /* Check if the interrupt is for SPI device */
368 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
369 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
370 ret = IRQ_HANDLED;
371 }
372
373 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
374 __func__, ret);
375
376 return ret;
377}
378
379/**
380 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
381 * @master: Pointer to struct spi_master.
382 * @speed_hz: Baud rate.
383 */
384static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
385{
386 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
387
388 /* if baud rate is less than we can support limit it */
389 if (n_spbr > PCH_MAX_SPBR)
390 n_spbr = PCH_MAX_SPBR;
391
392 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
393}
394
395/**
396 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
397 * @master: Pointer to struct spi_master.
398 * @bits_per_word: Bits per word for SPI transfer.
399 */
400static void pch_spi_set_bits_per_word(struct spi_master *master,
401 u8 bits_per_word)
402{
403 if (bits_per_word == 8)
404 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
405 else
406 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
407}
408
409/**
410 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
411 * @spi: Pointer to struct spi_device.
412 */
413static void pch_spi_setup_transfer(struct spi_device *spi)
414{
415 u32 flags = 0;
416
417 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
418 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
419 spi->max_speed_hz);
420 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
421
422 /* set bits per word */
423 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
424
425 if (!(spi->mode & SPI_LSB_FIRST))
426 flags |= SPCR_LSBF_BIT;
427 if (spi->mode & SPI_CPOL)
428 flags |= SPCR_CPOL_BIT;
429 if (spi->mode & SPI_CPHA)
430 flags |= SPCR_CPHA_BIT;
431 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
432 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
433
434 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
435 pch_spi_clear_fifo(spi->master);
436}
437
438/**
439 * pch_spi_reset() - Clears SPI registers
440 * @master: Pointer to struct spi_master.
441 */
442static void pch_spi_reset(struct spi_master *master)
443{
444 /* write 1 to reset SPI */
445 pch_spi_writereg(master, PCH_SRST, 0x1);
446
447 /* clear reset */
448 pch_spi_writereg(master, PCH_SRST, 0x0);
449}
450
451static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
452{
453
454 struct spi_transfer *transfer;
455 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
456 int retval;
457 unsigned long flags;
458
459 spin_lock_irqsave(&data->lock, flags);
460 /* validate Tx/Rx buffers and Transfer length */
461 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
462 if (!transfer->tx_buf && !transfer->rx_buf) {
463 dev_err(&pspi->dev,
464 "%s Tx and Rx buffer NULL\n", __func__);
465 retval = -EINVAL;
466 goto err_return_spinlock;
467 }
468
469 if (!transfer->len) {
470 dev_err(&pspi->dev, "%s Transfer length invalid\n",
471 __func__);
472 retval = -EINVAL;
473 goto err_return_spinlock;
474 }
475
476 dev_dbg(&pspi->dev,
477 "%s Tx/Rx buffer valid. Transfer length valid\n",
478 __func__);
479 }
480 spin_unlock_irqrestore(&data->lock, flags);
481
482 /* We won't process any messages if we have been asked to terminate */
483 if (data->status == STATUS_EXITING) {
484 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
485 retval = -ESHUTDOWN;
486 goto err_out;
487 }
488
489 /* If suspended ,return -EINVAL */
490 if (data->board_dat->suspend_sts) {
491 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
492 retval = -EINVAL;
493 goto err_out;
494 }
495
496 /* set status of message */
497 pmsg->actual_length = 0;
498 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
499
500 pmsg->status = -EINPROGRESS;
501 spin_lock_irqsave(&data->lock, flags);
502 /* add message to queue */
503 list_add_tail(&pmsg->queue, &data->queue);
504 spin_unlock_irqrestore(&data->lock, flags);
505
506 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
507
508 schedule_work(&data->work);
509 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
510
511 retval = 0;
512
513err_out:
514 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
515 return retval;
516err_return_spinlock:
517 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
518 spin_unlock_irqrestore(&data->lock, flags);
519 return retval;
520}
521
522static inline void pch_spi_select_chip(struct pch_spi_data *data,
523 struct spi_device *pspi)
524{
525 if (data->current_chip != NULL) {
526 if (pspi->chip_select != data->n_curnt_chip) {
527 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
528 data->current_chip = NULL;
529 }
530 }
531
532 data->current_chip = pspi;
533
534 data->n_curnt_chip = data->current_chip->chip_select;
535
536 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
537 pch_spi_setup_transfer(pspi);
538}
539
540static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
541{
542 int size;
543 u32 n_writes;
544 int j;
545 struct spi_message *pmsg, *tmp;
546 const u8 *tx_buf;
547 const u16 *tx_sbuf;
548
549 /* set baud rate if needed */
550 if (data->cur_trans->speed_hz) {
551 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
552 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
553 }
554
555 /* set bits per word if needed */
556 if (data->cur_trans->bits_per_word &&
557 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
558 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
559 pch_spi_set_bits_per_word(data->master,
560 data->cur_trans->bits_per_word);
561 *bpw = data->cur_trans->bits_per_word;
562 } else {
563 *bpw = data->current_msg->spi->bits_per_word;
564 }
565
566 /* reset Tx/Rx index */
567 data->tx_index = 0;
568 data->rx_index = 0;
569
570 data->bpw_len = data->cur_trans->len / (*bpw / 8);
571
572 /* find alloc size */
573 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
574
575 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
576 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
577 if (data->pkt_tx_buff != NULL) {
578 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
579 if (!data->pkt_rx_buff)
580 kfree(data->pkt_tx_buff);
581 }
582
583 if (!data->pkt_rx_buff) {
584 /* flush queue and set status of all transfers to -ENOMEM */
585 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
586 pmsg->status = -ENOMEM;
587
588 if (pmsg->complete)
589 pmsg->complete(pmsg->context);
590
591 /* delete from queue */
592 list_del_init(&pmsg->queue);
593 }
594 return;
595 }
596
597 /* copy Tx Data */
598 if (data->cur_trans->tx_buf != NULL) {
599 if (*bpw == 8) {
600 tx_buf = data->cur_trans->tx_buf;
601 for (j = 0; j < data->bpw_len; j++)
602 data->pkt_tx_buff[j] = *tx_buf++;
603 } else {
604 tx_sbuf = data->cur_trans->tx_buf;
605 for (j = 0; j < data->bpw_len; j++)
606 data->pkt_tx_buff[j] = *tx_sbuf++;
607 }
608 }
609
610 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
611 n_writes = data->bpw_len;
612 if (n_writes > PCH_MAX_FIFO_DEPTH)
613 n_writes = PCH_MAX_FIFO_DEPTH;
614
615 dev_dbg(&data->master->dev,
616 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
617 __func__);
618 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
619
620 for (j = 0; j < n_writes; j++)
621 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
622
623 /* update tx_index */
624 data->tx_index = j;
625
626 /* reset transfer complete flag */
627 data->transfer_complete = false;
628 data->transfer_active = true;
629}
630
631static void pch_spi_nomore_transfer(struct pch_spi_data *data)
632{
633 struct spi_message *pmsg, *tmp;
634 dev_dbg(&data->master->dev, "%s called\n", __func__);
635 /* Invoke complete callback
636 * [To the spi core..indicating end of transfer] */
637 data->current_msg->status = 0;
638
639 if (data->current_msg->complete) {
640 dev_dbg(&data->master->dev,
641 "%s:Invoking callback of SPI core\n", __func__);
642 data->current_msg->complete(data->current_msg->context);
643 }
644
645 /* update status in global variable */
646 data->bcurrent_msg_processing = false;
647
648 dev_dbg(&data->master->dev,
649 "%s:data->bcurrent_msg_processing = false\n", __func__);
650
651 data->current_msg = NULL;
652 data->cur_trans = NULL;
653
654 /* check if we have items in list and not suspending
655 * return 1 if list empty */
656 if ((list_empty(&data->queue) == 0) &&
657 (!data->board_dat->suspend_sts) &&
658 (data->status != STATUS_EXITING)) {
659 /* We have some more work to do (either there is more tranint
660 * bpw;sfer requests in the current message or there are
661 *more messages)
662 */
663 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
664 schedule_work(&data->work);
665 } else if (data->board_dat->suspend_sts ||
666 data->status == STATUS_EXITING) {
667 dev_dbg(&data->master->dev,
668 "%s suspend/remove initiated, flushing queue\n",
669 __func__);
670 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
671 pmsg->status = -EIO;
672
673 if (pmsg->complete)
674 pmsg->complete(pmsg->context);
675
676 /* delete from queue */
677 list_del_init(&pmsg->queue);
678 }
679 }
680}
681
682static void pch_spi_set_ir(struct pch_spi_data *data)
683{
684 /* enable interrupts, set threshold, enable SPI */
685 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
686 /* set receive threshold to PCH_RX_THOLD */
687 pch_spi_setclr_reg(data->master, PCH_SPCR,
688 PCH_RX_THOLD << SPCR_RFIC_FIELD |
689 SPCR_FIE_BIT | SPCR_RFIE_BIT |
690 SPCR_ORIE_BIT | SPCR_SPE_BIT,
691 MASK_RFIC_SPCR_BITS | PCH_ALL);
692 else
693 /* set receive threshold to maximum */
694 pch_spi_setclr_reg(data->master, PCH_SPCR,
695 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
696 SPCR_FIE_BIT | SPCR_ORIE_BIT |
697 SPCR_SPE_BIT,
698 MASK_RFIC_SPCR_BITS | PCH_ALL);
699
700 /* Wait until the transfer completes; go to sleep after
701 initiating the transfer. */
702 dev_dbg(&data->master->dev,
703 "%s:waiting for transfer to get over\n", __func__);
704
705 wait_event_interruptible(data->wait, data->transfer_complete);
706
707 /* clear all interrupts */
708 pch_spi_writereg(data->master, PCH_SPSR,
709 pch_spi_readreg(data->master, PCH_SPSR));
710 /* Disable interrupts and SPI transfer */
711 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
712 /* clear FIFO */
713 pch_spi_clear_fifo(data->master);
714}
715
716static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
717{
718 int j;
719 u8 *rx_buf;
720 u16 *rx_sbuf;
721
722 /* copy Rx Data */
723 if (!data->cur_trans->rx_buf)
724 return;
725
726 if (bpw == 8) {
727 rx_buf = data->cur_trans->rx_buf;
728 for (j = 0; j < data->bpw_len; j++)
729 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
730 } else {
731 rx_sbuf = data->cur_trans->rx_buf;
732 for (j = 0; j < data->bpw_len; j++)
733 *rx_sbuf++ = data->pkt_rx_buff[j];
734 }
735}
736
737static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
738{
739 int j;
740 u8 *rx_buf;
741 u16 *rx_sbuf;
742 const u8 *rx_dma_buf;
743 const u16 *rx_dma_sbuf;
744
745 /* copy Rx Data */
746 if (!data->cur_trans->rx_buf)
747 return;
748
749 if (bpw == 8) {
750 rx_buf = data->cur_trans->rx_buf;
751 rx_dma_buf = data->dma.rx_buf_virt;
752 for (j = 0; j < data->bpw_len; j++)
753 *rx_buf++ = *rx_dma_buf++ & 0xFF;
754 data->cur_trans->rx_buf = rx_buf;
755 } else {
756 rx_sbuf = data->cur_trans->rx_buf;
757 rx_dma_sbuf = data->dma.rx_buf_virt;
758 for (j = 0; j < data->bpw_len; j++)
759 *rx_sbuf++ = *rx_dma_sbuf++;
760 data->cur_trans->rx_buf = rx_sbuf;
761 }
762}
763
764static int pch_spi_start_transfer(struct pch_spi_data *data)
765{
766 struct pch_spi_dma_ctrl *dma;
767 unsigned long flags;
768 int rtn;
769
770 dma = &data->dma;
771
772 spin_lock_irqsave(&data->lock, flags);
773
774 /* disable interrupts, SPI set enable */
775 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
776
777 spin_unlock_irqrestore(&data->lock, flags);
778
779 /* Wait until the transfer completes; go to sleep after
780 initiating the transfer. */
781 dev_dbg(&data->master->dev,
782 "%s:waiting for transfer to get over\n", __func__);
783 rtn = wait_event_interruptible_timeout(data->wait,
784 data->transfer_complete,
785 msecs_to_jiffies(2 * HZ));
786 if (!rtn)
787 dev_err(&data->master->dev,
788 "%s wait-event timeout\n", __func__);
789
790 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
791 DMA_FROM_DEVICE);
792
793 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
794 DMA_FROM_DEVICE);
795 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
796
797 async_tx_ack(dma->desc_rx);
798 async_tx_ack(dma->desc_tx);
799 kfree(dma->sg_tx_p);
800 kfree(dma->sg_rx_p);
801
802 spin_lock_irqsave(&data->lock, flags);
803
804 /* clear fifo threshold, disable interrupts, disable SPI transfer */
805 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
806 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
807 SPCR_SPE_BIT);
808 /* clear all interrupts */
809 pch_spi_writereg(data->master, PCH_SPSR,
810 pch_spi_readreg(data->master, PCH_SPSR));
811 /* clear FIFO */
812 pch_spi_clear_fifo(data->master);
813
814 spin_unlock_irqrestore(&data->lock, flags);
815
816 return rtn;
817}
818
819static void pch_dma_rx_complete(void *arg)
820{
821 struct pch_spi_data *data = arg;
822
823 /* transfer is completed;inform pch_spi_process_messages_dma */
824 data->transfer_complete = true;
825 wake_up_interruptible(&data->wait);
826}
827
828static bool pch_spi_filter(struct dma_chan *chan, void *slave)
829{
830 struct pch_dma_slave *param = slave;
831
832 if ((chan->chan_id == param->chan_id) &&
833 (param->dma_dev == chan->device->dev)) {
834 chan->private = param;
835 return true;
836 } else {
837 return false;
838 }
839}
840
841static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
842{
843 dma_cap_mask_t mask;
844 struct dma_chan *chan;
845 struct pci_dev *dma_dev;
846 struct pch_dma_slave *param;
847 struct pch_spi_dma_ctrl *dma;
848 unsigned int width;
849
850 if (bpw == 8)
851 width = PCH_DMA_WIDTH_1_BYTE;
852 else
853 width = PCH_DMA_WIDTH_2_BYTES;
854
855 dma = &data->dma;
856 dma_cap_zero(mask);
857 dma_cap_set(DMA_SLAVE, mask);
858
859 /* Get DMA's dev information */
860 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
861 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
862
863 /* Set Tx DMA */
864 param = &dma->param_tx;
865 param->dma_dev = &dma_dev->dev;
866 param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
867 param->tx_reg = data->io_base_addr + PCH_SPDWR;
868 param->width = width;
869 chan = dma_request_channel(mask, pch_spi_filter, param);
870 if (!chan) {
871 dev_err(&data->master->dev,
872 "ERROR: dma_request_channel FAILS(Tx)\n");
873 data->use_dma = 0;
874 return;
875 }
876 dma->chan_tx = chan;
877
878 /* Set Rx DMA */
879 param = &dma->param_rx;
880 param->dma_dev = &dma_dev->dev;
881 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
882 param->rx_reg = data->io_base_addr + PCH_SPDRR;
883 param->width = width;
884 chan = dma_request_channel(mask, pch_spi_filter, param);
885 if (!chan) {
886 dev_err(&data->master->dev,
887 "ERROR: dma_request_channel FAILS(Rx)\n");
888 dma_release_channel(dma->chan_tx);
889 dma->chan_tx = NULL;
890 data->use_dma = 0;
891 return;
892 }
893 dma->chan_rx = chan;
894}
895
896static void pch_spi_release_dma(struct pch_spi_data *data)
897{
898 struct pch_spi_dma_ctrl *dma;
899
900 dma = &data->dma;
901 if (dma->chan_tx) {
902 dma_release_channel(dma->chan_tx);
903 dma->chan_tx = NULL;
904 }
905 if (dma->chan_rx) {
906 dma_release_channel(dma->chan_rx);
907 dma->chan_rx = NULL;
908 }
909}
910
911static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
912{
913 const u8 *tx_buf;
914 const u16 *tx_sbuf;
915 u8 *tx_dma_buf;
916 u16 *tx_dma_sbuf;
917 struct scatterlist *sg;
918 struct dma_async_tx_descriptor *desc_tx;
919 struct dma_async_tx_descriptor *desc_rx;
920 int num;
921 int i;
922 int size;
923 int rem;
924 int head;
925 unsigned long flags;
926 struct pch_spi_dma_ctrl *dma;
927
928 dma = &data->dma;
929
930 /* set baud rate if needed */
931 if (data->cur_trans->speed_hz) {
932 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
933 spin_lock_irqsave(&data->lock, flags);
934 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
935 spin_unlock_irqrestore(&data->lock, flags);
936 }
937
938 /* set bits per word if needed */
939 if (data->cur_trans->bits_per_word &&
940 (data->current_msg->spi->bits_per_word !=
941 data->cur_trans->bits_per_word)) {
942 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
943 spin_lock_irqsave(&data->lock, flags);
944 pch_spi_set_bits_per_word(data->master,
945 data->cur_trans->bits_per_word);
946 spin_unlock_irqrestore(&data->lock, flags);
947 *bpw = data->cur_trans->bits_per_word;
948 } else {
949 *bpw = data->current_msg->spi->bits_per_word;
950 }
951 data->bpw_len = data->cur_trans->len / (*bpw / 8);
952
953 if (data->bpw_len > PCH_BUF_SIZE) {
954 data->bpw_len = PCH_BUF_SIZE;
955 data->cur_trans->len -= PCH_BUF_SIZE;
956 }
957
958 /* copy Tx Data */
959 if (data->cur_trans->tx_buf != NULL) {
960 if (*bpw == 8) {
961 tx_buf = data->cur_trans->tx_buf;
962 tx_dma_buf = dma->tx_buf_virt;
963 for (i = 0; i < data->bpw_len; i++)
964 *tx_dma_buf++ = *tx_buf++;
965 } else {
966 tx_sbuf = data->cur_trans->tx_buf;
967 tx_dma_sbuf = dma->tx_buf_virt;
968 for (i = 0; i < data->bpw_len; i++)
969 *tx_dma_sbuf++ = *tx_sbuf++;
970 }
971 }
972
973 /* Calculate Rx parameter for DMA transmitting */
974 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
975 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
976 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
977 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
978 } else {
979 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
980 rem = PCH_DMA_TRANS_SIZE;
981 }
982 size = PCH_DMA_TRANS_SIZE;
983 } else {
984 num = 1;
985 size = data->bpw_len;
986 rem = data->bpw_len;
987 }
988 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
989 __func__, num, size, rem);
990 spin_lock_irqsave(&data->lock, flags);
991
992 /* set receive fifo threshold and transmit fifo threshold */
993 pch_spi_setclr_reg(data->master, PCH_SPCR,
994 ((size - 1) << SPCR_RFIC_FIELD) |
995 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
996 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
997
998 spin_unlock_irqrestore(&data->lock, flags);
999
1000 /* RX */
1001 dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1002 if (!dma->sg_rx_p)
1003 return;
1004
1005 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1006 /* offset, length setting */
1007 sg = dma->sg_rx_p;
1008 for (i = 0; i < num; i++, sg++) {
1009 if (i == (num - 2)) {
1010 sg->offset = size * i;
1011 sg->offset = sg->offset * (*bpw / 8);
1012 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1013 sg->offset);
1014 sg_dma_len(sg) = rem;
1015 } else if (i == (num - 1)) {
1016 sg->offset = size * (i - 1) + rem;
1017 sg->offset = sg->offset * (*bpw / 8);
1018 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1019 sg->offset);
1020 sg_dma_len(sg) = size;
1021 } else {
1022 sg->offset = size * i;
1023 sg->offset = sg->offset * (*bpw / 8);
1024 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1025 sg->offset);
1026 sg_dma_len(sg) = size;
1027 }
1028 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1029 }
1030 sg = dma->sg_rx_p;
1031 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1032 num, DMA_DEV_TO_MEM,
1033 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1034 if (!desc_rx) {
1035 dev_err(&data->master->dev,
1036 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1037 return;
1038 }
1039 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1040 desc_rx->callback = pch_dma_rx_complete;
1041 desc_rx->callback_param = data;
1042 dma->nent = num;
1043 dma->desc_rx = desc_rx;
1044
1045 /* Calculate Tx parameter for DMA transmitting */
1046 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1047 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1048 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1049 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1050 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1051 } else {
1052 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1053 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1054 PCH_DMA_TRANS_SIZE - head;
1055 }
1056 size = PCH_DMA_TRANS_SIZE;
1057 } else {
1058 num = 1;
1059 size = data->bpw_len;
1060 rem = data->bpw_len;
1061 head = 0;
1062 }
1063
1064 dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1065 if (!dma->sg_tx_p)
1066 return;
1067
1068 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1069 /* offset, length setting */
1070 sg = dma->sg_tx_p;
1071 for (i = 0; i < num; i++, sg++) {
1072 if (i == 0) {
1073 sg->offset = 0;
1074 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1075 sg->offset);
1076 sg_dma_len(sg) = size + head;
1077 } else if (i == (num - 1)) {
1078 sg->offset = head + size * i;
1079 sg->offset = sg->offset * (*bpw / 8);
1080 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1081 sg->offset);
1082 sg_dma_len(sg) = rem;
1083 } else {
1084 sg->offset = head + size * i;
1085 sg->offset = sg->offset * (*bpw / 8);
1086 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1087 sg->offset);
1088 sg_dma_len(sg) = size;
1089 }
1090 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1091 }
1092 sg = dma->sg_tx_p;
1093 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1094 sg, num, DMA_MEM_TO_DEV,
1095 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1096 if (!desc_tx) {
1097 dev_err(&data->master->dev,
1098 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1099 return;
1100 }
1101 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1102 desc_tx->callback = NULL;
1103 desc_tx->callback_param = data;
1104 dma->nent = num;
1105 dma->desc_tx = desc_tx;
1106
1107 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1108
1109 spin_lock_irqsave(&data->lock, flags);
1110 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1111 desc_rx->tx_submit(desc_rx);
1112 desc_tx->tx_submit(desc_tx);
1113 spin_unlock_irqrestore(&data->lock, flags);
1114
1115 /* reset transfer complete flag */
1116 data->transfer_complete = false;
1117}
1118
1119static void pch_spi_process_messages(struct work_struct *pwork)
1120{
1121 struct spi_message *pmsg, *tmp;
1122 struct pch_spi_data *data;
1123 int bpw;
1124
1125 data = container_of(pwork, struct pch_spi_data, work);
1126 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1127
1128 spin_lock(&data->lock);
1129 /* check if suspend has been initiated;if yes flush queue */
1130 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1131 dev_dbg(&data->master->dev,
1132 "%s suspend/remove initiated, flushing queue\n", __func__);
1133 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1134 pmsg->status = -EIO;
1135
1136 if (pmsg->complete) {
1137 spin_unlock(&data->lock);
1138 pmsg->complete(pmsg->context);
1139 spin_lock(&data->lock);
1140 }
1141
1142 /* delete from queue */
1143 list_del_init(&pmsg->queue);
1144 }
1145
1146 spin_unlock(&data->lock);
1147 return;
1148 }
1149
1150 data->bcurrent_msg_processing = true;
1151 dev_dbg(&data->master->dev,
1152 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1153
1154 /* Get the message from the queue and delete it from there. */
1155 data->current_msg = list_entry(data->queue.next, struct spi_message,
1156 queue);
1157
1158 list_del_init(&data->current_msg->queue);
1159
1160 data->current_msg->status = 0;
1161
1162 pch_spi_select_chip(data, data->current_msg->spi);
1163
1164 spin_unlock(&data->lock);
1165
1166 if (data->use_dma)
1167 pch_spi_request_dma(data,
1168 data->current_msg->spi->bits_per_word);
1169 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1170 do {
1171 int cnt;
1172 /* If we are already processing a message get the next
1173 transfer structure from the message otherwise retrieve
1174 the 1st transfer request from the message. */
1175 spin_lock(&data->lock);
1176 if (data->cur_trans == NULL) {
1177 data->cur_trans =
1178 list_entry(data->current_msg->transfers.next,
1179 struct spi_transfer, transfer_list);
1180 dev_dbg(&data->master->dev,
1181 "%s :Getting 1st transfer message\n",
1182 __func__);
1183 } else {
1184 data->cur_trans =
1185 list_entry(data->cur_trans->transfer_list.next,
1186 struct spi_transfer, transfer_list);
1187 dev_dbg(&data->master->dev,
1188 "%s :Getting next transfer message\n",
1189 __func__);
1190 }
1191 spin_unlock(&data->lock);
1192
1193 if (!data->cur_trans->len)
1194 goto out;
1195 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1196 data->save_total_len = data->cur_trans->len;
1197 if (data->use_dma) {
1198 int i;
1199 char *save_rx_buf = data->cur_trans->rx_buf;
1200 for (i = 0; i < cnt; i ++) {
1201 pch_spi_handle_dma(data, &bpw);
1202 if (!pch_spi_start_transfer(data)) {
1203 data->transfer_complete = true;
1204 data->current_msg->status = -EIO;
1205 data->current_msg->complete
1206 (data->current_msg->context);
1207 data->bcurrent_msg_processing = false;
1208 data->current_msg = NULL;
1209 data->cur_trans = NULL;
1210 goto out;
1211 }
1212 pch_spi_copy_rx_data_for_dma(data, bpw);
1213 }
1214 data->cur_trans->rx_buf = save_rx_buf;
1215 } else {
1216 pch_spi_set_tx(data, &bpw);
1217 pch_spi_set_ir(data);
1218 pch_spi_copy_rx_data(data, bpw);
1219 kfree(data->pkt_rx_buff);
1220 data->pkt_rx_buff = NULL;
1221 kfree(data->pkt_tx_buff);
1222 data->pkt_tx_buff = NULL;
1223 }
1224 /* increment message count */
1225 data->cur_trans->len = data->save_total_len;
1226 data->current_msg->actual_length += data->cur_trans->len;
1227
1228 dev_dbg(&data->master->dev,
1229 "%s:data->current_msg->actual_length=%d\n",
1230 __func__, data->current_msg->actual_length);
1231
1232 /* check for delay */
1233 if (data->cur_trans->delay_usecs) {
1234 dev_dbg(&data->master->dev, "%s:delay in usec=%d\n",
1235 __func__, data->cur_trans->delay_usecs);
1236 udelay(data->cur_trans->delay_usecs);
1237 }
1238
1239 spin_lock(&data->lock);
1240
1241 /* No more transfer in this message. */
1242 if ((data->cur_trans->transfer_list.next) ==
1243 &(data->current_msg->transfers)) {
1244 pch_spi_nomore_transfer(data);
1245 }
1246
1247 spin_unlock(&data->lock);
1248
1249 } while (data->cur_trans != NULL);
1250
1251out:
1252 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1253 if (data->use_dma)
1254 pch_spi_release_dma(data);
1255}
1256
1257static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1258 struct pch_spi_data *data)
1259{
1260 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1261
1262 flush_work(&data->work);
1263}
1264
1265static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1266 struct pch_spi_data *data)
1267{
1268 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1269
1270 /* reset PCH SPI h/w */
1271 pch_spi_reset(data->master);
1272 dev_dbg(&board_dat->pdev->dev,
1273 "%s pch_spi_reset invoked successfully\n", __func__);
1274
1275 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1276
1277 return 0;
1278}
1279
1280static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1281 struct pch_spi_data *data)
1282{
1283 struct pch_spi_dma_ctrl *dma;
1284
1285 dma = &data->dma;
1286 if (dma->tx_buf_dma)
1287 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1288 dma->tx_buf_virt, dma->tx_buf_dma);
1289 if (dma->rx_buf_dma)
1290 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1291 dma->rx_buf_virt, dma->rx_buf_dma);
1292}
1293
1294static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1295 struct pch_spi_data *data)
1296{
1297 struct pch_spi_dma_ctrl *dma;
1298 int ret;
1299
1300 dma = &data->dma;
1301 ret = 0;
1302 /* Get Consistent memory for Tx DMA */
1303 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1304 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1305 if (!dma->tx_buf_virt)
1306 ret = -ENOMEM;
1307
1308 /* Get Consistent memory for Rx DMA */
1309 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1310 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1311 if (!dma->rx_buf_virt)
1312 ret = -ENOMEM;
1313
1314 return ret;
1315}
1316
1317static int pch_spi_pd_probe(struct platform_device *plat_dev)
1318{
1319 int ret;
1320 struct spi_master *master;
1321 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1322 struct pch_spi_data *data;
1323
1324 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1325
1326 master = spi_alloc_master(&board_dat->pdev->dev,
1327 sizeof(struct pch_spi_data));
1328 if (!master) {
1329 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1330 plat_dev->id);
1331 return -ENOMEM;
1332 }
1333
1334 data = spi_master_get_devdata(master);
1335 data->master = master;
1336
1337 platform_set_drvdata(plat_dev, data);
1338
1339 /* baseaddress + address offset) */
1340 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1341 PCH_ADDRESS_SIZE * plat_dev->id;
1342 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1343 if (!data->io_remap_addr) {
1344 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1345 ret = -ENOMEM;
1346 goto err_pci_iomap;
1347 }
1348 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1349
1350 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1351 plat_dev->id, data->io_remap_addr);
1352
1353 /* initialize members of SPI master */
1354 master->num_chipselect = PCH_MAX_CS;
1355 master->transfer = pch_spi_transfer;
1356 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1357 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1358 master->max_speed_hz = PCH_MAX_BAUDRATE;
1359
1360 data->board_dat = board_dat;
1361 data->plat_dev = plat_dev;
1362 data->n_curnt_chip = 255;
1363 data->status = STATUS_RUNNING;
1364 data->ch = plat_dev->id;
1365 data->use_dma = use_dma;
1366
1367 INIT_LIST_HEAD(&data->queue);
1368 spin_lock_init(&data->lock);
1369 INIT_WORK(&data->work, pch_spi_process_messages);
1370 init_waitqueue_head(&data->wait);
1371
1372 ret = pch_spi_get_resources(board_dat, data);
1373 if (ret) {
1374 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1375 goto err_spi_get_resources;
1376 }
1377
1378 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1379 IRQF_SHARED, KBUILD_MODNAME, data);
1380 if (ret) {
1381 dev_err(&plat_dev->dev,
1382 "%s request_irq failed\n", __func__);
1383 goto err_request_irq;
1384 }
1385 data->irq_reg_sts = true;
1386
1387 pch_spi_set_master_mode(master);
1388
1389 if (use_dma) {
1390 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1391 ret = pch_alloc_dma_buf(board_dat, data);
1392 if (ret)
1393 goto err_spi_register_master;
1394 }
1395
1396 ret = spi_register_master(master);
1397 if (ret != 0) {
1398 dev_err(&plat_dev->dev,
1399 "%s spi_register_master FAILED\n", __func__);
1400 goto err_spi_register_master;
1401 }
1402
1403 return 0;
1404
1405err_spi_register_master:
1406 pch_free_dma_buf(board_dat, data);
1407 free_irq(board_dat->pdev->irq, data);
1408err_request_irq:
1409 pch_spi_free_resources(board_dat, data);
1410err_spi_get_resources:
1411 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1412err_pci_iomap:
1413 spi_master_put(master);
1414
1415 return ret;
1416}
1417
1418static int pch_spi_pd_remove(struct platform_device *plat_dev)
1419{
1420 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1421 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1422 int count;
1423 unsigned long flags;
1424
1425 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1426 __func__, plat_dev->id, board_dat->pdev->irq);
1427
1428 if (use_dma)
1429 pch_free_dma_buf(board_dat, data);
1430
1431 /* check for any pending messages; no action is taken if the queue
1432 * is still full; but at least we tried. Unload anyway */
1433 count = 500;
1434 spin_lock_irqsave(&data->lock, flags);
1435 data->status = STATUS_EXITING;
1436 while ((list_empty(&data->queue) == 0) && --count) {
1437 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1438 __func__);
1439 spin_unlock_irqrestore(&data->lock, flags);
1440 msleep(PCH_SLEEP_TIME);
1441 spin_lock_irqsave(&data->lock, flags);
1442 }
1443 spin_unlock_irqrestore(&data->lock, flags);
1444
1445 pch_spi_free_resources(board_dat, data);
1446 /* disable interrupts & free IRQ */
1447 if (data->irq_reg_sts) {
1448 /* disable interrupts */
1449 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1450 data->irq_reg_sts = false;
1451 free_irq(board_dat->pdev->irq, data);
1452 }
1453
1454 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1455 spi_unregister_master(data->master);
1456
1457 return 0;
1458}
1459#ifdef CONFIG_PM
1460static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1461 pm_message_t state)
1462{
1463 u8 count;
1464 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1465 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1466
1467 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1468
1469 if (!board_dat) {
1470 dev_err(&pd_dev->dev,
1471 "%s pci_get_drvdata returned NULL\n", __func__);
1472 return -EFAULT;
1473 }
1474
1475 /* check if the current message is processed:
1476 Only after thats done the transfer will be suspended */
1477 count = 255;
1478 while ((--count) > 0) {
1479 if (!(data->bcurrent_msg_processing))
1480 break;
1481 msleep(PCH_SLEEP_TIME);
1482 }
1483
1484 /* Free IRQ */
1485 if (data->irq_reg_sts) {
1486 /* disable all interrupts */
1487 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1488 pch_spi_reset(data->master);
1489 free_irq(board_dat->pdev->irq, data);
1490
1491 data->irq_reg_sts = false;
1492 dev_dbg(&pd_dev->dev,
1493 "%s free_irq invoked successfully.\n", __func__);
1494 }
1495
1496 return 0;
1497}
1498
1499static int pch_spi_pd_resume(struct platform_device *pd_dev)
1500{
1501 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1502 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1503 int retval;
1504
1505 if (!board_dat) {
1506 dev_err(&pd_dev->dev,
1507 "%s pci_get_drvdata returned NULL\n", __func__);
1508 return -EFAULT;
1509 }
1510
1511 if (!data->irq_reg_sts) {
1512 /* register IRQ */
1513 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1514 IRQF_SHARED, KBUILD_MODNAME, data);
1515 if (retval < 0) {
1516 dev_err(&pd_dev->dev,
1517 "%s request_irq failed\n", __func__);
1518 return retval;
1519 }
1520
1521 /* reset PCH SPI h/w */
1522 pch_spi_reset(data->master);
1523 pch_spi_set_master_mode(data->master);
1524 data->irq_reg_sts = true;
1525 }
1526 return 0;
1527}
1528#else
1529#define pch_spi_pd_suspend NULL
1530#define pch_spi_pd_resume NULL
1531#endif
1532
1533static struct platform_driver pch_spi_pd_driver = {
1534 .driver = {
1535 .name = "pch-spi",
1536 },
1537 .probe = pch_spi_pd_probe,
1538 .remove = pch_spi_pd_remove,
1539 .suspend = pch_spi_pd_suspend,
1540 .resume = pch_spi_pd_resume
1541};
1542
1543static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1544{
1545 struct pch_spi_board_data *board_dat;
1546 struct platform_device *pd_dev = NULL;
1547 int retval;
1548 int i;
1549 struct pch_pd_dev_save *pd_dev_save;
1550
1551 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1552 if (!pd_dev_save)
1553 return -ENOMEM;
1554
1555 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1556 if (!board_dat) {
1557 retval = -ENOMEM;
1558 goto err_no_mem;
1559 }
1560
1561 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1562 if (retval) {
1563 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1564 goto pci_request_regions;
1565 }
1566
1567 board_dat->pdev = pdev;
1568 board_dat->num = id->driver_data;
1569 pd_dev_save->num = id->driver_data;
1570 pd_dev_save->board_dat = board_dat;
1571
1572 retval = pci_enable_device(pdev);
1573 if (retval) {
1574 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1575 goto pci_enable_device;
1576 }
1577
1578 for (i = 0; i < board_dat->num; i++) {
1579 pd_dev = platform_device_alloc("pch-spi", i);
1580 if (!pd_dev) {
1581 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1582 retval = -ENOMEM;
1583 goto err_platform_device;
1584 }
1585 pd_dev_save->pd_save[i] = pd_dev;
1586 pd_dev->dev.parent = &pdev->dev;
1587
1588 retval = platform_device_add_data(pd_dev, board_dat,
1589 sizeof(*board_dat));
1590 if (retval) {
1591 dev_err(&pdev->dev,
1592 "platform_device_add_data failed\n");
1593 platform_device_put(pd_dev);
1594 goto err_platform_device;
1595 }
1596
1597 retval = platform_device_add(pd_dev);
1598 if (retval) {
1599 dev_err(&pdev->dev, "platform_device_add failed\n");
1600 platform_device_put(pd_dev);
1601 goto err_platform_device;
1602 }
1603 }
1604
1605 pci_set_drvdata(pdev, pd_dev_save);
1606
1607 return 0;
1608
1609err_platform_device:
1610 while (--i >= 0)
1611 platform_device_unregister(pd_dev_save->pd_save[i]);
1612 pci_disable_device(pdev);
1613pci_enable_device:
1614 pci_release_regions(pdev);
1615pci_request_regions:
1616 kfree(board_dat);
1617err_no_mem:
1618 kfree(pd_dev_save);
1619
1620 return retval;
1621}
1622
1623static void pch_spi_remove(struct pci_dev *pdev)
1624{
1625 int i;
1626 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1627
1628 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1629
1630 for (i = 0; i < pd_dev_save->num; i++)
1631 platform_device_unregister(pd_dev_save->pd_save[i]);
1632
1633 pci_disable_device(pdev);
1634 pci_release_regions(pdev);
1635 kfree(pd_dev_save->board_dat);
1636 kfree(pd_dev_save);
1637}
1638
1639#ifdef CONFIG_PM
1640static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1641{
1642 int retval;
1643 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1644
1645 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1646
1647 pd_dev_save->board_dat->suspend_sts = true;
1648
1649 /* save config space */
1650 retval = pci_save_state(pdev);
1651 if (retval == 0) {
1652 pci_enable_wake(pdev, PCI_D3hot, 0);
1653 pci_disable_device(pdev);
1654 pci_set_power_state(pdev, PCI_D3hot);
1655 } else {
1656 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1657 }
1658
1659 return retval;
1660}
1661
1662static int pch_spi_resume(struct pci_dev *pdev)
1663{
1664 int retval;
1665 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1666 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1667
1668 pci_set_power_state(pdev, PCI_D0);
1669 pci_restore_state(pdev);
1670
1671 retval = pci_enable_device(pdev);
1672 if (retval < 0) {
1673 dev_err(&pdev->dev,
1674 "%s pci_enable_device failed\n", __func__);
1675 } else {
1676 pci_enable_wake(pdev, PCI_D3hot, 0);
1677
1678 /* set suspend status to false */
1679 pd_dev_save->board_dat->suspend_sts = false;
1680 }
1681
1682 return retval;
1683}
1684#else
1685#define pch_spi_suspend NULL
1686#define pch_spi_resume NULL
1687
1688#endif
1689
1690static struct pci_driver pch_spi_pcidev_driver = {
1691 .name = "pch_spi",
1692 .id_table = pch_spi_pcidev_id,
1693 .probe = pch_spi_probe,
1694 .remove = pch_spi_remove,
1695 .suspend = pch_spi_suspend,
1696 .resume = pch_spi_resume,
1697};
1698
1699static int __init pch_spi_init(void)
1700{
1701 int ret;
1702 ret = platform_driver_register(&pch_spi_pd_driver);
1703 if (ret)
1704 return ret;
1705
1706 ret = pci_register_driver(&pch_spi_pcidev_driver);
1707 if (ret) {
1708 platform_driver_unregister(&pch_spi_pd_driver);
1709 return ret;
1710 }
1711
1712 return 0;
1713}
1714module_init(pch_spi_init);
1715
1716static void __exit pch_spi_exit(void)
1717{
1718 pci_unregister_driver(&pch_spi_pcidev_driver);
1719 platform_driver_unregister(&pch_spi_pd_driver);
1720}
1721module_exit(pch_spi_exit);
1722
1723module_param(use_dma, int, 0644);
1724MODULE_PARM_DESC(use_dma,
1725 "to use DMA for data transfers pass 1 else 0; default 1");
1726
1727MODULE_LICENSE("GPL");
1728MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1729MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1730