1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * SPI driver for NVIDIA's Tegra114 SPI Controller.
   4 *
   5 * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/completion.h>
  10#include <linux/delay.h>
  11#include <linux/dmaengine.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/dmapool.h>
  14#include <linux/err.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/kernel.h>
  18#include <linux/kthread.h>
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/of.h>
  23#include <linux/of_device.h>
  24#include <linux/reset.h>
  25#include <linux/spi/spi.h>
  26
  27#define SPI_COMMAND1				0x000
  28#define SPI_BIT_LENGTH(x)			(((x) & 0x1f) << 0)
  29#define SPI_PACKED				(1 << 5)
  30#define SPI_TX_EN				(1 << 11)
  31#define SPI_RX_EN				(1 << 12)
  32#define SPI_BOTH_EN_BYTE			(1 << 13)
  33#define SPI_BOTH_EN_BIT				(1 << 14)
  34#define SPI_LSBYTE_FE				(1 << 15)
  35#define SPI_LSBIT_FE				(1 << 16)
  36#define SPI_BIDIROE				(1 << 17)
  37#define SPI_IDLE_SDA_DRIVE_LOW			(0 << 18)
  38#define SPI_IDLE_SDA_DRIVE_HIGH			(1 << 18)
  39#define SPI_IDLE_SDA_PULL_LOW			(2 << 18)
  40#define SPI_IDLE_SDA_PULL_HIGH			(3 << 18)
  41#define SPI_IDLE_SDA_MASK			(3 << 18)
  42#define SPI_CS_SW_VAL				(1 << 20)
  43#define SPI_CS_SW_HW				(1 << 21)
  44/* SPI_CS_POL_INACTIVE bits are default high */
  45						/* n from 0 to 3 */
  46#define SPI_CS_POL_INACTIVE(n)			(1 << (22 + (n)))
  47#define SPI_CS_POL_INACTIVE_MASK		(0xF << 22)
  48
  49#define SPI_CS_SEL_0				(0 << 26)
  50#define SPI_CS_SEL_1				(1 << 26)
  51#define SPI_CS_SEL_2				(2 << 26)
  52#define SPI_CS_SEL_3				(3 << 26)
  53#define SPI_CS_SEL_MASK				(3 << 26)
  54#define SPI_CS_SEL(x)				(((x) & 0x3) << 26)
  55#define SPI_CONTROL_MODE_0			(0 << 28)
  56#define SPI_CONTROL_MODE_1			(1 << 28)
  57#define SPI_CONTROL_MODE_2			(2 << 28)
  58#define SPI_CONTROL_MODE_3			(3 << 28)
  59#define SPI_CONTROL_MODE_MASK			(3 << 28)
  60#define SPI_MODE_SEL(x)				(((x) & 0x3) << 28)
  61#define SPI_M_S					(1 << 30)
  62#define SPI_PIO					(1 << 31)
  63
  64#define SPI_COMMAND2				0x004
  65#define SPI_TX_TAP_DELAY(x)			(((x) & 0x3F) << 6)
  66#define SPI_RX_TAP_DELAY(x)			(((x) & 0x3F) << 0)
  67
  68#define SPI_CS_TIMING1				0x008
  69#define SPI_SETUP_HOLD(setup, hold)		(((setup) << 4) | (hold))
  70#define SPI_CS_SETUP_HOLD(reg, cs, val)			\
  71		((((val) & 0xFFu) << ((cs) * 8)) |	\
  72		((reg) & ~(0xFFu << ((cs) * 8))))
  73
  74#define SPI_CS_TIMING2				0x00C
  75#define CYCLES_BETWEEN_PACKETS_0(x)		(((x) & 0x1F) << 0)
  76#define CS_ACTIVE_BETWEEN_PACKETS_0		(1 << 5)
  77#define CYCLES_BETWEEN_PACKETS_1(x)		(((x) & 0x1F) << 8)
  78#define CS_ACTIVE_BETWEEN_PACKETS_1		(1 << 13)
  79#define CYCLES_BETWEEN_PACKETS_2(x)		(((x) & 0x1F) << 16)
  80#define CS_ACTIVE_BETWEEN_PACKETS_2		(1 << 21)
  81#define CYCLES_BETWEEN_PACKETS_3(x)		(((x) & 0x1F) << 24)
  82#define CS_ACTIVE_BETWEEN_PACKETS_3		(1 << 29)
  83#define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val)		\
  84		(reg = (((val) & 0x1) << ((cs) * 8 + 5)) |	\
  85			((reg) & ~(1 << ((cs) * 8 + 5))))
  86#define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val)		\
  87		(reg = (((val) & 0x1F) << ((cs) * 8)) |		\
  88			((reg) & ~(0x1F << ((cs) * 8))))
  89#define MAX_SETUP_HOLD_CYCLES			16
  90#define MAX_INACTIVE_CYCLES			32
  91
  92#define SPI_TRANS_STATUS			0x010
  93#define SPI_BLK_CNT(val)			(((val) >> 0) & 0xFFFF)
  94#define SPI_SLV_IDLE_COUNT(val)			(((val) >> 16) & 0xFF)
  95#define SPI_RDY					(1 << 30)
  96
  97#define SPI_FIFO_STATUS				0x014
  98#define SPI_RX_FIFO_EMPTY			(1 << 0)
  99#define SPI_RX_FIFO_FULL			(1 << 1)
 100#define SPI_TX_FIFO_EMPTY			(1 << 2)
 101#define SPI_TX_FIFO_FULL			(1 << 3)
 102#define SPI_RX_FIFO_UNF				(1 << 4)
 103#define SPI_RX_FIFO_OVF				(1 << 5)
 104#define SPI_TX_FIFO_UNF				(1 << 6)
 105#define SPI_TX_FIFO_OVF				(1 << 7)
 106#define SPI_ERR					(1 << 8)
 107#define SPI_TX_FIFO_FLUSH			(1 << 14)
 108#define SPI_RX_FIFO_FLUSH			(1 << 15)
 109#define SPI_TX_FIFO_EMPTY_COUNT(val)		(((val) >> 16) & 0x7F)
 110#define SPI_RX_FIFO_FULL_COUNT(val)		(((val) >> 23) & 0x7F)
 111#define SPI_FRAME_END				(1 << 30)
 112#define SPI_CS_INACTIVE				(1 << 31)
 113
 114#define SPI_FIFO_ERROR				(SPI_RX_FIFO_UNF | \
 115			SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
 116#define SPI_FIFO_EMPTY			(SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
 117
 118#define SPI_TX_DATA				0x018
 119#define SPI_RX_DATA				0x01C
 120
 121#define SPI_DMA_CTL				0x020
 122#define SPI_TX_TRIG_1				(0 << 15)
 123#define SPI_TX_TRIG_4				(1 << 15)
 124#define SPI_TX_TRIG_8				(2 << 15)
 125#define SPI_TX_TRIG_16				(3 << 15)
 126#define SPI_TX_TRIG_MASK			(3 << 15)
 127#define SPI_RX_TRIG_1				(0 << 19)
 128#define SPI_RX_TRIG_4				(1 << 19)
 129#define SPI_RX_TRIG_8				(2 << 19)
 130#define SPI_RX_TRIG_16				(3 << 19)
 131#define SPI_RX_TRIG_MASK			(3 << 19)
 132#define SPI_IE_TX				(1 << 28)
 133#define SPI_IE_RX				(1 << 29)
 134#define SPI_CONT				(1 << 30)
 135#define SPI_DMA					(1 << 31)
 136#define SPI_DMA_EN				SPI_DMA
 137
 138#define SPI_DMA_BLK				0x024
 139#define SPI_DMA_BLK_SET(x)			(((x) & 0xFFFF) << 0)
 140
 141#define SPI_TX_FIFO				0x108
 142#define SPI_RX_FIFO				0x188
 143#define SPI_INTR_MASK				0x18c
 144#define SPI_INTR_ALL_MASK			(0x1fUL << 25)
 145#define MAX_CHIP_SELECT				4
 146#define SPI_FIFO_DEPTH				64
 147#define DATA_DIR_TX				(1 << 0)
 148#define DATA_DIR_RX				(1 << 1)
 149
 150#define SPI_DMA_TIMEOUT				(msecs_to_jiffies(1000))
 151#define DEFAULT_SPI_DMA_BUF_LEN			(16*1024)
 152#define TX_FIFO_EMPTY_COUNT_MAX			SPI_TX_FIFO_EMPTY_COUNT(0x40)
 153#define RX_FIFO_FULL_COUNT_ZERO			SPI_RX_FIFO_FULL_COUNT(0)
 154#define MAX_HOLD_CYCLES				16
 155#define SPI_DEFAULT_SPEED			25000000
 156
 157struct tegra_spi_soc_data {
 158	bool has_intr_mask_reg;
 159};
 160
 161struct tegra_spi_client_data {
 162	int tx_clk_tap_delay;
 163	int rx_clk_tap_delay;
 164};
 165
 166struct tegra_spi_data {
 167	struct device				*dev;
 168	struct spi_master			*master;
 169	spinlock_t				lock;
 170
 171	struct clk				*clk;
 172	struct reset_control			*rst;
 173	void __iomem				*base;
 174	phys_addr_t				phys;
 175	unsigned				irq;
 176	u32					cur_speed;
 177
 178	struct spi_device			*cur_spi;
 179	struct spi_device			*cs_control;
 180	unsigned				cur_pos;
 181	unsigned				words_per_32bit;
 182	unsigned				bytes_per_word;
 183	unsigned				curr_dma_words;
 184	unsigned				cur_direction;
 185
 186	unsigned				cur_rx_pos;
 187	unsigned				cur_tx_pos;
 188
 189	unsigned				dma_buf_size;
 190	unsigned				max_buf_size;
 191	bool					is_curr_dma_xfer;
 192	bool					use_hw_based_cs;
 193
 194	struct completion			rx_dma_complete;
 195	struct completion			tx_dma_complete;
 196
 197	u32					tx_status;
 198	u32					rx_status;
 199	u32					status_reg;
 200	bool					is_packed;
 201
 202	u32					command1_reg;
 203	u32					dma_control_reg;
 204	u32					def_command1_reg;
 205	u32					def_command2_reg;
 206	u32					spi_cs_timing1;
 207	u32					spi_cs_timing2;
 208	u8					last_used_cs;
 209
 210	struct completion			xfer_completion;
 211	struct spi_transfer			*curr_xfer;
 212	struct dma_chan				*rx_dma_chan;
 213	u32					*rx_dma_buf;
 214	dma_addr_t				rx_dma_phys;
 215	struct dma_async_tx_descriptor		*rx_dma_desc;
 216
 217	struct dma_chan				*tx_dma_chan;
 218	u32					*tx_dma_buf;
 219	dma_addr_t				tx_dma_phys;
 220	struct dma_async_tx_descriptor		*tx_dma_desc;
 221	const struct tegra_spi_soc_data		*soc_data;
 222};
 223
 224static int tegra_spi_runtime_suspend(struct device *dev);
 225static int tegra_spi_runtime_resume(struct device *dev);
 226
 227static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
 228		unsigned long reg)
 229{
 230	return readl(tspi->base + reg);
 231}
 232
 233static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
 234		u32 val, unsigned long reg)
 235{
 236	writel(val, tspi->base + reg);
 237
 238	/* Read back register to make sure that register writes completed */
 239	if (reg != SPI_TX_FIFO)
 240		readl(tspi->base + SPI_COMMAND1);
 241}
 242
 243static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
 244{
 245	u32 val;
 246
 247	/* Write 1 to clear status register */
 248	val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
 249	tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
 250
 251	/* Clear fifo status error if any */
 252	val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 253	if (val & SPI_ERR)
 254		tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
 255				SPI_FIFO_STATUS);
 256}
 257
 258static unsigned tegra_spi_calculate_curr_xfer_param(
 259	struct spi_device *spi, struct tegra_spi_data *tspi,
 260	struct spi_transfer *t)
 261{
 262	unsigned remain_len = t->len - tspi->cur_pos;
 263	unsigned max_word;
 264	unsigned bits_per_word = t->bits_per_word;
 265	unsigned max_len;
 266	unsigned total_fifo_words;
 267
 268	tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
 269
 270	if ((bits_per_word == 8 || bits_per_word == 16 ||
 271	     bits_per_word == 32) && t->len > 3) {
 272		tspi->is_packed = true;
 273		tspi->words_per_32bit = 32/bits_per_word;
 274	} else {
 275		tspi->is_packed = false;
 276		tspi->words_per_32bit = 1;
 277	}
 278
 279	if (tspi->is_packed) {
 280		max_len = min(remain_len, tspi->max_buf_size);
 281		tspi->curr_dma_words = max_len/tspi->bytes_per_word;
 282		total_fifo_words = (max_len + 3) / 4;
 283	} else {
 284		max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
 285		max_word = min(max_word, tspi->max_buf_size/4);
 286		tspi->curr_dma_words = max_word;
 287		total_fifo_words = max_word;
 288	}
 289	return total_fifo_words;
 290}
 291
 292static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
 293	struct tegra_spi_data *tspi, struct spi_transfer *t)
 294{
 295	unsigned nbytes;
 296	unsigned tx_empty_count;
 297	u32 fifo_status;
 298	unsigned max_n_32bit;
 299	unsigned i, count;
 300	unsigned int written_words;
 301	unsigned fifo_words_left;
 302	u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 303
 304	fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 305	tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
 306
 307	if (tspi->is_packed) {
 308		fifo_words_left = tx_empty_count * tspi->words_per_32bit;
 309		written_words = min(fifo_words_left, tspi->curr_dma_words);
 310		nbytes = written_words * tspi->bytes_per_word;
 311		max_n_32bit = DIV_ROUND_UP(nbytes, 4);
 312		for (count = 0; count < max_n_32bit; count++) {
 313			u32 x = 0;
 314
 315			for (i = 0; (i < 4) && nbytes; i++, nbytes--)
 316				x |= (u32)(*tx_buf++) << (i * 8);
 317			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 318		}
 319
 320		tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
 321	} else {
 322		unsigned int write_bytes;
 323		max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
 324		written_words = max_n_32bit;
 325		nbytes = written_words * tspi->bytes_per_word;
 326		if (nbytes > t->len - tspi->cur_pos)
 327			nbytes = t->len - tspi->cur_pos;
 328		write_bytes = nbytes;
 329		for (count = 0; count < max_n_32bit; count++) {
 330			u32 x = 0;
 331
 332			for (i = 0; nbytes && (i < tspi->bytes_per_word);
 333							i++, nbytes--)
 334				x |= (u32)(*tx_buf++) << (i * 8);
 335			tegra_spi_writel(tspi, x, SPI_TX_FIFO);
 336		}
 337
 338		tspi->cur_tx_pos += write_bytes;
 339	}
 340
 341	return written_words;
 342}
 343
 344static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
 345		struct tegra_spi_data *tspi, struct spi_transfer *t)
 346{
 347	unsigned rx_full_count;
 348	u32 fifo_status;
 349	unsigned i, count;
 350	unsigned int read_words = 0;
 351	unsigned len;
 352	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
 353
 354	fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 355	rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
 356	if (tspi->is_packed) {
 357		len = tspi->curr_dma_words * tspi->bytes_per_word;
 358		for (count = 0; count < rx_full_count; count++) {
 359			u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
 360
 361			for (i = 0; len && (i < 4); i++, len--)
 362				*rx_buf++ = (x >> i*8) & 0xFF;
 363		}
 364		read_words += tspi->curr_dma_words;
 365		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 366	} else {
 367		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 368		u8 bytes_per_word = tspi->bytes_per_word;
 369		unsigned int read_bytes;
 370
 371		len = rx_full_count * bytes_per_word;
 372		if (len > t->len - tspi->cur_pos)
 373			len = t->len - tspi->cur_pos;
 374		read_bytes = len;
 375		for (count = 0; count < rx_full_count; count++) {
 376			u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
 377
 378			for (i = 0; len && (i < bytes_per_word); i++, len--)
 379				*rx_buf++ = (x >> (i*8)) & 0xFF;
 380		}
 381		read_words += rx_full_count;
 382		tspi->cur_rx_pos += read_bytes;
 383	}
 384
 385	return read_words;
 386}
 387
 388static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
 389		struct tegra_spi_data *tspi, struct spi_transfer *t)
 390{
 391	/* Make the dma buffer to read by cpu */
 392	dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
 393				tspi->dma_buf_size, DMA_TO_DEVICE);
 394
 395	if (tspi->is_packed) {
 396		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 397
 398		memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
 399		tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 400	} else {
 401		unsigned int i;
 402		unsigned int count;
 403		u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
 404		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 405		unsigned int write_bytes;
 406
 407		if (consume > t->len - tspi->cur_pos)
 408			consume = t->len - tspi->cur_pos;
 409		write_bytes = consume;
 410		for (count = 0; count < tspi->curr_dma_words; count++) {
 411			u32 x = 0;
 412
 413			for (i = 0; consume && (i < tspi->bytes_per_word);
 414							i++, consume--)
 415				x |= (u32)(*tx_buf++) << (i * 8);
 416			tspi->tx_dma_buf[count] = x;
 417		}
 418
 419		tspi->cur_tx_pos += write_bytes;
 420	}
 421
 422	/* Make the dma buffer to read by dma */
 423	dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
 424				tspi->dma_buf_size, DMA_TO_DEVICE);
 425}
 426
 427static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
 428		struct tegra_spi_data *tspi, struct spi_transfer *t)
 429{
 430	/* Make the dma buffer to read by cpu */
 431	dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
 432		tspi->dma_buf_size, DMA_FROM_DEVICE);
 433
 434	if (tspi->is_packed) {
 435		unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
 436
 437		memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
 438		tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
 439	} else {
 440		unsigned int i;
 441		unsigned int count;
 442		unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
 443		u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
 444		unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
 445		unsigned int read_bytes;
 446
 447		if (consume > t->len - tspi->cur_pos)
 448			consume = t->len - tspi->cur_pos;
 449		read_bytes = consume;
 450		for (count = 0; count < tspi->curr_dma_words; count++) {
 451			u32 x = tspi->rx_dma_buf[count] & rx_mask;
 452
 453			for (i = 0; consume && (i < tspi->bytes_per_word);
 454							i++, consume--)
 455				*rx_buf++ = (x >> (i*8)) & 0xFF;
 456		}
 457
 458		tspi->cur_rx_pos += read_bytes;
 459	}
 460
 461	/* Make the dma buffer to read by dma */
 462	dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 463		tspi->dma_buf_size, DMA_FROM_DEVICE);
 464}
 465
 466static void tegra_spi_dma_complete(void *args)
 467{
 468	struct completion *dma_complete = args;
 469
 470	complete(dma_complete);
 471}
 472
 473static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
 474{
 475	reinit_completion(&tspi->tx_dma_complete);
 476	tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
 477				tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
 478				DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 479	if (!tspi->tx_dma_desc) {
 480		dev_err(tspi->dev, "Not able to get desc for Tx\n");
 481		return -EIO;
 482	}
 483
 484	tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
 485	tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
 486
 487	dmaengine_submit(tspi->tx_dma_desc);
 488	dma_async_issue_pending(tspi->tx_dma_chan);
 489	return 0;
 490}
 491
 492static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
 493{
 494	reinit_completion(&tspi->rx_dma_complete);
 495	tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
 496				tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
 497				DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
 498	if (!tspi->rx_dma_desc) {
 499		dev_err(tspi->dev, "Not able to get desc for Rx\n");
 500		return -EIO;
 501	}
 502
 503	tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
 504	tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
 505
 506	dmaengine_submit(tspi->rx_dma_desc);
 507	dma_async_issue_pending(tspi->rx_dma_chan);
 508	return 0;
 509}
 510
 511static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
 512{
 513	unsigned long timeout = jiffies + HZ;
 514	u32 status;
 515
 516	status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 517	if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 518		status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
 519		tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
 520		while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
 521			status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
 522			if (time_after(jiffies, timeout)) {
 523				dev_err(tspi->dev,
 524					"timeout waiting for fifo flush\n");
 525				return -EIO;
 526			}
 527
 528			udelay(1);
 529		}
 530	}
 531
 532	return 0;
 533}
 534
 535static int tegra_spi_start_dma_based_transfer(
 536		struct tegra_spi_data *tspi, struct spi_transfer *t)
 537{
 538	u32 val;
 539	unsigned int len;
 540	int ret = 0;
 541	u8 dma_burst;
 542	struct dma_slave_config dma_sconfig = {0};
 543
 544	val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
 545	tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 546
 547	if (tspi->is_packed)
 548		len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
 549					4) * 4;
 550	else
 551		len = tspi->curr_dma_words * 4;
 552
 553	/* Set attention level based on length of transfer */
 554	if (len & 0xF) {
 555		val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
 556		dma_burst = 1;
 557	} else if (((len) >> 4) & 0x1) {
 558		val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
 559		dma_burst = 4;
 560	} else {
 561		val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
 562		dma_burst = 8;
 563	}
 564
 565	if (!tspi->soc_data->has_intr_mask_reg) {
 566		if (tspi->cur_direction & DATA_DIR_TX)
 567			val |= SPI_IE_TX;
 568
 569		if (tspi->cur_direction & DATA_DIR_RX)
 570			val |= SPI_IE_RX;
 571	}
 572
 573	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 574	tspi->dma_control_reg = val;
 575
 576	dma_sconfig.device_fc = true;
 577	if (tspi->cur_direction & DATA_DIR_TX) {
 578		dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
 579		dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 580		dma_sconfig.dst_maxburst = dma_burst;
 581		ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
 582		if (ret < 0) {
 583			dev_err(tspi->dev,
 584				"DMA slave config failed: %d\n", ret);
 585			return ret;
 586		}
 587
 588		tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
 589		ret = tegra_spi_start_tx_dma(tspi, len);
 590		if (ret < 0) {
 591			dev_err(tspi->dev,
 592				"Starting tx dma failed, err %d\n", ret);
 593			return ret;
 594		}
 595	}
 596
 597	if (tspi->cur_direction & DATA_DIR_RX) {
 598		dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
 599		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 600		dma_sconfig.src_maxburst = dma_burst;
 601		ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
 602		if (ret < 0) {
 603			dev_err(tspi->dev,
 604				"DMA slave config failed: %d\n", ret);
 605			return ret;
 606		}
 607
 608		/* Make the dma buffer to read by dma */
 609		dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
 610				tspi->dma_buf_size, DMA_FROM_DEVICE);
 611
 612		ret = tegra_spi_start_rx_dma(tspi, len);
 613		if (ret < 0) {
 614			dev_err(tspi->dev,
 615				"Starting rx dma failed, err %d\n", ret);
 616			if (tspi->cur_direction & DATA_DIR_TX)
 617				dmaengine_terminate_all(tspi->tx_dma_chan);
 618			return ret;
 619		}
 620	}
 621	tspi->is_curr_dma_xfer = true;
 622	tspi->dma_control_reg = val;
 623
 624	val |= SPI_DMA_EN;
 625	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 626	return ret;
 627}
 628
 629static int tegra_spi_start_cpu_based_transfer(
 630		struct tegra_spi_data *tspi, struct spi_transfer *t)
 631{
 632	u32 val;
 633	unsigned cur_words;
 634
 635	if (tspi->cur_direction & DATA_DIR_TX)
 636		cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
 637	else
 638		cur_words = tspi->curr_dma_words;
 639
 640	val = SPI_DMA_BLK_SET(cur_words - 1);
 641	tegra_spi_writel(tspi, val, SPI_DMA_BLK);
 642
 643	val = 0;
 644	if (tspi->cur_direction & DATA_DIR_TX)
 645		val |= SPI_IE_TX;
 646
 647	if (tspi->cur_direction & DATA_DIR_RX)
 648		val |= SPI_IE_RX;
 649
 650	tegra_spi_writel(tspi, val, SPI_DMA_CTL);
 651	tspi->dma_control_reg = val;
 652
 653	tspi->is_curr_dma_xfer = false;
 654
 655	val = tspi->command1_reg;
 656	val |= SPI_PIO;
 657	tegra_spi_writel(tspi, val, SPI_COMMAND1);
 658	return 0;
 659}
 660
 661static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
 662			bool dma_to_memory)
 663{
 664	struct dma_chan *dma_chan;
 665	u32 *dma_buf;
 666	dma_addr_t dma_phys;
 
 667
 668	dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
 669	if (IS_ERR(dma_chan))
 670		return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
 671				     "Dma channel is not available\n");
 
 
 
 
 
 672
 673	dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
 674				&dma_phys, GFP_KERNEL);
 675	if (!dma_buf) {
 676		dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
 677		dma_release_channel(dma_chan);
 678		return -ENOMEM;
 679	}
 680
 681	if (dma_to_memory) {
 682		tspi->rx_dma_chan = dma_chan;
 683		tspi->rx_dma_buf = dma_buf;
 684		tspi->rx_dma_phys = dma_phys;
 685	} else {
 686		tspi->tx_dma_chan = dma_chan;
 687		tspi->tx_dma_buf = dma_buf;
 688		tspi->tx_dma_phys = dma_phys;
 689	}
 690	return 0;
 691}
 692
 693static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
 694	bool dma_to_memory)
 695{
 696	u32 *dma_buf;
 697	dma_addr_t dma_phys;
 698	struct dma_chan *dma_chan;
 699
 700	if (dma_to_memory) {
 701		dma_buf = tspi->rx_dma_buf;
 702		dma_chan = tspi->rx_dma_chan;
 703		dma_phys = tspi->rx_dma_phys;
 704		tspi->rx_dma_chan = NULL;
 705		tspi->rx_dma_buf = NULL;
 706	} else {
 707		dma_buf = tspi->tx_dma_buf;
 708		dma_chan = tspi->tx_dma_chan;
 709		dma_phys = tspi->tx_dma_phys;
 710		tspi->tx_dma_buf = NULL;
 711		tspi->tx_dma_chan = NULL;
 712	}
 713	if (!dma_chan)
 714		return;
 715
 716	dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
 717	dma_release_channel(dma_chan);
 718}
 719
 720static int tegra_spi_set_hw_cs_timing(struct spi_device *spi)
 
 721{
 722	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 723	struct spi_delay *setup = &spi->cs_setup;
 724	struct spi_delay *hold = &spi->cs_hold;
 725	struct spi_delay *inactive = &spi->cs_inactive;
 726	u8 setup_dly, hold_dly, inactive_dly;
 727	u32 setup_hold;
 728	u32 spi_cs_timing;
 729	u32 inactive_cycles;
 730	u8 cs_state;
 731
 732	if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
 733	    (hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
 734	    (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
 735		dev_err(&spi->dev,
 736			"Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
 737			SPI_DELAY_UNIT_SCK);
 738		return -EINVAL;
 739	}
 740
 741	setup_dly = setup ? setup->value : 0;
 742	hold_dly = hold ? hold->value : 0;
 743	inactive_dly = inactive ? inactive->value : 0;
 744
 745	setup_dly = min_t(u8, setup_dly, MAX_SETUP_HOLD_CYCLES);
 746	hold_dly = min_t(u8, hold_dly, MAX_SETUP_HOLD_CYCLES);
 747	if (setup_dly && hold_dly) {
 748		setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
 749		spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
 750						  spi->chip_select,
 751						  setup_hold);
 752		if (tspi->spi_cs_timing1 != spi_cs_timing) {
 753			tspi->spi_cs_timing1 = spi_cs_timing;
 754			tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
 755		}
 756	}
 757
 758	inactive_cycles = min_t(u8, inactive_dly, MAX_INACTIVE_CYCLES);
 759	if (inactive_cycles)
 760		inactive_cycles--;
 761	cs_state = inactive_cycles ? 0 : 1;
 762	spi_cs_timing = tspi->spi_cs_timing2;
 763	SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
 764					  cs_state);
 765	SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select,
 766				       inactive_cycles);
 767	if (tspi->spi_cs_timing2 != spi_cs_timing) {
 768		tspi->spi_cs_timing2 = spi_cs_timing;
 769		tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
 770	}
 771
 772	return 0;
 773}
 774
 775static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
 776					struct spi_transfer *t,
 777					bool is_first_of_msg,
 778					bool is_single_xfer)
 779{
 780	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 781	struct tegra_spi_client_data *cdata = spi->controller_data;
 782	u32 speed = t->speed_hz;
 783	u8 bits_per_word = t->bits_per_word;
 784	u32 command1, command2;
 785	int req_mode;
 786	u32 tx_tap = 0, rx_tap = 0;
 787
 788	if (speed != tspi->cur_speed) {
 789		clk_set_rate(tspi->clk, speed);
 790		tspi->cur_speed = speed;
 791	}
 792
 793	tspi->cur_spi = spi;
 794	tspi->cur_pos = 0;
 795	tspi->cur_rx_pos = 0;
 796	tspi->cur_tx_pos = 0;
 797	tspi->curr_xfer = t;
 798
 799	if (is_first_of_msg) {
 800		tegra_spi_clear_status(tspi);
 801
 802		command1 = tspi->def_command1_reg;
 803		command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 804
 805		command1 &= ~SPI_CONTROL_MODE_MASK;
 806		req_mode = spi->mode & 0x3;
 807		if (req_mode == SPI_MODE_0)
 808			command1 |= SPI_CONTROL_MODE_0;
 809		else if (req_mode == SPI_MODE_1)
 810			command1 |= SPI_CONTROL_MODE_1;
 811		else if (req_mode == SPI_MODE_2)
 812			command1 |= SPI_CONTROL_MODE_2;
 813		else if (req_mode == SPI_MODE_3)
 814			command1 |= SPI_CONTROL_MODE_3;
 815
 816		if (spi->mode & SPI_LSB_FIRST)
 817			command1 |= SPI_LSBIT_FE;
 818		else
 819			command1 &= ~SPI_LSBIT_FE;
 820
 821		if (spi->mode & SPI_3WIRE)
 822			command1 |= SPI_BIDIROE;
 823		else
 824			command1 &= ~SPI_BIDIROE;
 825
 826		if (tspi->cs_control) {
 827			if (tspi->cs_control != spi)
 828				tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 829			tspi->cs_control = NULL;
 830		} else
 831			tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 832
 833		/* GPIO based chip select control */
 834		if (spi->cs_gpiod)
 835			gpiod_set_value(spi->cs_gpiod, 1);
 836
 837		if (is_single_xfer && !(t->cs_change)) {
 838			tspi->use_hw_based_cs = true;
 839			command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
 840		} else {
 841			tspi->use_hw_based_cs = false;
 842			command1 |= SPI_CS_SW_HW;
 843			if (spi->mode & SPI_CS_HIGH)
 844				command1 |= SPI_CS_SW_VAL;
 845			else
 846				command1 &= ~SPI_CS_SW_VAL;
 847		}
 848
 849		if (tspi->last_used_cs != spi->chip_select) {
 850			if (cdata && cdata->tx_clk_tap_delay)
 851				tx_tap = cdata->tx_clk_tap_delay;
 852			if (cdata && cdata->rx_clk_tap_delay)
 853				rx_tap = cdata->rx_clk_tap_delay;
 854			command2 = SPI_TX_TAP_DELAY(tx_tap) |
 855				   SPI_RX_TAP_DELAY(rx_tap);
 856			if (command2 != tspi->def_command2_reg)
 857				tegra_spi_writel(tspi, command2, SPI_COMMAND2);
 858			tspi->last_used_cs = spi->chip_select;
 859		}
 860
 861	} else {
 862		command1 = tspi->command1_reg;
 863		command1 &= ~SPI_BIT_LENGTH(~0);
 864		command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
 865	}
 866
 867	return command1;
 868}
 869
 870static int tegra_spi_start_transfer_one(struct spi_device *spi,
 871		struct spi_transfer *t, u32 command1)
 872{
 873	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 874	unsigned total_fifo_words;
 875	int ret;
 876
 877	total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
 878
 879	if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
 880		command1 |= SPI_BOTH_EN_BIT;
 881	else
 882		command1 &= ~SPI_BOTH_EN_BIT;
 883
 884	if (tspi->is_packed)
 885		command1 |= SPI_PACKED;
 886	else
 887		command1 &= ~SPI_PACKED;
 888
 889	command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
 890	tspi->cur_direction = 0;
 891	if (t->rx_buf) {
 892		command1 |= SPI_RX_EN;
 893		tspi->cur_direction |= DATA_DIR_RX;
 894	}
 895	if (t->tx_buf) {
 896		command1 |= SPI_TX_EN;
 897		tspi->cur_direction |= DATA_DIR_TX;
 898	}
 899	command1 |= SPI_CS_SEL(spi->chip_select);
 900	tegra_spi_writel(tspi, command1, SPI_COMMAND1);
 901	tspi->command1_reg = command1;
 902
 903	dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
 904		tspi->def_command1_reg, (unsigned)command1);
 905
 906	ret = tegra_spi_flush_fifos(tspi);
 907	if (ret < 0)
 908		return ret;
 909	if (total_fifo_words > SPI_FIFO_DEPTH)
 910		ret = tegra_spi_start_dma_based_transfer(tspi, t);
 911	else
 912		ret = tegra_spi_start_cpu_based_transfer(tspi, t);
 913	return ret;
 914}
 915
 916static struct tegra_spi_client_data
 917	*tegra_spi_parse_cdata_dt(struct spi_device *spi)
 918{
 919	struct tegra_spi_client_data *cdata;
 920	struct device_node *slave_np;
 921
 922	slave_np = spi->dev.of_node;
 923	if (!slave_np) {
 924		dev_dbg(&spi->dev, "device node not found\n");
 925		return NULL;
 926	}
 927
 928	cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
 929	if (!cdata)
 930		return NULL;
 931
 932	of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
 933			     &cdata->tx_clk_tap_delay);
 934	of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
 935			     &cdata->rx_clk_tap_delay);
 936	return cdata;
 937}
 938
 939static void tegra_spi_cleanup(struct spi_device *spi)
 940{
 941	struct tegra_spi_client_data *cdata = spi->controller_data;
 942
 943	spi->controller_data = NULL;
 944	if (spi->dev.of_node)
 945		kfree(cdata);
 946}
 947
 948static int tegra_spi_setup(struct spi_device *spi)
 949{
 950	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
 951	struct tegra_spi_client_data *cdata = spi->controller_data;
 952	u32 val;
 953	unsigned long flags;
 954	int ret;
 955
 956	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
 957		spi->bits_per_word,
 958		spi->mode & SPI_CPOL ? "" : "~",
 959		spi->mode & SPI_CPHA ? "" : "~",
 960		spi->max_speed_hz);
 961
 962	if (!cdata) {
 963		cdata = tegra_spi_parse_cdata_dt(spi);
 964		spi->controller_data = cdata;
 965	}
 966
 967	ret = pm_runtime_resume_and_get(tspi->dev);
 968	if (ret < 0) {
 969		dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
 970		if (cdata)
 971			tegra_spi_cleanup(spi);
 972		return ret;
 973	}
 974
 975	if (tspi->soc_data->has_intr_mask_reg) {
 976		val = tegra_spi_readl(tspi, SPI_INTR_MASK);
 977		val &= ~SPI_INTR_ALL_MASK;
 978		tegra_spi_writel(tspi, val, SPI_INTR_MASK);
 979	}
 980
 981	spin_lock_irqsave(&tspi->lock, flags);
 982	/* GPIO based chip select control */
 983	if (spi->cs_gpiod)
 984		gpiod_set_value(spi->cs_gpiod, 0);
 985
 986	val = tspi->def_command1_reg;
 987	if (spi->mode & SPI_CS_HIGH)
 988		val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
 989	else
 990		val |= SPI_CS_POL_INACTIVE(spi->chip_select);
 991	tspi->def_command1_reg = val;
 992	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
 993	spin_unlock_irqrestore(&tspi->lock, flags);
 994
 995	pm_runtime_put(tspi->dev);
 996	return 0;
 997}
 998
 
 
 
 
 
 
 
 
 
 
 
 999static void tegra_spi_transfer_end(struct spi_device *spi)
1000{
1001	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
1002	int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
1003
1004	/* GPIO based chip select control */
1005	if (spi->cs_gpiod)
1006		gpiod_set_value(spi->cs_gpiod, 0);
1007
1008	if (!tspi->use_hw_based_cs) {
1009		if (cs_val)
1010			tspi->command1_reg |= SPI_CS_SW_VAL;
1011		else
1012			tspi->command1_reg &= ~SPI_CS_SW_VAL;
1013		tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1014	}
1015
1016	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1017}
1018
1019static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
1020{
1021	dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
1022	dev_dbg(tspi->dev, "Command1:    0x%08x | Command2:    0x%08x\n",
1023		tegra_spi_readl(tspi, SPI_COMMAND1),
1024		tegra_spi_readl(tspi, SPI_COMMAND2));
1025	dev_dbg(tspi->dev, "DMA_CTL:     0x%08x | DMA_BLK:     0x%08x\n",
1026		tegra_spi_readl(tspi, SPI_DMA_CTL),
1027		tegra_spi_readl(tspi, SPI_DMA_BLK));
1028	dev_dbg(tspi->dev, "TRANS_STAT:  0x%08x | FIFO_STATUS: 0x%08x\n",
1029		tegra_spi_readl(tspi, SPI_TRANS_STATUS),
1030		tegra_spi_readl(tspi, SPI_FIFO_STATUS));
1031}
1032
1033static int tegra_spi_transfer_one_message(struct spi_master *master,
1034			struct spi_message *msg)
1035{
1036	bool is_first_msg = true;
1037	struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1038	struct spi_transfer *xfer;
1039	struct spi_device *spi = msg->spi;
1040	int ret;
1041	bool skip = false;
1042	int single_xfer;
1043
1044	msg->status = 0;
1045	msg->actual_length = 0;
1046
1047	single_xfer = list_is_singular(&msg->transfers);
1048	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1049		u32 cmd1;
1050
1051		reinit_completion(&tspi->xfer_completion);
1052
1053		cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
1054						    single_xfer);
1055
1056		if (!xfer->len) {
1057			ret = 0;
1058			skip = true;
1059			goto complete_xfer;
1060		}
1061
1062		ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
1063		if (ret < 0) {
1064			dev_err(tspi->dev,
1065				"spi can not start transfer, err %d\n", ret);
1066			goto complete_xfer;
1067		}
1068
1069		is_first_msg = false;
1070		ret = wait_for_completion_timeout(&tspi->xfer_completion,
1071						SPI_DMA_TIMEOUT);
1072		if (WARN_ON(ret == 0)) {
1073			dev_err(tspi->dev, "spi transfer timeout\n");
 
1074			if (tspi->is_curr_dma_xfer &&
1075			    (tspi->cur_direction & DATA_DIR_TX))
1076				dmaengine_terminate_all(tspi->tx_dma_chan);
1077			if (tspi->is_curr_dma_xfer &&
1078			    (tspi->cur_direction & DATA_DIR_RX))
1079				dmaengine_terminate_all(tspi->rx_dma_chan);
1080			ret = -EIO;
1081			tegra_spi_dump_regs(tspi);
1082			tegra_spi_flush_fifos(tspi);
1083			reset_control_assert(tspi->rst);
1084			udelay(2);
1085			reset_control_deassert(tspi->rst);
1086			tspi->last_used_cs = master->num_chipselect + 1;
1087			goto complete_xfer;
1088		}
1089
1090		if (tspi->tx_status ||  tspi->rx_status) {
1091			dev_err(tspi->dev, "Error in Transfer\n");
1092			ret = -EIO;
1093			tegra_spi_dump_regs(tspi);
1094			goto complete_xfer;
1095		}
1096		msg->actual_length += xfer->len;
1097
1098complete_xfer:
1099		if (ret < 0 || skip) {
1100			tegra_spi_transfer_end(spi);
1101			spi_transfer_delay_exec(xfer);
1102			goto exit;
1103		} else if (list_is_last(&xfer->transfer_list,
1104					&msg->transfers)) {
1105			if (xfer->cs_change)
1106				tspi->cs_control = spi;
1107			else {
1108				tegra_spi_transfer_end(spi);
1109				spi_transfer_delay_exec(xfer);
1110			}
1111		} else if (xfer->cs_change) {
1112			tegra_spi_transfer_end(spi);
1113			spi_transfer_delay_exec(xfer);
1114		}
1115
1116	}
1117	ret = 0;
1118exit:
1119	msg->status = ret;
1120	spi_finalize_current_message(master);
1121	return ret;
1122}
1123
1124static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
1125{
1126	struct spi_transfer *t = tspi->curr_xfer;
1127	unsigned long flags;
1128
1129	spin_lock_irqsave(&tspi->lock, flags);
1130	if (tspi->tx_status ||  tspi->rx_status) {
1131		dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1132			tspi->status_reg);
1133		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1134			tspi->command1_reg, tspi->dma_control_reg);
1135		tegra_spi_dump_regs(tspi);
1136		tegra_spi_flush_fifos(tspi);
1137		complete(&tspi->xfer_completion);
1138		spin_unlock_irqrestore(&tspi->lock, flags);
1139		reset_control_assert(tspi->rst);
1140		udelay(2);
1141		reset_control_deassert(tspi->rst);
1142		return IRQ_HANDLED;
1143	}
1144
1145	if (tspi->cur_direction & DATA_DIR_RX)
1146		tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1147
1148	if (tspi->cur_direction & DATA_DIR_TX)
1149		tspi->cur_pos = tspi->cur_tx_pos;
1150	else
1151		tspi->cur_pos = tspi->cur_rx_pos;
1152
1153	if (tspi->cur_pos == t->len) {
1154		complete(&tspi->xfer_completion);
1155		goto exit;
1156	}
1157
1158	tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1159	tegra_spi_start_cpu_based_transfer(tspi, t);
1160exit:
1161	spin_unlock_irqrestore(&tspi->lock, flags);
1162	return IRQ_HANDLED;
1163}
1164
1165static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1166{
1167	struct spi_transfer *t = tspi->curr_xfer;
1168	long wait_status;
1169	int err = 0;
1170	unsigned total_fifo_words;
1171	unsigned long flags;
1172
1173	/* Abort dmas if any error */
1174	if (tspi->cur_direction & DATA_DIR_TX) {
1175		if (tspi->tx_status) {
1176			dmaengine_terminate_all(tspi->tx_dma_chan);
1177			err += 1;
1178		} else {
1179			wait_status = wait_for_completion_interruptible_timeout(
1180				&tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1181			if (wait_status <= 0) {
1182				dmaengine_terminate_all(tspi->tx_dma_chan);
1183				dev_err(tspi->dev, "TxDma Xfer failed\n");
1184				err += 1;
1185			}
1186		}
1187	}
1188
1189	if (tspi->cur_direction & DATA_DIR_RX) {
1190		if (tspi->rx_status) {
1191			dmaengine_terminate_all(tspi->rx_dma_chan);
1192			err += 2;
1193		} else {
1194			wait_status = wait_for_completion_interruptible_timeout(
1195				&tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1196			if (wait_status <= 0) {
1197				dmaengine_terminate_all(tspi->rx_dma_chan);
1198				dev_err(tspi->dev, "RxDma Xfer failed\n");
1199				err += 2;
1200			}
1201		}
1202	}
1203
1204	spin_lock_irqsave(&tspi->lock, flags);
1205	if (err) {
1206		dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1207			tspi->status_reg);
1208		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1209			tspi->command1_reg, tspi->dma_control_reg);
1210		tegra_spi_dump_regs(tspi);
1211		tegra_spi_flush_fifos(tspi);
1212		complete(&tspi->xfer_completion);
1213		spin_unlock_irqrestore(&tspi->lock, flags);
1214		reset_control_assert(tspi->rst);
1215		udelay(2);
1216		reset_control_deassert(tspi->rst);
1217		return IRQ_HANDLED;
1218	}
1219
1220	if (tspi->cur_direction & DATA_DIR_RX)
1221		tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1222
1223	if (tspi->cur_direction & DATA_DIR_TX)
1224		tspi->cur_pos = tspi->cur_tx_pos;
1225	else
1226		tspi->cur_pos = tspi->cur_rx_pos;
1227
1228	if (tspi->cur_pos == t->len) {
1229		complete(&tspi->xfer_completion);
1230		goto exit;
1231	}
1232
1233	/* Continue transfer in current message */
1234	total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1235							tspi, t);
1236	if (total_fifo_words > SPI_FIFO_DEPTH)
1237		err = tegra_spi_start_dma_based_transfer(tspi, t);
1238	else
1239		err = tegra_spi_start_cpu_based_transfer(tspi, t);
1240
1241exit:
1242	spin_unlock_irqrestore(&tspi->lock, flags);
1243	return IRQ_HANDLED;
1244}
1245
1246static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1247{
1248	struct tegra_spi_data *tspi = context_data;
1249
1250	if (!tspi->is_curr_dma_xfer)
1251		return handle_cpu_based_xfer(tspi);
1252	return handle_dma_based_xfer(tspi);
1253}
1254
1255static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1256{
1257	struct tegra_spi_data *tspi = context_data;
1258
1259	tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1260	if (tspi->cur_direction & DATA_DIR_TX)
1261		tspi->tx_status = tspi->status_reg &
1262					(SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1263
1264	if (tspi->cur_direction & DATA_DIR_RX)
1265		tspi->rx_status = tspi->status_reg &
1266					(SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1267	tegra_spi_clear_status(tspi);
1268
1269	return IRQ_WAKE_THREAD;
1270}
1271
1272static struct tegra_spi_soc_data tegra114_spi_soc_data = {
1273	.has_intr_mask_reg = false,
1274};
1275
1276static struct tegra_spi_soc_data tegra124_spi_soc_data = {
1277	.has_intr_mask_reg = false,
1278};
1279
1280static struct tegra_spi_soc_data tegra210_spi_soc_data = {
1281	.has_intr_mask_reg = true,
1282};
1283
1284static const struct of_device_id tegra_spi_of_match[] = {
1285	{
1286		.compatible = "nvidia,tegra114-spi",
1287		.data	    = &tegra114_spi_soc_data,
1288	}, {
1289		.compatible = "nvidia,tegra124-spi",
1290		.data	    = &tegra124_spi_soc_data,
1291	}, {
1292		.compatible = "nvidia,tegra210-spi",
1293		.data	    = &tegra210_spi_soc_data,
1294	},
1295	{}
1296};
1297MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1298
1299static int tegra_spi_probe(struct platform_device *pdev)
1300{
1301	struct spi_master	*master;
1302	struct tegra_spi_data	*tspi;
1303	struct resource		*r;
1304	int ret, spi_irq;
1305	int bus_num;
1306
1307	master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1308	if (!master) {
1309		dev_err(&pdev->dev, "master allocation failed\n");
1310		return -ENOMEM;
1311	}
1312	platform_set_drvdata(pdev, master);
1313	tspi = spi_master_get_devdata(master);
1314
1315	if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1316				 &master->max_speed_hz))
1317		master->max_speed_hz = 25000000; /* 25MHz */
1318
1319	/* the spi->mode bits understood by this driver: */
1320	master->use_gpio_descriptors = true;
1321	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1322			    SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
1323	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1324	master->setup = tegra_spi_setup;
1325	master->cleanup = tegra_spi_cleanup;
1326	master->transfer_one_message = tegra_spi_transfer_one_message;
1327	master->set_cs_timing = tegra_spi_set_hw_cs_timing;
1328	master->num_chipselect = MAX_CHIP_SELECT;
1329	master->auto_runtime_pm = true;
1330	bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1331	if (bus_num >= 0)
1332		master->bus_num = bus_num;
1333
1334	tspi->master = master;
1335	tspi->dev = &pdev->dev;
1336	spin_lock_init(&tspi->lock);
1337
1338	tspi->soc_data = of_device_get_match_data(&pdev->dev);
1339	if (!tspi->soc_data) {
1340		dev_err(&pdev->dev, "unsupported tegra\n");
1341		ret = -ENODEV;
1342		goto exit_free_master;
1343	}
1344
1345	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1346	tspi->base = devm_ioremap_resource(&pdev->dev, r);
1347	if (IS_ERR(tspi->base)) {
1348		ret = PTR_ERR(tspi->base);
1349		goto exit_free_master;
1350	}
1351	tspi->phys = r->start;
1352
1353	spi_irq = platform_get_irq(pdev, 0);
1354	if (spi_irq < 0) {
1355		ret = spi_irq;
1356		goto exit_free_master;
1357	}
1358	tspi->irq = spi_irq;
1359
1360	tspi->clk = devm_clk_get(&pdev->dev, "spi");
1361	if (IS_ERR(tspi->clk)) {
1362		dev_err(&pdev->dev, "can not get clock\n");
1363		ret = PTR_ERR(tspi->clk);
1364		goto exit_free_master;
1365	}
1366
1367	tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1368	if (IS_ERR(tspi->rst)) {
1369		dev_err(&pdev->dev, "can not get reset\n");
1370		ret = PTR_ERR(tspi->rst);
1371		goto exit_free_master;
1372	}
1373
1374	tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1375	tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1376
1377	ret = tegra_spi_init_dma_param(tspi, true);
1378	if (ret < 0)
1379		goto exit_free_master;
1380	ret = tegra_spi_init_dma_param(tspi, false);
1381	if (ret < 0)
1382		goto exit_rx_dma_free;
1383	tspi->max_buf_size = tspi->dma_buf_size;
1384	init_completion(&tspi->tx_dma_complete);
1385	init_completion(&tspi->rx_dma_complete);
1386
1387	init_completion(&tspi->xfer_completion);
1388
1389	pm_runtime_enable(&pdev->dev);
1390	if (!pm_runtime_enabled(&pdev->dev)) {
1391		ret = tegra_spi_runtime_resume(&pdev->dev);
1392		if (ret)
1393			goto exit_pm_disable;
1394	}
1395
1396	ret = pm_runtime_resume_and_get(&pdev->dev);
1397	if (ret < 0) {
1398		dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1399		goto exit_pm_disable;
1400	}
1401
1402	reset_control_assert(tspi->rst);
1403	udelay(2);
1404	reset_control_deassert(tspi->rst);
1405	tspi->def_command1_reg  = SPI_M_S;
1406	tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1407	tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
1408	tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
1409	tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1410	tspi->last_used_cs = master->num_chipselect + 1;
1411	pm_runtime_put(&pdev->dev);
1412	ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1413				   tegra_spi_isr_thread, IRQF_ONESHOT,
1414				   dev_name(&pdev->dev), tspi);
1415	if (ret < 0) {
1416		dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1417			tspi->irq);
1418		goto exit_pm_disable;
1419	}
1420
1421	master->dev.of_node = pdev->dev.of_node;
1422	ret = devm_spi_register_master(&pdev->dev, master);
1423	if (ret < 0) {
1424		dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1425		goto exit_free_irq;
1426	}
1427	return ret;
1428
1429exit_free_irq:
1430	free_irq(spi_irq, tspi);
1431exit_pm_disable:
1432	pm_runtime_disable(&pdev->dev);
1433	if (!pm_runtime_status_suspended(&pdev->dev))
1434		tegra_spi_runtime_suspend(&pdev->dev);
1435	tegra_spi_deinit_dma_param(tspi, false);
1436exit_rx_dma_free:
1437	tegra_spi_deinit_dma_param(tspi, true);
1438exit_free_master:
1439	spi_master_put(master);
1440	return ret;
1441}
1442
1443static int tegra_spi_remove(struct platform_device *pdev)
1444{
1445	struct spi_master *master = platform_get_drvdata(pdev);
1446	struct tegra_spi_data	*tspi = spi_master_get_devdata(master);
1447
1448	free_irq(tspi->irq, tspi);
1449
1450	if (tspi->tx_dma_chan)
1451		tegra_spi_deinit_dma_param(tspi, false);
1452
1453	if (tspi->rx_dma_chan)
1454		tegra_spi_deinit_dma_param(tspi, true);
1455
1456	pm_runtime_disable(&pdev->dev);
1457	if (!pm_runtime_status_suspended(&pdev->dev))
1458		tegra_spi_runtime_suspend(&pdev->dev);
1459
1460	return 0;
1461}
1462
1463#ifdef CONFIG_PM_SLEEP
1464static int tegra_spi_suspend(struct device *dev)
1465{
1466	struct spi_master *master = dev_get_drvdata(dev);
1467
1468	return spi_master_suspend(master);
1469}
1470
1471static int tegra_spi_resume(struct device *dev)
1472{
1473	struct spi_master *master = dev_get_drvdata(dev);
1474	struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1475	int ret;
1476
1477	ret = pm_runtime_resume_and_get(dev);
1478	if (ret < 0) {
1479		dev_err(dev, "pm runtime failed, e = %d\n", ret);
1480		return ret;
1481	}
1482	tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1483	tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
1484	tspi->last_used_cs = master->num_chipselect + 1;
1485	pm_runtime_put(dev);
1486
1487	return spi_master_resume(master);
1488}
1489#endif
1490
1491static int tegra_spi_runtime_suspend(struct device *dev)
1492{
1493	struct spi_master *master = dev_get_drvdata(dev);
1494	struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1495
1496	/* Flush all write which are in PPSB queue by reading back */
1497	tegra_spi_readl(tspi, SPI_COMMAND1);
1498
1499	clk_disable_unprepare(tspi->clk);
1500	return 0;
1501}
1502
1503static int tegra_spi_runtime_resume(struct device *dev)
1504{
1505	struct spi_master *master = dev_get_drvdata(dev);
1506	struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1507	int ret;
1508
1509	ret = clk_prepare_enable(tspi->clk);
1510	if (ret < 0) {
1511		dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1512		return ret;
1513	}
1514	return 0;
1515}
1516
1517static const struct dev_pm_ops tegra_spi_pm_ops = {
1518	SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1519		tegra_spi_runtime_resume, NULL)
1520	SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1521};
1522static struct platform_driver tegra_spi_driver = {
1523	.driver = {
1524		.name		= "spi-tegra114",
1525		.pm		= &tegra_spi_pm_ops,
1526		.of_match_table	= tegra_spi_of_match,
1527	},
1528	.probe =	tegra_spi_probe,
1529	.remove =	tegra_spi_remove,
1530};
1531module_platform_driver(tegra_spi_driver);
1532
1533MODULE_ALIAS("platform:spi-tegra114");
1534MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1535MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1536MODULE_LICENSE("GPL v2");