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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4#include <linux/of.h>
5#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/rtc.h>
8#include <linux/platform_device.h>
9#include <linux/pm.h>
10#include <linux/pm_wakeirq.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14
15/* RTC Register offsets from RTC CTRL REG */
16#define PM8XXX_ALARM_CTRL_OFFSET 0x01
17#define PM8XXX_RTC_WRITE_OFFSET 0x02
18#define PM8XXX_RTC_READ_OFFSET 0x06
19#define PM8XXX_ALARM_RW_OFFSET 0x0A
20
21/* RTC_CTRL register bit fields */
22#define PM8xxx_RTC_ENABLE BIT(7)
23#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
24#define PM8xxx_RTC_ALARM_ENABLE BIT(7)
25
26#define NUM_8_BIT_RTC_REGS 0x4
27
28/**
29 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
30 * @ctrl: base address of control register
31 * @write: base address of write register
32 * @read: base address of read register
33 * @alarm_ctrl: base address of alarm control register
34 * @alarm_ctrl2: base address of alarm control2 register
35 * @alarm_rw: base address of alarm read-write register
36 * @alarm_en: alarm enable mask
37 */
38struct pm8xxx_rtc_regs {
39 unsigned int ctrl;
40 unsigned int write;
41 unsigned int read;
42 unsigned int alarm_ctrl;
43 unsigned int alarm_ctrl2;
44 unsigned int alarm_rw;
45 unsigned int alarm_en;
46};
47
48/**
49 * struct pm8xxx_rtc - rtc driver internal structure
50 * @rtc: rtc device for this driver.
51 * @regmap: regmap used to access RTC registers
52 * @allow_set_time: indicates whether writing to the RTC is allowed
53 * @rtc_alarm_irq: rtc alarm irq number.
54 * @regs: rtc registers description.
55 * @rtc_dev: device structure.
56 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
57 */
58struct pm8xxx_rtc {
59 struct rtc_device *rtc;
60 struct regmap *regmap;
61 bool allow_set_time;
62 int rtc_alarm_irq;
63 const struct pm8xxx_rtc_regs *regs;
64 struct device *rtc_dev;
65 spinlock_t ctrl_reg_lock;
66};
67
68/*
69 * Steps to write the RTC registers.
70 * 1. Disable alarm if enabled.
71 * 2. Disable rtc if enabled.
72 * 3. Write 0x00 to LSB.
73 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
74 * 5. Enable rtc if disabled in step 2.
75 * 6. Enable alarm if disabled in step 1.
76 */
77static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
78{
79 int rc, i;
80 unsigned long secs, irq_flags;
81 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
82 unsigned int ctrl_reg, rtc_ctrl_reg;
83 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
84 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
85
86 if (!rtc_dd->allow_set_time)
87 return -ENODEV;
88
89 secs = rtc_tm_to_time64(tm);
90
91 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
92
93 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
94 value[i] = secs & 0xFF;
95 secs >>= 8;
96 }
97
98 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
99
100 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
101 if (rc)
102 goto rtc_rw_fail;
103
104 if (ctrl_reg & regs->alarm_en) {
105 alarm_enabled = 1;
106 ctrl_reg &= ~regs->alarm_en;
107 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
108 if (rc) {
109 dev_err(dev, "Write to RTC Alarm control register failed\n");
110 goto rtc_rw_fail;
111 }
112 }
113
114 /* Disable RTC H/w before writing on RTC register */
115 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
116 if (rc)
117 goto rtc_rw_fail;
118
119 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
120 rtc_disabled = 1;
121 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
122 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
123 if (rc) {
124 dev_err(dev, "Write to RTC control register failed\n");
125 goto rtc_rw_fail;
126 }
127 }
128
129 /* Write 0 to Byte[0] */
130 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
131 if (rc) {
132 dev_err(dev, "Write to RTC write data register failed\n");
133 goto rtc_rw_fail;
134 }
135
136 /* Write Byte[1], Byte[2], Byte[3] */
137 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
138 &value[1], sizeof(value) - 1);
139 if (rc) {
140 dev_err(dev, "Write to RTC write data register failed\n");
141 goto rtc_rw_fail;
142 }
143
144 /* Write Byte[0] */
145 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
146 if (rc) {
147 dev_err(dev, "Write to RTC write data register failed\n");
148 goto rtc_rw_fail;
149 }
150
151 /* Enable RTC H/w after writing on RTC register */
152 if (rtc_disabled) {
153 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
154 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
155 if (rc) {
156 dev_err(dev, "Write to RTC control register failed\n");
157 goto rtc_rw_fail;
158 }
159 }
160
161 if (alarm_enabled) {
162 ctrl_reg |= regs->alarm_en;
163 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
164 if (rc) {
165 dev_err(dev, "Write to RTC Alarm control register failed\n");
166 goto rtc_rw_fail;
167 }
168 }
169
170rtc_rw_fail:
171 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
172
173 return rc;
174}
175
176static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
177{
178 int rc;
179 u8 value[NUM_8_BIT_RTC_REGS];
180 unsigned long secs;
181 unsigned int reg;
182 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
183 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
184
185 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
186 if (rc) {
187 dev_err(dev, "RTC read data register failed\n");
188 return rc;
189 }
190
191 /*
192 * Read the LSB again and check if there has been a carry over.
193 * If there is, redo the read operation.
194 */
195 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
196 if (rc < 0) {
197 dev_err(dev, "RTC read data register failed\n");
198 return rc;
199 }
200
201 if (unlikely(reg < value[0])) {
202 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
203 value, sizeof(value));
204 if (rc) {
205 dev_err(dev, "RTC read data register failed\n");
206 return rc;
207 }
208 }
209
210 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
211 ((unsigned long)value[3] << 24);
212
213 rtc_time64_to_tm(secs, tm);
214
215 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
216
217 return 0;
218}
219
220static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
221{
222 int rc, i;
223 u8 value[NUM_8_BIT_RTC_REGS];
224 unsigned int ctrl_reg;
225 unsigned long secs, irq_flags;
226 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
227 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
228
229 secs = rtc_tm_to_time64(&alarm->time);
230
231 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
232 value[i] = secs & 0xFF;
233 secs >>= 8;
234 }
235
236 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
237
238 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
239 sizeof(value));
240 if (rc) {
241 dev_err(dev, "Write to RTC ALARM register failed\n");
242 goto rtc_rw_fail;
243 }
244
245 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
246 if (rc)
247 goto rtc_rw_fail;
248
249 if (alarm->enabled)
250 ctrl_reg |= regs->alarm_en;
251 else
252 ctrl_reg &= ~regs->alarm_en;
253
254 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
255 if (rc) {
256 dev_err(dev, "Write to RTC alarm control register failed\n");
257 goto rtc_rw_fail;
258 }
259
260 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
261 &alarm->time, &alarm->time);
262rtc_rw_fail:
263 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
264 return rc;
265}
266
267static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268{
269 int rc;
270 unsigned int ctrl_reg;
271 u8 value[NUM_8_BIT_RTC_REGS];
272 unsigned long secs;
273 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
274 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
275
276 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
277 sizeof(value));
278 if (rc) {
279 dev_err(dev, "RTC alarm time read failed\n");
280 return rc;
281 }
282
283 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
284 ((unsigned long)value[3] << 24);
285
286 rtc_time64_to_tm(secs, &alarm->time);
287
288 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
289 if (rc) {
290 dev_err(dev, "Read from RTC alarm control register failed\n");
291 return rc;
292 }
293 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
294
295 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
296 &alarm->time, &alarm->time);
297
298 return 0;
299}
300
301static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
302{
303 int rc;
304 unsigned long irq_flags;
305 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
306 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
307 unsigned int ctrl_reg;
308 u8 value[NUM_8_BIT_RTC_REGS] = {0};
309
310 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
311
312 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
313 if (rc)
314 goto rtc_rw_fail;
315
316 if (enable)
317 ctrl_reg |= regs->alarm_en;
318 else
319 ctrl_reg &= ~regs->alarm_en;
320
321 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
322 if (rc) {
323 dev_err(dev, "Write to RTC control register failed\n");
324 goto rtc_rw_fail;
325 }
326
327 /* Clear Alarm register */
328 if (!enable) {
329 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
330 sizeof(value));
331 if (rc) {
332 dev_err(dev, "Clear RTC ALARM register failed\n");
333 goto rtc_rw_fail;
334 }
335 }
336
337rtc_rw_fail:
338 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
339 return rc;
340}
341
342static const struct rtc_class_ops pm8xxx_rtc_ops = {
343 .read_time = pm8xxx_rtc_read_time,
344 .set_time = pm8xxx_rtc_set_time,
345 .set_alarm = pm8xxx_rtc_set_alarm,
346 .read_alarm = pm8xxx_rtc_read_alarm,
347 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
348};
349
350static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
351{
352 struct pm8xxx_rtc *rtc_dd = dev_id;
353 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
354 unsigned int ctrl_reg;
355 int rc;
356
357 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
358
359 spin_lock(&rtc_dd->ctrl_reg_lock);
360
361 /* Clear the alarm enable bit */
362 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
363 if (rc) {
364 spin_unlock(&rtc_dd->ctrl_reg_lock);
365 goto rtc_alarm_handled;
366 }
367
368 ctrl_reg &= ~regs->alarm_en;
369
370 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
371 if (rc) {
372 spin_unlock(&rtc_dd->ctrl_reg_lock);
373 dev_err(rtc_dd->rtc_dev,
374 "Write to alarm control register failed\n");
375 goto rtc_alarm_handled;
376 }
377
378 spin_unlock(&rtc_dd->ctrl_reg_lock);
379
380 /* Clear RTC alarm register */
381 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
382 if (rc) {
383 dev_err(rtc_dd->rtc_dev,
384 "RTC Alarm control2 register read failed\n");
385 goto rtc_alarm_handled;
386 }
387
388 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
389 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
390 if (rc)
391 dev_err(rtc_dd->rtc_dev,
392 "Write to RTC Alarm control2 register failed\n");
393
394rtc_alarm_handled:
395 return IRQ_HANDLED;
396}
397
398static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
399{
400 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
401 unsigned int ctrl_reg;
402 int rc;
403
404 /* Check if the RTC is on, else turn it on */
405 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
406 if (rc)
407 return rc;
408
409 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
410 ctrl_reg |= PM8xxx_RTC_ENABLE;
411 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
412 if (rc)
413 return rc;
414 }
415
416 return 0;
417}
418
419static const struct pm8xxx_rtc_regs pm8921_regs = {
420 .ctrl = 0x11d,
421 .write = 0x11f,
422 .read = 0x123,
423 .alarm_rw = 0x127,
424 .alarm_ctrl = 0x11d,
425 .alarm_ctrl2 = 0x11e,
426 .alarm_en = BIT(1),
427};
428
429static const struct pm8xxx_rtc_regs pm8058_regs = {
430 .ctrl = 0x1e8,
431 .write = 0x1ea,
432 .read = 0x1ee,
433 .alarm_rw = 0x1f2,
434 .alarm_ctrl = 0x1e8,
435 .alarm_ctrl2 = 0x1e9,
436 .alarm_en = BIT(1),
437};
438
439static const struct pm8xxx_rtc_regs pm8941_regs = {
440 .ctrl = 0x6046,
441 .write = 0x6040,
442 .read = 0x6048,
443 .alarm_rw = 0x6140,
444 .alarm_ctrl = 0x6146,
445 .alarm_ctrl2 = 0x6148,
446 .alarm_en = BIT(7),
447};
448
449static const struct pm8xxx_rtc_regs pmk8350_regs = {
450 .ctrl = 0x6146,
451 .write = 0x6140,
452 .read = 0x6148,
453 .alarm_rw = 0x6240,
454 .alarm_ctrl = 0x6246,
455 .alarm_ctrl2 = 0x6248,
456 .alarm_en = BIT(7),
457};
458
459/*
460 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
461 */
462static const struct of_device_id pm8xxx_id_table[] = {
463 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
464 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
465 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
466 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
467 { },
468};
469MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
470
471static int pm8xxx_rtc_probe(struct platform_device *pdev)
472{
473 int rc;
474 struct pm8xxx_rtc *rtc_dd;
475 const struct of_device_id *match;
476
477 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
478 if (!match)
479 return -ENXIO;
480
481 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
482 if (rtc_dd == NULL)
483 return -ENOMEM;
484
485 /* Initialise spinlock to protect RTC control register */
486 spin_lock_init(&rtc_dd->ctrl_reg_lock);
487
488 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
489 if (!rtc_dd->regmap) {
490 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
491 return -ENXIO;
492 }
493
494 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
495 if (rtc_dd->rtc_alarm_irq < 0)
496 return -ENXIO;
497
498 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
499 "allow-set-time");
500
501 rtc_dd->regs = match->data;
502 rtc_dd->rtc_dev = &pdev->dev;
503
504 rc = pm8xxx_rtc_enable(rtc_dd);
505 if (rc)
506 return rc;
507
508 platform_set_drvdata(pdev, rtc_dd);
509
510 device_init_wakeup(&pdev->dev, 1);
511
512 /* Register the RTC device */
513 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
514 if (IS_ERR(rtc_dd->rtc))
515 return PTR_ERR(rtc_dd->rtc);
516
517 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
518 rtc_dd->rtc->range_max = U32_MAX;
519
520 /* Request the alarm IRQ */
521 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
522 pm8xxx_alarm_trigger,
523 IRQF_TRIGGER_RISING,
524 "pm8xxx_rtc_alarm", rtc_dd);
525 if (rc < 0) {
526 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
527 return rc;
528 }
529
530 rc = devm_rtc_register_device(rtc_dd->rtc);
531 if (rc)
532 return rc;
533
534 rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->rtc_alarm_irq);
535 if (rc)
536 return rc;
537
538 return 0;
539}
540
541static int pm8xxx_remove(struct platform_device *pdev)
542{
543 dev_pm_clear_wake_irq(&pdev->dev);
544 return 0;
545}
546
547static struct platform_driver pm8xxx_rtc_driver = {
548 .probe = pm8xxx_rtc_probe,
549 .remove = pm8xxx_remove,
550 .driver = {
551 .name = "rtc-pm8xxx",
552 .of_match_table = pm8xxx_id_table,
553 },
554};
555
556module_platform_driver(pm8xxx_rtc_driver);
557
558MODULE_ALIAS("platform:rtc-pm8xxx");
559MODULE_DESCRIPTION("PMIC8xxx RTC driver");
560MODULE_LICENSE("GPL v2");
561MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4#include <linux/of.h>
5#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/rtc.h>
8#include <linux/platform_device.h>
9#include <linux/pm.h>
10#include <linux/regmap.h>
11#include <linux/slab.h>
12#include <linux/spinlock.h>
13
14/* RTC Register offsets from RTC CTRL REG */
15#define PM8XXX_ALARM_CTRL_OFFSET 0x01
16#define PM8XXX_RTC_WRITE_OFFSET 0x02
17#define PM8XXX_RTC_READ_OFFSET 0x06
18#define PM8XXX_ALARM_RW_OFFSET 0x0A
19
20/* RTC_CTRL register bit fields */
21#define PM8xxx_RTC_ENABLE BIT(7)
22#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
23
24#define NUM_8_BIT_RTC_REGS 0x4
25
26/**
27 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
28 * @ctrl: base address of control register
29 * @write: base address of write register
30 * @read: base address of read register
31 * @alarm_ctrl: base address of alarm control register
32 * @alarm_ctrl2: base address of alarm control2 register
33 * @alarm_rw: base address of alarm read-write register
34 * @alarm_en: alarm enable mask
35 */
36struct pm8xxx_rtc_regs {
37 unsigned int ctrl;
38 unsigned int write;
39 unsigned int read;
40 unsigned int alarm_ctrl;
41 unsigned int alarm_ctrl2;
42 unsigned int alarm_rw;
43 unsigned int alarm_en;
44};
45
46/**
47 * struct pm8xxx_rtc - rtc driver internal structure
48 * @rtc: rtc device for this driver.
49 * @regmap: regmap used to access RTC registers
50 * @allow_set_time: indicates whether writing to the RTC is allowed
51 * @rtc_alarm_irq: rtc alarm irq number.
52 * @ctrl_reg: rtc control register.
53 * @rtc_dev: device structure.
54 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
55 */
56struct pm8xxx_rtc {
57 struct rtc_device *rtc;
58 struct regmap *regmap;
59 bool allow_set_time;
60 int rtc_alarm_irq;
61 const struct pm8xxx_rtc_regs *regs;
62 struct device *rtc_dev;
63 spinlock_t ctrl_reg_lock;
64};
65
66/*
67 * Steps to write the RTC registers.
68 * 1. Disable alarm if enabled.
69 * 2. Disable rtc if enabled.
70 * 3. Write 0x00 to LSB.
71 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
72 * 5. Enable rtc if disabled in step 2.
73 * 6. Enable alarm if disabled in step 1.
74 */
75static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
76{
77 int rc, i;
78 unsigned long secs, irq_flags;
79 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
80 unsigned int ctrl_reg, rtc_ctrl_reg;
81 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
82 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
83
84 if (!rtc_dd->allow_set_time)
85 return -EACCES;
86
87 rtc_tm_to_time(tm, &secs);
88
89 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
90
91 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
92 value[i] = secs & 0xFF;
93 secs >>= 8;
94 }
95
96 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
97
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
99 if (rc)
100 goto rtc_rw_fail;
101
102 if (ctrl_reg & regs->alarm_en) {
103 alarm_enabled = 1;
104 ctrl_reg &= ~regs->alarm_en;
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
106 if (rc) {
107 dev_err(dev, "Write to RTC Alarm control register failed\n");
108 goto rtc_rw_fail;
109 }
110 }
111
112 /* Disable RTC H/w before writing on RTC register */
113 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
114 if (rc)
115 goto rtc_rw_fail;
116
117 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
118 rtc_disabled = 1;
119 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
120 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
121 if (rc) {
122 dev_err(dev, "Write to RTC control register failed\n");
123 goto rtc_rw_fail;
124 }
125 }
126
127 /* Write 0 to Byte[0] */
128 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
129 if (rc) {
130 dev_err(dev, "Write to RTC write data register failed\n");
131 goto rtc_rw_fail;
132 }
133
134 /* Write Byte[1], Byte[2], Byte[3] */
135 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
136 &value[1], sizeof(value) - 1);
137 if (rc) {
138 dev_err(dev, "Write to RTC write data register failed\n");
139 goto rtc_rw_fail;
140 }
141
142 /* Write Byte[0] */
143 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
144 if (rc) {
145 dev_err(dev, "Write to RTC write data register failed\n");
146 goto rtc_rw_fail;
147 }
148
149 /* Enable RTC H/w after writing on RTC register */
150 if (rtc_disabled) {
151 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
152 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
153 if (rc) {
154 dev_err(dev, "Write to RTC control register failed\n");
155 goto rtc_rw_fail;
156 }
157 }
158
159 if (alarm_enabled) {
160 ctrl_reg |= regs->alarm_en;
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
162 if (rc) {
163 dev_err(dev, "Write to RTC Alarm control register failed\n");
164 goto rtc_rw_fail;
165 }
166 }
167
168rtc_rw_fail:
169 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
170
171 return rc;
172}
173
174static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
175{
176 int rc;
177 u8 value[NUM_8_BIT_RTC_REGS];
178 unsigned long secs;
179 unsigned int reg;
180 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
181 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
182
183 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
184 if (rc) {
185 dev_err(dev, "RTC read data register failed\n");
186 return rc;
187 }
188
189 /*
190 * Read the LSB again and check if there has been a carry over.
191 * If there is, redo the read operation.
192 */
193 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
194 if (rc < 0) {
195 dev_err(dev, "RTC read data register failed\n");
196 return rc;
197 }
198
199 if (unlikely(reg < value[0])) {
200 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
201 value, sizeof(value));
202 if (rc) {
203 dev_err(dev, "RTC read data register failed\n");
204 return rc;
205 }
206 }
207
208 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
209 ((unsigned long)value[3] << 24);
210
211 rtc_time_to_tm(secs, tm);
212
213 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
214
215 return 0;
216}
217
218static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
219{
220 int rc, i;
221 u8 value[NUM_8_BIT_RTC_REGS];
222 unsigned int ctrl_reg;
223 unsigned long secs, irq_flags;
224 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
225 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
226
227 rtc_tm_to_time(&alarm->time, &secs);
228
229 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
230 value[i] = secs & 0xFF;
231 secs >>= 8;
232 }
233
234 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
235
236 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
237 sizeof(value));
238 if (rc) {
239 dev_err(dev, "Write to RTC ALARM register failed\n");
240 goto rtc_rw_fail;
241 }
242
243 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
244 if (rc)
245 goto rtc_rw_fail;
246
247 if (alarm->enabled)
248 ctrl_reg |= regs->alarm_en;
249 else
250 ctrl_reg &= ~regs->alarm_en;
251
252 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
253 if (rc) {
254 dev_err(dev, "Write to RTC alarm control register failed\n");
255 goto rtc_rw_fail;
256 }
257
258 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
259 &alarm->time, &alarm->time);
260rtc_rw_fail:
261 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
262 return rc;
263}
264
265static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
266{
267 int rc;
268 u8 value[NUM_8_BIT_RTC_REGS];
269 unsigned long secs;
270 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
271 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
272
273 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
274 sizeof(value));
275 if (rc) {
276 dev_err(dev, "RTC alarm time read failed\n");
277 return rc;
278 }
279
280 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
281 ((unsigned long)value[3] << 24);
282
283 rtc_time_to_tm(secs, &alarm->time);
284
285 rc = rtc_valid_tm(&alarm->time);
286 if (rc < 0) {
287 dev_err(dev, "Invalid alarm time read from RTC\n");
288 return rc;
289 }
290
291 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
292 &alarm->time, &alarm->time);
293
294 return 0;
295}
296
297static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
298{
299 int rc;
300 unsigned long irq_flags;
301 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
302 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
303 unsigned int ctrl_reg;
304
305 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
306
307 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
308 if (rc)
309 goto rtc_rw_fail;
310
311 if (enable)
312 ctrl_reg |= regs->alarm_en;
313 else
314 ctrl_reg &= ~regs->alarm_en;
315
316 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
317 if (rc) {
318 dev_err(dev, "Write to RTC control register failed\n");
319 goto rtc_rw_fail;
320 }
321
322rtc_rw_fail:
323 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
324 return rc;
325}
326
327static const struct rtc_class_ops pm8xxx_rtc_ops = {
328 .read_time = pm8xxx_rtc_read_time,
329 .set_time = pm8xxx_rtc_set_time,
330 .set_alarm = pm8xxx_rtc_set_alarm,
331 .read_alarm = pm8xxx_rtc_read_alarm,
332 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
333};
334
335static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
336{
337 struct pm8xxx_rtc *rtc_dd = dev_id;
338 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
339 unsigned int ctrl_reg;
340 int rc;
341 unsigned long irq_flags;
342
343 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
344
345 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
346
347 /* Clear the alarm enable bit */
348 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
349 if (rc) {
350 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
351 goto rtc_alarm_handled;
352 }
353
354 ctrl_reg &= ~regs->alarm_en;
355
356 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
357 if (rc) {
358 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
359 dev_err(rtc_dd->rtc_dev,
360 "Write to alarm control register failed\n");
361 goto rtc_alarm_handled;
362 }
363
364 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
365
366 /* Clear RTC alarm register */
367 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
368 if (rc) {
369 dev_err(rtc_dd->rtc_dev,
370 "RTC Alarm control2 register read failed\n");
371 goto rtc_alarm_handled;
372 }
373
374 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
375 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
376 if (rc)
377 dev_err(rtc_dd->rtc_dev,
378 "Write to RTC Alarm control2 register failed\n");
379
380rtc_alarm_handled:
381 return IRQ_HANDLED;
382}
383
384static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
385{
386 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
387 unsigned int ctrl_reg;
388 int rc;
389
390 /* Check if the RTC is on, else turn it on */
391 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
392 if (rc)
393 return rc;
394
395 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
396 ctrl_reg |= PM8xxx_RTC_ENABLE;
397 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
398 if (rc)
399 return rc;
400 }
401
402 return 0;
403}
404
405static const struct pm8xxx_rtc_regs pm8921_regs = {
406 .ctrl = 0x11d,
407 .write = 0x11f,
408 .read = 0x123,
409 .alarm_rw = 0x127,
410 .alarm_ctrl = 0x11d,
411 .alarm_ctrl2 = 0x11e,
412 .alarm_en = BIT(1),
413};
414
415static const struct pm8xxx_rtc_regs pm8058_regs = {
416 .ctrl = 0x1e8,
417 .write = 0x1ea,
418 .read = 0x1ee,
419 .alarm_rw = 0x1f2,
420 .alarm_ctrl = 0x1e8,
421 .alarm_ctrl2 = 0x1e9,
422 .alarm_en = BIT(1),
423};
424
425static const struct pm8xxx_rtc_regs pm8941_regs = {
426 .ctrl = 0x6046,
427 .write = 0x6040,
428 .read = 0x6048,
429 .alarm_rw = 0x6140,
430 .alarm_ctrl = 0x6146,
431 .alarm_ctrl2 = 0x6148,
432 .alarm_en = BIT(7),
433};
434
435/*
436 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
437 */
438static const struct of_device_id pm8xxx_id_table[] = {
439 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
440 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
441 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
442 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
443 { },
444};
445MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
446
447static int pm8xxx_rtc_probe(struct platform_device *pdev)
448{
449 int rc;
450 struct pm8xxx_rtc *rtc_dd;
451 const struct of_device_id *match;
452
453 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
454 if (!match)
455 return -ENXIO;
456
457 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
458 if (rtc_dd == NULL)
459 return -ENOMEM;
460
461 /* Initialise spinlock to protect RTC control register */
462 spin_lock_init(&rtc_dd->ctrl_reg_lock);
463
464 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
465 if (!rtc_dd->regmap) {
466 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
467 return -ENXIO;
468 }
469
470 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
471 if (rtc_dd->rtc_alarm_irq < 0)
472 return -ENXIO;
473
474 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
475 "allow-set-time");
476
477 rtc_dd->regs = match->data;
478 rtc_dd->rtc_dev = &pdev->dev;
479
480 rc = pm8xxx_rtc_enable(rtc_dd);
481 if (rc)
482 return rc;
483
484 platform_set_drvdata(pdev, rtc_dd);
485
486 device_init_wakeup(&pdev->dev, 1);
487
488 /* Register the RTC device */
489 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
490 &pm8xxx_rtc_ops, THIS_MODULE);
491 if (IS_ERR(rtc_dd->rtc)) {
492 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
493 __func__, PTR_ERR(rtc_dd->rtc));
494 return PTR_ERR(rtc_dd->rtc);
495 }
496
497 /* Request the alarm IRQ */
498 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
499 pm8xxx_alarm_trigger,
500 IRQF_TRIGGER_RISING,
501 "pm8xxx_rtc_alarm", rtc_dd);
502 if (rc < 0) {
503 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
504 return rc;
505 }
506
507 dev_dbg(&pdev->dev, "Probe success !!\n");
508
509 return 0;
510}
511
512#ifdef CONFIG_PM_SLEEP
513static int pm8xxx_rtc_resume(struct device *dev)
514{
515 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
516
517 if (device_may_wakeup(dev))
518 disable_irq_wake(rtc_dd->rtc_alarm_irq);
519
520 return 0;
521}
522
523static int pm8xxx_rtc_suspend(struct device *dev)
524{
525 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
526
527 if (device_may_wakeup(dev))
528 enable_irq_wake(rtc_dd->rtc_alarm_irq);
529
530 return 0;
531}
532#endif
533
534static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
535 pm8xxx_rtc_suspend,
536 pm8xxx_rtc_resume);
537
538static struct platform_driver pm8xxx_rtc_driver = {
539 .probe = pm8xxx_rtc_probe,
540 .driver = {
541 .name = "rtc-pm8xxx",
542 .pm = &pm8xxx_rtc_pm_ops,
543 .of_match_table = pm8xxx_id_table,
544 },
545};
546
547module_platform_driver(pm8xxx_rtc_driver);
548
549MODULE_ALIAS("platform:rtc-pm8xxx");
550MODULE_DESCRIPTION("PMIC8xxx RTC driver");
551MODULE_LICENSE("GPL v2");
552MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");