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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek Pulse Width Modulator driver
4 *
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 *
8 */
9
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/types.h>
22
23/* PWM registers and bits definitions */
24#define PWMCON 0x00
25#define PWMHDUR 0x04
26#define PWMLDUR 0x08
27#define PWMGDUR 0x0c
28#define PWMWAVENUM 0x28
29#define PWMDWIDTH 0x2c
30#define PWM45DWIDTH_FIXUP 0x30
31#define PWMTHRES 0x30
32#define PWM45THRES_FIXUP 0x34
33#define PWM_CK_26M_SEL 0x210
34
35#define PWM_CLK_DIV_MAX 7
36
37struct pwm_mediatek_of_data {
38 unsigned int num_pwms;
39 bool pwm45_fixup;
40 bool has_ck_26m_sel;
41};
42
43/**
44 * struct pwm_mediatek_chip - struct representing PWM chip
45 * @chip: linux PWM chip representation
46 * @regs: base address of PWM chip
47 * @clk_top: the top clock generator
48 * @clk_main: the clock used by PWM core
49 * @clk_pwms: the clock used by each PWM channel
50 * @clk_freq: the fix clock frequency of legacy MIPS SoC
51 * @soc: pointer to chip's platform data
52 */
53struct pwm_mediatek_chip {
54 struct pwm_chip chip;
55 void __iomem *regs;
56 struct clk *clk_top;
57 struct clk *clk_main;
58 struct clk **clk_pwms;
59 const struct pwm_mediatek_of_data *soc;
60};
61
62static const unsigned int pwm_mediatek_reg_offset[] = {
63 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
64};
65
66static inline struct pwm_mediatek_chip *
67to_pwm_mediatek_chip(struct pwm_chip *chip)
68{
69 return container_of(chip, struct pwm_mediatek_chip, chip);
70}
71
72static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
73 struct pwm_device *pwm)
74{
75 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
76 int ret;
77
78 ret = clk_prepare_enable(pc->clk_top);
79 if (ret < 0)
80 return ret;
81
82 ret = clk_prepare_enable(pc->clk_main);
83 if (ret < 0)
84 goto disable_clk_top;
85
86 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
87 if (ret < 0)
88 goto disable_clk_main;
89
90 return 0;
91
92disable_clk_main:
93 clk_disable_unprepare(pc->clk_main);
94disable_clk_top:
95 clk_disable_unprepare(pc->clk_top);
96
97 return ret;
98}
99
100static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
101 struct pwm_device *pwm)
102{
103 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
104
105 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
106 clk_disable_unprepare(pc->clk_main);
107 clk_disable_unprepare(pc->clk_top);
108}
109
110static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
111 unsigned int num, unsigned int offset,
112 u32 value)
113{
114 writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
115}
116
117static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
118 int duty_ns, int period_ns)
119{
120 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
121 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
122 reg_thres = PWMTHRES;
123 u64 resolution;
124 int ret;
125
126 ret = pwm_mediatek_clk_enable(chip, pwm);
127
128 if (ret < 0)
129 return ret;
130
131 /* Make sure we use the bus clock and not the 26MHz clock */
132 if (pc->soc->has_ck_26m_sel)
133 writel(0, pc->regs + PWM_CK_26M_SEL);
134
135 /* Using resolution in picosecond gets accuracy higher */
136 resolution = (u64)NSEC_PER_SEC * 1000;
137 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
138
139 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
140 while (cnt_period > 8191) {
141 resolution *= 2;
142 clkdiv++;
143 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
144 resolution);
145 }
146
147 if (clkdiv > PWM_CLK_DIV_MAX) {
148 pwm_mediatek_clk_disable(chip, pwm);
149 dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
150 return -EINVAL;
151 }
152
153 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
154 /*
155 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
156 * from the other PWMs on MT7623.
157 */
158 reg_width = PWM45DWIDTH_FIXUP;
159 reg_thres = PWM45THRES_FIXUP;
160 }
161
162 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
163 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
164 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
165 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
166
167 pwm_mediatek_clk_disable(chip, pwm);
168
169 return 0;
170}
171
172static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
173{
174 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
175 u32 value;
176 int ret;
177
178 ret = pwm_mediatek_clk_enable(chip, pwm);
179 if (ret < 0)
180 return ret;
181
182 value = readl(pc->regs);
183 value |= BIT(pwm->hwpwm);
184 writel(value, pc->regs);
185
186 return 0;
187}
188
189static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
190{
191 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
192 u32 value;
193
194 value = readl(pc->regs);
195 value &= ~BIT(pwm->hwpwm);
196 writel(value, pc->regs);
197
198 pwm_mediatek_clk_disable(chip, pwm);
199}
200
201static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm,
202 const struct pwm_state *state)
203{
204 int err;
205
206 if (state->polarity != PWM_POLARITY_NORMAL)
207 return -EINVAL;
208
209 if (!state->enabled) {
210 if (pwm->state.enabled)
211 pwm_mediatek_disable(chip, pwm);
212
213 return 0;
214 }
215
216 err = pwm_mediatek_config(pwm->chip, pwm, state->duty_cycle, state->period);
217 if (err)
218 return err;
219
220 if (!pwm->state.enabled)
221 err = pwm_mediatek_enable(chip, pwm);
222
223 return err;
224}
225
226static const struct pwm_ops pwm_mediatek_ops = {
227 .apply = pwm_mediatek_apply,
228 .owner = THIS_MODULE,
229};
230
231static int pwm_mediatek_probe(struct platform_device *pdev)
232{
233 struct pwm_mediatek_chip *pc;
234 unsigned int i;
235 int ret;
236
237 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
238 if (!pc)
239 return -ENOMEM;
240
241 pc->soc = of_device_get_match_data(&pdev->dev);
242
243 pc->regs = devm_platform_ioremap_resource(pdev, 0);
244 if (IS_ERR(pc->regs))
245 return PTR_ERR(pc->regs);
246
247 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
248 sizeof(*pc->clk_pwms), GFP_KERNEL);
249 if (!pc->clk_pwms)
250 return -ENOMEM;
251
252 pc->clk_top = devm_clk_get(&pdev->dev, "top");
253 if (IS_ERR(pc->clk_top))
254 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
255 "Failed to get top clock\n");
256
257 pc->clk_main = devm_clk_get(&pdev->dev, "main");
258 if (IS_ERR(pc->clk_main))
259 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
260 "Failed to get main clock\n");
261
262 for (i = 0; i < pc->soc->num_pwms; i++) {
263 char name[8];
264
265 snprintf(name, sizeof(name), "pwm%d", i + 1);
266
267 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
268 if (IS_ERR(pc->clk_pwms[i]))
269 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
270 "Failed to get %s clock\n", name);
271 }
272
273 pc->chip.dev = &pdev->dev;
274 pc->chip.ops = &pwm_mediatek_ops;
275 pc->chip.npwm = pc->soc->num_pwms;
276
277 ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
278 if (ret < 0)
279 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
280
281 return 0;
282}
283
284static const struct pwm_mediatek_of_data mt2712_pwm_data = {
285 .num_pwms = 8,
286 .pwm45_fixup = false,
287 .has_ck_26m_sel = false,
288};
289
290static const struct pwm_mediatek_of_data mt6795_pwm_data = {
291 .num_pwms = 7,
292 .pwm45_fixup = false,
293 .has_ck_26m_sel = false,
294};
295
296static const struct pwm_mediatek_of_data mt7622_pwm_data = {
297 .num_pwms = 6,
298 .pwm45_fixup = false,
299 .has_ck_26m_sel = true,
300};
301
302static const struct pwm_mediatek_of_data mt7623_pwm_data = {
303 .num_pwms = 5,
304 .pwm45_fixup = true,
305 .has_ck_26m_sel = false,
306};
307
308static const struct pwm_mediatek_of_data mt7628_pwm_data = {
309 .num_pwms = 4,
310 .pwm45_fixup = true,
311 .has_ck_26m_sel = false,
312};
313
314static const struct pwm_mediatek_of_data mt7629_pwm_data = {
315 .num_pwms = 1,
316 .pwm45_fixup = false,
317 .has_ck_26m_sel = false,
318};
319
320static const struct pwm_mediatek_of_data mt8183_pwm_data = {
321 .num_pwms = 4,
322 .pwm45_fixup = false,
323 .has_ck_26m_sel = true,
324};
325
326static const struct pwm_mediatek_of_data mt8365_pwm_data = {
327 .num_pwms = 3,
328 .pwm45_fixup = false,
329 .has_ck_26m_sel = true,
330};
331
332static const struct pwm_mediatek_of_data mt7986_pwm_data = {
333 .num_pwms = 2,
334 .pwm45_fixup = false,
335 .has_ck_26m_sel = true,
336};
337
338static const struct pwm_mediatek_of_data mt8516_pwm_data = {
339 .num_pwms = 5,
340 .pwm45_fixup = false,
341 .has_ck_26m_sel = true,
342};
343
344static const struct of_device_id pwm_mediatek_of_match[] = {
345 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
346 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data },
347 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
348 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
349 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
350 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
351 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
352 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
353 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
354 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
355 { },
356};
357MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
358
359static struct platform_driver pwm_mediatek_driver = {
360 .driver = {
361 .name = "pwm-mediatek",
362 .of_match_table = pwm_mediatek_of_match,
363 },
364 .probe = pwm_mediatek_probe,
365};
366module_platform_driver(pwm_mediatek_driver);
367
368MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
369MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek Pulse Width Modulator driver
4 *
5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
7 *
8 */
9
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/types.h>
22
23/* PWM registers and bits definitions */
24#define PWMCON 0x00
25#define PWMHDUR 0x04
26#define PWMLDUR 0x08
27#define PWMGDUR 0x0c
28#define PWMWAVENUM 0x28
29#define PWMDWIDTH 0x2c
30#define PWM45DWIDTH_FIXUP 0x30
31#define PWMTHRES 0x30
32#define PWM45THRES_FIXUP 0x34
33
34#define PWM_CLK_DIV_MAX 7
35
36struct pwm_mediatek_of_data {
37 unsigned int num_pwms;
38 bool pwm45_fixup;
39};
40
41/**
42 * struct pwm_mediatek_chip - struct representing PWM chip
43 * @chip: linux PWM chip representation
44 * @regs: base address of PWM chip
45 * @clk_top: the top clock generator
46 * @clk_main: the clock used by PWM core
47 * @clk_pwms: the clock used by each PWM channel
48 * @clk_freq: the fix clock frequency of legacy MIPS SoC
49 */
50struct pwm_mediatek_chip {
51 struct pwm_chip chip;
52 void __iomem *regs;
53 struct clk *clk_top;
54 struct clk *clk_main;
55 struct clk **clk_pwms;
56 const struct pwm_mediatek_of_data *soc;
57};
58
59static const unsigned int pwm_mediatek_reg_offset[] = {
60 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
61};
62
63static inline struct pwm_mediatek_chip *
64to_pwm_mediatek_chip(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_mediatek_chip, chip);
67}
68
69static int pwm_mediatek_clk_enable(struct pwm_chip *chip,
70 struct pwm_device *pwm)
71{
72 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
73 int ret;
74
75 ret = clk_prepare_enable(pc->clk_top);
76 if (ret < 0)
77 return ret;
78
79 ret = clk_prepare_enable(pc->clk_main);
80 if (ret < 0)
81 goto disable_clk_top;
82
83 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
84 if (ret < 0)
85 goto disable_clk_main;
86
87 return 0;
88
89disable_clk_main:
90 clk_disable_unprepare(pc->clk_main);
91disable_clk_top:
92 clk_disable_unprepare(pc->clk_top);
93
94 return ret;
95}
96
97static void pwm_mediatek_clk_disable(struct pwm_chip *chip,
98 struct pwm_device *pwm)
99{
100 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
101
102 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
103 clk_disable_unprepare(pc->clk_main);
104 clk_disable_unprepare(pc->clk_top);
105}
106
107static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip,
108 unsigned int num, unsigned int offset)
109{
110 return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset);
111}
112
113static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
114 unsigned int num, unsigned int offset,
115 u32 value)
116{
117 writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
118}
119
120static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
121 int duty_ns, int period_ns)
122{
123 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
124 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
125 reg_thres = PWMTHRES;
126 u64 resolution;
127 int ret;
128
129 ret = pwm_mediatek_clk_enable(chip, pwm);
130
131 if (ret < 0)
132 return ret;
133
134 /* Using resolution in picosecond gets accuracy higher */
135 resolution = (u64)NSEC_PER_SEC * 1000;
136 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
137
138 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
139 while (cnt_period > 8191) {
140 resolution *= 2;
141 clkdiv++;
142 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
143 resolution);
144 }
145
146 if (clkdiv > PWM_CLK_DIV_MAX) {
147 pwm_mediatek_clk_disable(chip, pwm);
148 dev_err(chip->dev, "period %d not supported\n", period_ns);
149 return -EINVAL;
150 }
151
152 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
153 /*
154 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
155 * from the other PWMs on MT7623.
156 */
157 reg_width = PWM45DWIDTH_FIXUP;
158 reg_thres = PWM45THRES_FIXUP;
159 }
160
161 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
162 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
163 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
164 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
165
166 pwm_mediatek_clk_disable(chip, pwm);
167
168 return 0;
169}
170
171static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)
172{
173 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
174 u32 value;
175 int ret;
176
177 ret = pwm_mediatek_clk_enable(chip, pwm);
178 if (ret < 0)
179 return ret;
180
181 value = readl(pc->regs);
182 value |= BIT(pwm->hwpwm);
183 writel(value, pc->regs);
184
185 return 0;
186}
187
188static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm)
189{
190 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
191 u32 value;
192
193 value = readl(pc->regs);
194 value &= ~BIT(pwm->hwpwm);
195 writel(value, pc->regs);
196
197 pwm_mediatek_clk_disable(chip, pwm);
198}
199
200static const struct pwm_ops pwm_mediatek_ops = {
201 .config = pwm_mediatek_config,
202 .enable = pwm_mediatek_enable,
203 .disable = pwm_mediatek_disable,
204 .owner = THIS_MODULE,
205};
206
207static int pwm_mediatek_probe(struct platform_device *pdev)
208{
209 struct pwm_mediatek_chip *pc;
210 struct resource *res;
211 unsigned int i;
212 int ret;
213
214 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
215 if (!pc)
216 return -ENOMEM;
217
218 pc->soc = of_device_get_match_data(&pdev->dev);
219
220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
221 pc->regs = devm_ioremap_resource(&pdev->dev, res);
222 if (IS_ERR(pc->regs))
223 return PTR_ERR(pc->regs);
224
225 pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
226 sizeof(*pc->clk_pwms), GFP_KERNEL);
227 if (!pc->clk_pwms)
228 return -ENOMEM;
229
230 pc->clk_top = devm_clk_get(&pdev->dev, "top");
231 if (IS_ERR(pc->clk_top)) {
232 dev_err(&pdev->dev, "clock: top fail: %ld\n",
233 PTR_ERR(pc->clk_top));
234 return PTR_ERR(pc->clk_top);
235 }
236
237 pc->clk_main = devm_clk_get(&pdev->dev, "main");
238 if (IS_ERR(pc->clk_main)) {
239 dev_err(&pdev->dev, "clock: main fail: %ld\n",
240 PTR_ERR(pc->clk_main));
241 return PTR_ERR(pc->clk_main);
242 }
243
244 for (i = 0; i < pc->soc->num_pwms; i++) {
245 char name[8];
246
247 snprintf(name, sizeof(name), "pwm%d", i + 1);
248
249 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
250 if (IS_ERR(pc->clk_pwms[i])) {
251 dev_err(&pdev->dev, "clock: %s fail: %ld\n",
252 name, PTR_ERR(pc->clk_pwms[i]));
253 return PTR_ERR(pc->clk_pwms[i]);
254 }
255 }
256
257 platform_set_drvdata(pdev, pc);
258
259 pc->chip.dev = &pdev->dev;
260 pc->chip.ops = &pwm_mediatek_ops;
261 pc->chip.base = -1;
262 pc->chip.npwm = pc->soc->num_pwms;
263
264 ret = pwmchip_add(&pc->chip);
265 if (ret < 0) {
266 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
267 return ret;
268 }
269
270 return 0;
271}
272
273static int pwm_mediatek_remove(struct platform_device *pdev)
274{
275 struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev);
276
277 return pwmchip_remove(&pc->chip);
278}
279
280static const struct pwm_mediatek_of_data mt2712_pwm_data = {
281 .num_pwms = 8,
282 .pwm45_fixup = false,
283};
284
285static const struct pwm_mediatek_of_data mt7622_pwm_data = {
286 .num_pwms = 6,
287 .pwm45_fixup = false,
288};
289
290static const struct pwm_mediatek_of_data mt7623_pwm_data = {
291 .num_pwms = 5,
292 .pwm45_fixup = true,
293};
294
295static const struct pwm_mediatek_of_data mt7628_pwm_data = {
296 .num_pwms = 4,
297 .pwm45_fixup = true,
298};
299
300static const struct pwm_mediatek_of_data mt7629_pwm_data = {
301 .num_pwms = 1,
302 .pwm45_fixup = false,
303};
304
305static const struct pwm_mediatek_of_data mt8516_pwm_data = {
306 .num_pwms = 5,
307 .pwm45_fixup = false,
308};
309
310static const struct of_device_id pwm_mediatek_of_match[] = {
311 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
312 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
313 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
314 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
315 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
316 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
317 { },
318};
319MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match);
320
321static struct platform_driver pwm_mediatek_driver = {
322 .driver = {
323 .name = "pwm-mediatek",
324 .of_match_table = pwm_mediatek_of_match,
325 },
326 .probe = pwm_mediatek_probe,
327 .remove = pwm_mediatek_remove,
328};
329module_platform_driver(pwm_mediatek_driver);
330
331MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
332MODULE_LICENSE("GPL v2");