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v6.2
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* drivers/net/ethernet/micrel/ks8851.h
  3 *
  4 * Copyright 2009 Simtec Electronics
  5 *      Ben Dooks <ben@simtec.co.uk>
  6 *
  7 * KS8851 register definitions
  8*/
  9
 10#ifndef __KS8851_H__
 11#define __KS8851_H__
 12
 13#include <linux/eeprom_93cx6.h>
 14
 15#define KS_CCR					0x08
 16#define CCR_LE					(1 << 10)   /* KSZ8851-16MLL */
 17#define CCR_EEPROM				(1 << 9)
 18#define CCR_SPI					(1 << 8)    /* KSZ8851SNL    */
 19#define CCR_8BIT				(1 << 7)    /* KSZ8851-16MLL */
 20#define CCR_16BIT				(1 << 6)    /* KSZ8851-16MLL */
 21#define CCR_32BIT				(1 << 5)    /* KSZ8851-16MLL */
 22#define CCR_SHARED				(1 << 4)    /* KSZ8851-16MLL */
 23#define CCR_48PIN				(1 << 1)    /* KSZ8851-16MLL */
 24#define CCR_32PIN				(1 << 0)    /* KSZ8851SNL    */
 25
 26/* MAC address registers */
 27#define KS_MAR(_m)				(0x14 - (_m))
 28#define KS_MARL					0x10
 29#define KS_MARM					0x12
 30#define KS_MARH					0x14
 31
 32#define KS_OBCR					0x20
 33#define OBCR_ODS_16mA				(1 << 6)
 34
 35#define KS_EEPCR				0x22
 36#define EEPCR_EESRWA				(1 << 5)
 37#define EEPCR_EESA				(1 << 4)
 38#define EEPCR_EESB				(1 << 3)
 39#define EEPCR_EEDO				(1 << 2)
 40#define EEPCR_EESCK				(1 << 1)
 41#define EEPCR_EECS				(1 << 0)
 42
 43#define KS_MBIR					0x24
 44#define MBIR_TXMBF				(1 << 12)
 45#define MBIR_TXMBFA				(1 << 11)
 46#define MBIR_RXMBF				(1 << 4)
 47#define MBIR_RXMBFA				(1 << 3)
 48
 49#define KS_GRR					0x26
 50#define GRR_QMU					(1 << 1)
 51#define GRR_GSR					(1 << 0)
 52
 53#define KS_WFCR					0x2A
 54#define WFCR_MPRXE				(1 << 7)
 55#define WFCR_WF3E				(1 << 3)
 56#define WFCR_WF2E				(1 << 2)
 57#define WFCR_WF1E				(1 << 1)
 58#define WFCR_WF0E				(1 << 0)
 59
 60#define KS_WF0CRC0				0x30
 61#define KS_WF0CRC1				0x32
 62#define KS_WF0BM0				0x34
 63#define KS_WF0BM1				0x36
 64#define KS_WF0BM2				0x38
 65#define KS_WF0BM3				0x3A
 66
 67#define KS_WF1CRC0				0x40
 68#define KS_WF1CRC1				0x42
 69#define KS_WF1BM0				0x44
 70#define KS_WF1BM1				0x46
 71#define KS_WF1BM2				0x48
 72#define KS_WF1BM3				0x4A
 73
 74#define KS_WF2CRC0				0x50
 75#define KS_WF2CRC1				0x52
 76#define KS_WF2BM0				0x54
 77#define KS_WF2BM1				0x56
 78#define KS_WF2BM2				0x58
 79#define KS_WF2BM3				0x5A
 80
 81#define KS_WF3CRC0				0x60
 82#define KS_WF3CRC1				0x62
 83#define KS_WF3BM0				0x64
 84#define KS_WF3BM1				0x66
 85#define KS_WF3BM2				0x68
 86#define KS_WF3BM3				0x6A
 87
 88#define KS_TXCR					0x70
 89#define TXCR_TCGICMP				(1 << 8)
 90#define TXCR_TCGUDP				(1 << 7)
 91#define TXCR_TCGTCP				(1 << 6)
 92#define TXCR_TCGIP				(1 << 5)
 93#define TXCR_FTXQ				(1 << 4)
 94#define TXCR_TXFCE				(1 << 3)
 95#define TXCR_TXPE				(1 << 2)
 96#define TXCR_TXCRC				(1 << 1)
 97#define TXCR_TXE				(1 << 0)
 98
 99#define KS_TXSR					0x72
100#define TXSR_TXLC				(1 << 13)
101#define TXSR_TXMC				(1 << 12)
102#define TXSR_TXFID_MASK				(0x3f << 0)
103#define TXSR_TXFID_SHIFT			(0)
104#define TXSR_TXFID_GET(_v)			(((_v) >> 0) & 0x3f)
105
106#define KS_RXCR1				0x74
107#define RXCR1_FRXQ				(1 << 15)
108#define RXCR1_RXUDPFCC				(1 << 14)
109#define RXCR1_RXTCPFCC				(1 << 13)
110#define RXCR1_RXIPFCC				(1 << 12)
111#define RXCR1_RXPAFMA				(1 << 11)
112#define RXCR1_RXFCE				(1 << 10)
113#define RXCR1_RXEFE				(1 << 9)
114#define RXCR1_RXMAFMA				(1 << 8)
115#define RXCR1_RXBE				(1 << 7)
116#define RXCR1_RXME				(1 << 6)
117#define RXCR1_RXUE				(1 << 5)
118#define RXCR1_RXAE				(1 << 4)
119#define RXCR1_RXINVF				(1 << 1)
120#define RXCR1_RXE				(1 << 0)
121
122#define KS_RXCR2				0x76
123#define RXCR2_SRDBL_MASK			(0x7 << 5)  /* KSZ8851SNL    */
124#define RXCR2_SRDBL_SHIFT			(5)	    /* KSZ8851SNL    */
125#define RXCR2_SRDBL_4B				(0x0 << 5)  /* KSZ8851SNL    */
126#define RXCR2_SRDBL_8B				(0x1 << 5)  /* KSZ8851SNL    */
127#define RXCR2_SRDBL_16B				(0x2 << 5)  /* KSZ8851SNL    */
128#define RXCR2_SRDBL_32B				(0x3 << 5)  /* KSZ8851SNL    */
129#define RXCR2_SRDBL_FRAME			(0x4 << 5)  /* KSZ8851SNL    */
130#define RXCR2_IUFFP				(1 << 4)
131#define RXCR2_RXIUFCEZ				(1 << 3)
132#define RXCR2_UDPLFE				(1 << 2)
133#define RXCR2_RXICMPFCC				(1 << 1)
134#define RXCR2_RXSAF				(1 << 0)
135
136#define KS_TXMIR				0x78
137
138#define KS_RXFHSR				0x7C
139#define RXFSHR_RXFV				(1 << 15)
140#define RXFSHR_RXICMPFCS			(1 << 13)
141#define RXFSHR_RXIPFCS				(1 << 12)
142#define RXFSHR_RXTCPFCS				(1 << 11)
143#define RXFSHR_RXUDPFCS				(1 << 10)
144#define RXFSHR_RXBF				(1 << 7)
145#define RXFSHR_RXMF				(1 << 6)
146#define RXFSHR_RXUF				(1 << 5)
147#define RXFSHR_RXMR				(1 << 4)
148#define RXFSHR_RXFT				(1 << 3)
149#define RXFSHR_RXFTL				(1 << 2)
150#define RXFSHR_RXRF				(1 << 1)
151#define RXFSHR_RXCE				(1 << 0)
152
153#define KS_RXFHBCR				0x7E
154#define RXFHBCR_CNT_MASK			(0xfff << 0)
155
156#define KS_TXQCR				0x80
157#define TXQCR_AETFE				(1 << 2)    /* KSZ8851SNL    */
158#define TXQCR_TXQMAM				(1 << 1)
159#define TXQCR_METFE				(1 << 0)
160
161#define KS_RXQCR				0x82
162#define RXQCR_RXDTTS				(1 << 12)
163#define RXQCR_RXDBCTS				(1 << 11)
164#define RXQCR_RXFCTS				(1 << 10)
165#define RXQCR_RXIPHTOE				(1 << 9)
166#define RXQCR_RXDTTE				(1 << 7)
167#define RXQCR_RXDBCTE				(1 << 6)
168#define RXQCR_RXFCTE				(1 << 5)
169#define RXQCR_ADRFE				(1 << 4)
170#define RXQCR_SDA				(1 << 3)
171#define RXQCR_RRXEF				(1 << 0)
172
173#define KS_TXFDPR				0x84
174#define TXFDPR_TXFPAI				(1 << 14)
175#define TXFDPR_TXFP_MASK			(0x7ff << 0)
176#define TXFDPR_TXFP_SHIFT			(0)
177
178#define KS_RXFDPR				0x86
179#define RXFDPR_RXFPAI				(1 << 14)
180#define RXFDPR_WST				(1 << 12)   /* KSZ8851-16MLL */
181#define RXFDPR_EMS				(1 << 11)   /* KSZ8851-16MLL */
182#define RXFDPR_RXFP_MASK			(0x7ff << 0)
183#define RXFDPR_RXFP_SHIFT			(0)
184
185#define KS_RXDTTR				0x8C
186#define KS_RXDBCTR				0x8E
187
188#define KS_IER					0x90
189#define KS_ISR					0x92
190#define IRQ_LCI					(1 << 15)
191#define IRQ_TXI					(1 << 14)
192#define IRQ_RXI					(1 << 13)
193#define IRQ_RXOI				(1 << 11)
194#define IRQ_TXPSI				(1 << 9)
195#define IRQ_RXPSI				(1 << 8)
196#define IRQ_TXSAI				(1 << 6)
197#define IRQ_RXWFDI				(1 << 5)
198#define IRQ_RXMPDI				(1 << 4)
199#define IRQ_LDI					(1 << 3)
200#define IRQ_EDI					(1 << 2)
201#define IRQ_SPIBEI				(1 << 1)    /* KSZ8851SNL    */
202#define IRQ_DEDI				(1 << 0)
203
204#define KS_RXFCTR				0x9C
205#define KS_RXFC					0x9D
206#define RXFCTR_RXFC_MASK			(0xff << 8)
207#define RXFCTR_RXFC_SHIFT			(8)
208#define RXFCTR_RXFC_GET(_v)			(((_v) >> 8) & 0xff)
209#define RXFCTR_RXFCT_MASK			(0xff << 0)
210#define RXFCTR_RXFCT_SHIFT			(0)
211
212#define KS_TXNTFSR				0x9E
213
214#define KS_MAHTR0				0xA0
215#define KS_MAHTR1				0xA2
216#define KS_MAHTR2				0xA4
217#define KS_MAHTR3				0xA6
218
219#define KS_FCLWR				0xB0
220#define KS_FCHWR				0xB2
221#define KS_FCOWR				0xB4
222
223#define KS_CIDER				0xC0
224#define CIDER_ID				0x8870
225#define CIDER_REV_MASK				(0x7 << 1)
226#define CIDER_REV_SHIFT				(1)
227#define CIDER_REV_GET(_v)			(((_v) >> 1) & 0x7)
228
229#define KS_CGCR					0xC6
230
231#define KS_IACR					0xC8
232#define IACR_RDEN				(1 << 12)
233#define IACR_TSEL_MASK				(0x3 << 10)
234#define IACR_TSEL_SHIFT				(10)
235#define IACR_TSEL_MIB				(0x3 << 10)
236#define IACR_ADDR_MASK				(0x1f << 0)
237#define IACR_ADDR_SHIFT				(0)
238
239#define KS_IADLR				0xD0
240#define KS_IAHDR				0xD2
241
242#define KS_PMECR				0xD4
243#define PMECR_PME_DELAY				(1 << 14)
244#define PMECR_PME_POL				(1 << 12)
245#define PMECR_WOL_WAKEUP			(1 << 11)
246#define PMECR_WOL_MAGICPKT			(1 << 10)
247#define PMECR_WOL_LINKUP			(1 << 9)
248#define PMECR_WOL_ENERGY			(1 << 8)
249#define PMECR_AUTO_WAKE_EN			(1 << 7)
250#define PMECR_WAKEUP_NORMAL			(1 << 6)
251#define PMECR_WKEVT_MASK			(0xf << 2)
252#define PMECR_WKEVT_SHIFT			(2)
253#define PMECR_WKEVT_GET(_v)			(((_v) >> 2) & 0xf)
254#define PMECR_WKEVT_ENERGY			(0x1 << 2)
255#define PMECR_WKEVT_LINK			(0x2 << 2)
256#define PMECR_WKEVT_MAGICPKT			(0x4 << 2)
257#define PMECR_WKEVT_FRAME			(0x8 << 2)
258#define PMECR_PM_MASK				(0x3 << 0)
259#define PMECR_PM_SHIFT				(0)
260#define PMECR_PM_NORMAL				(0x0 << 0)
261#define PMECR_PM_ENERGY				(0x1 << 0)
262#define PMECR_PM_SOFTDOWN			(0x2 << 0)
263#define PMECR_PM_POWERSAVE			(0x3 << 0)
264
265/* Standard MII PHY data */
266#define KS_P1MBCR				0xE4
267#define KS_P1MBSR				0xE6
268#define KS_PHY1ILR				0xE8
269#define KS_PHY1IHR				0xEA
270#define KS_P1ANAR				0xEC
271#define KS_P1ANLPR				0xEE
272
273#define KS_P1SCLMD				0xF4
274
275#define KS_P1CR					0xF6
276#define P1CR_LEDOFF				(1 << 15)
277#define P1CR_TXIDS				(1 << 14)
278#define P1CR_RESTARTAN				(1 << 13)
279#define P1CR_DISAUTOMDIX			(1 << 10)
280#define P1CR_FORCEMDIX				(1 << 9)
281#define P1CR_AUTONEGEN				(1 << 7)
282#define P1CR_FORCE100				(1 << 6)
283#define P1CR_FORCEFDX				(1 << 5)
284#define P1CR_ADV_FLOW				(1 << 4)
285#define P1CR_ADV_100BT_FDX			(1 << 3)
286#define P1CR_ADV_100BT_HDX			(1 << 2)
287#define P1CR_ADV_10BT_FDX			(1 << 1)
288#define P1CR_ADV_10BT_HDX			(1 << 0)
289
290#define KS_P1SR					0xF8
291#define P1SR_HP_MDIX				(1 << 15)
292#define P1SR_REV_POL				(1 << 13)
293#define P1SR_OP_100M				(1 << 10)
294#define P1SR_OP_FDX				(1 << 9)
295#define P1SR_OP_MDI				(1 << 7)
296#define P1SR_AN_DONE				(1 << 6)
297#define P1SR_LINK_GOOD				(1 << 5)
298#define P1SR_PNTR_FLOW				(1 << 4)
299#define P1SR_PNTR_100BT_FDX			(1 << 3)
300#define P1SR_PNTR_100BT_HDX			(1 << 2)
301#define P1SR_PNTR_10BT_FDX			(1 << 1)
302#define P1SR_PNTR_10BT_HDX			(1 << 0)
303
304/* TX Frame control */
305#define TXFR_TXIC				(1 << 15)
306#define TXFR_TXFID_MASK				(0x3f << 0)
307#define TXFR_TXFID_SHIFT			(0)
308
309/**
310 * struct ks8851_rxctrl - KS8851 driver rx control
311 * @mchash: Multicast hash-table data.
312 * @rxcr1: KS_RXCR1 register setting
313 * @rxcr2: KS_RXCR2 register setting
314 *
315 * Representation of the settings needs to control the receive filtering
316 * such as the multicast hash-filter and the receive register settings. This
317 * is used to make the job of working out if the receive settings change and
318 * then issuing the new settings to the worker that will send the necessary
319 * commands.
320 */
321struct ks8851_rxctrl {
322	u16	mchash[4];
323	u16	rxcr1;
324	u16	rxcr2;
325};
326
327/**
328 * union ks8851_tx_hdr - tx header data
329 * @txb: The header as bytes
330 * @txw: The header as 16bit, little-endian words
331 *
332 * A dual representation of the tx header data to allow
333 * access to individual bytes, and to allow 16bit accesses
334 * with 16bit alignment.
335 */
336union ks8851_tx_hdr {
337	u8	txb[6];
338	__le16	txw[3];
339};
340
341/**
342 * struct ks8851_net - KS8851 driver private data
343 * @netdev: The network device we're bound to
344 * @statelock: Lock on this structure for tx list.
345 * @mii: The MII state information for the mii calls.
346 * @rxctrl: RX settings for @rxctrl_work.
347 * @rxctrl_work: Work queue for updating RX mode and multicast lists
348 * @txq: Queue of packets for transmission.
349 * @txh: Space for generating packet TX header in DMA-able data
350 * @rxd: Space for receiving SPI data, in DMA-able space.
351 * @txd: Space for transmitting SPI data, in DMA-able space.
352 * @msg_enable: The message flags controlling driver output (see ethtool).
353 * @fid: Incrementing frame id tag.
354 * @rc_ier: Cached copy of KS_IER.
355 * @rc_ccr: Cached copy of KS_CCR.
356 * @rc_rxqcr: Cached copy of KS_RXQCR.
357 * @eeprom: 93CX6 EEPROM state for accessing on-board EEPROM.
358 * @vdd_reg:	Optional regulator supplying the chip
359 * @vdd_io: Optional digital power supply for IO
360 * @gpio: Optional reset_n gpio
361 * @mii_bus: Pointer to MII bus structure
362 * @lock: Bus access lock callback
363 * @unlock: Bus access unlock callback
364 * @rdreg16: 16bit register read callback
365 * @wrreg16: 16bit register write callback
366 * @rdfifo: FIFO read callback
367 * @wrfifo: FIFO write callback
368 * @start_xmit: start_xmit() implementation callback
369 * @rx_skb: rx_skb() implementation callback
370 * @flush_tx_work: flush_tx_work() implementation callback
371 *
372 * The @statelock is used to protect information in the structure which may
373 * need to be accessed via several sources, such as the network driver layer
374 * or one of the work queues.
375 *
376 * We align the buffers we may use for rx/tx to ensure that if the SPI driver
377 * wants to DMA map them, it will not have any problems with data the driver
378 * modifies.
379 */
380struct ks8851_net {
381	struct net_device	*netdev;
382	spinlock_t		statelock;
383
384	union ks8851_tx_hdr	txh ____cacheline_aligned;
385	u8			rxd[8];
386	u8			txd[8];
387
388	u32			msg_enable ____cacheline_aligned;
389	u16			tx_space;
390	u8			fid;
391
392	u16			rc_ier;
393	u16			rc_rxqcr;
394	u16			rc_ccr;
395
396	struct mii_if_info	mii;
397	struct ks8851_rxctrl	rxctrl;
398
399	struct work_struct	rxctrl_work;
400
401	struct sk_buff_head	txq;
402
403	struct eeprom_93cx6	eeprom;
404	struct regulator	*vdd_reg;
405	struct regulator	*vdd_io;
406	struct gpio_desc	*gpio;
407	struct mii_bus		*mii_bus;
408
409	void			(*lock)(struct ks8851_net *ks,
410					unsigned long *flags);
411	void			(*unlock)(struct ks8851_net *ks,
412					  unsigned long *flags);
413	unsigned int		(*rdreg16)(struct ks8851_net *ks,
414					   unsigned int reg);
415	void			(*wrreg16)(struct ks8851_net *ks,
416					   unsigned int reg, unsigned int val);
417	void			(*rdfifo)(struct ks8851_net *ks, u8 *buff,
418					  unsigned int len);
419	void			(*wrfifo)(struct ks8851_net *ks,
420					  struct sk_buff *txp, bool irq);
421	netdev_tx_t		(*start_xmit)(struct sk_buff *skb,
422					      struct net_device *dev);
423	void			(*rx_skb)(struct ks8851_net *ks,
424					  struct sk_buff *skb);
425	void			(*flush_tx_work)(struct ks8851_net *ks);
426};
427
428int ks8851_probe_common(struct net_device *netdev, struct device *dev,
429			int msg_en);
430void ks8851_remove_common(struct device *dev);
431int ks8851_suspend(struct device *dev);
432int ks8851_resume(struct device *dev);
433
434static __maybe_unused SIMPLE_DEV_PM_OPS(ks8851_pm_ops,
435					ks8851_suspend, ks8851_resume);
436
437/**
438 * ks8851_done_tx - update and then free skbuff after transmitting
439 * @ks: The device state
440 * @txb: The buffer transmitted
441 */
442static void __maybe_unused ks8851_done_tx(struct ks8851_net *ks,
443					  struct sk_buff *txb)
444{
445	struct net_device *dev = ks->netdev;
446
447	dev->stats.tx_bytes += txb->len;
448	dev->stats.tx_packets++;
449
450	dev_kfree_skb(txb);
451}
452
453#endif /* __KS8851_H__ */
v5.4
  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* drivers/net/ethernet/micrel/ks8851.h
  3 *
  4 * Copyright 2009 Simtec Electronics
  5 *      Ben Dooks <ben@simtec.co.uk>
  6 *
  7 * KS8851 register definitions
  8*/
  9
 
 
 
 
 
 10#define KS_CCR					0x08
 11#define CCR_LE					(1 << 10)   /* KSZ8851-16MLL */
 12#define CCR_EEPROM				(1 << 9)
 13#define CCR_SPI					(1 << 8)    /* KSZ8851SNL    */
 14#define CCR_8BIT				(1 << 7)    /* KSZ8851-16MLL */
 15#define CCR_16BIT				(1 << 6)    /* KSZ8851-16MLL */
 16#define CCR_32BIT				(1 << 5)    /* KSZ8851-16MLL */
 17#define CCR_SHARED				(1 << 4)    /* KSZ8851-16MLL */
 18#define CCR_48PIN				(1 << 1)    /* KSZ8851-16MLL */
 19#define CCR_32PIN				(1 << 0)    /* KSZ8851SNL    */
 20
 21/* MAC address registers */
 22#define KS_MAR(_m)				(0x15 - (_m))
 23#define KS_MARL					0x10
 24#define KS_MARM					0x12
 25#define KS_MARH					0x14
 26
 27#define KS_OBCR					0x20
 28#define OBCR_ODS_16mA				(1 << 6)
 29
 30#define KS_EEPCR				0x22
 31#define EEPCR_EESRWA				(1 << 5)
 32#define EEPCR_EESA				(1 << 4)
 33#define EEPCR_EESB				(1 << 3)
 34#define EEPCR_EEDO				(1 << 2)
 35#define EEPCR_EESCK				(1 << 1)
 36#define EEPCR_EECS				(1 << 0)
 37
 38#define KS_MBIR					0x24
 39#define MBIR_TXMBF				(1 << 12)
 40#define MBIR_TXMBFA				(1 << 11)
 41#define MBIR_RXMBF				(1 << 4)
 42#define MBIR_RXMBFA				(1 << 3)
 43
 44#define KS_GRR					0x26
 45#define GRR_QMU					(1 << 1)
 46#define GRR_GSR					(1 << 0)
 47
 48#define KS_WFCR					0x2A
 49#define WFCR_MPRXE				(1 << 7)
 50#define WFCR_WF3E				(1 << 3)
 51#define WFCR_WF2E				(1 << 2)
 52#define WFCR_WF1E				(1 << 1)
 53#define WFCR_WF0E				(1 << 0)
 54
 55#define KS_WF0CRC0				0x30
 56#define KS_WF0CRC1				0x32
 57#define KS_WF0BM0				0x34
 58#define KS_WF0BM1				0x36
 59#define KS_WF0BM2				0x38
 60#define KS_WF0BM3				0x3A
 61
 62#define KS_WF1CRC0				0x40
 63#define KS_WF1CRC1				0x42
 64#define KS_WF1BM0				0x44
 65#define KS_WF1BM1				0x46
 66#define KS_WF1BM2				0x48
 67#define KS_WF1BM3				0x4A
 68
 69#define KS_WF2CRC0				0x50
 70#define KS_WF2CRC1				0x52
 71#define KS_WF2BM0				0x54
 72#define KS_WF2BM1				0x56
 73#define KS_WF2BM2				0x58
 74#define KS_WF2BM3				0x5A
 75
 76#define KS_WF3CRC0				0x60
 77#define KS_WF3CRC1				0x62
 78#define KS_WF3BM0				0x64
 79#define KS_WF3BM1				0x66
 80#define KS_WF3BM2				0x68
 81#define KS_WF3BM3				0x6A
 82
 83#define KS_TXCR					0x70
 84#define TXCR_TCGICMP				(1 << 8)
 85#define TXCR_TCGUDP				(1 << 7)
 86#define TXCR_TCGTCP				(1 << 6)
 87#define TXCR_TCGIP				(1 << 5)
 88#define TXCR_FTXQ				(1 << 4)
 89#define TXCR_TXFCE				(1 << 3)
 90#define TXCR_TXPE				(1 << 2)
 91#define TXCR_TXCRC				(1 << 1)
 92#define TXCR_TXE				(1 << 0)
 93
 94#define KS_TXSR					0x72
 95#define TXSR_TXLC				(1 << 13)
 96#define TXSR_TXMC				(1 << 12)
 97#define TXSR_TXFID_MASK				(0x3f << 0)
 98#define TXSR_TXFID_SHIFT			(0)
 99#define TXSR_TXFID_GET(_v)			(((_v) >> 0) & 0x3f)
100
101#define KS_RXCR1				0x74
102#define RXCR1_FRXQ				(1 << 15)
103#define RXCR1_RXUDPFCC				(1 << 14)
104#define RXCR1_RXTCPFCC				(1 << 13)
105#define RXCR1_RXIPFCC				(1 << 12)
106#define RXCR1_RXPAFMA				(1 << 11)
107#define RXCR1_RXFCE				(1 << 10)
108#define RXCR1_RXEFE				(1 << 9)
109#define RXCR1_RXMAFMA				(1 << 8)
110#define RXCR1_RXBE				(1 << 7)
111#define RXCR1_RXME				(1 << 6)
112#define RXCR1_RXUE				(1 << 5)
113#define RXCR1_RXAE				(1 << 4)
114#define RXCR1_RXINVF				(1 << 1)
115#define RXCR1_RXE				(1 << 0)
116
117#define KS_RXCR2				0x76
118#define RXCR2_SRDBL_MASK			(0x7 << 5)  /* KSZ8851SNL    */
119#define RXCR2_SRDBL_SHIFT			(5)	    /* KSZ8851SNL    */
120#define RXCR2_SRDBL_4B				(0x0 << 5)  /* KSZ8851SNL    */
121#define RXCR2_SRDBL_8B				(0x1 << 5)  /* KSZ8851SNL    */
122#define RXCR2_SRDBL_16B				(0x2 << 5)  /* KSZ8851SNL    */
123#define RXCR2_SRDBL_32B				(0x3 << 5)  /* KSZ8851SNL    */
124#define RXCR2_SRDBL_FRAME			(0x4 << 5)  /* KSZ8851SNL    */
125#define RXCR2_IUFFP				(1 << 4)
126#define RXCR2_RXIUFCEZ				(1 << 3)
127#define RXCR2_UDPLFE				(1 << 2)
128#define RXCR2_RXICMPFCC				(1 << 1)
129#define RXCR2_RXSAF				(1 << 0)
130
131#define KS_TXMIR				0x78
132
133#define KS_RXFHSR				0x7C
134#define RXFSHR_RXFV				(1 << 15)
135#define RXFSHR_RXICMPFCS			(1 << 13)
136#define RXFSHR_RXIPFCS				(1 << 12)
137#define RXFSHR_RXTCPFCS				(1 << 11)
138#define RXFSHR_RXUDPFCS				(1 << 10)
139#define RXFSHR_RXBF				(1 << 7)
140#define RXFSHR_RXMF				(1 << 6)
141#define RXFSHR_RXUF				(1 << 5)
142#define RXFSHR_RXMR				(1 << 4)
143#define RXFSHR_RXFT				(1 << 3)
144#define RXFSHR_RXFTL				(1 << 2)
145#define RXFSHR_RXRF				(1 << 1)
146#define RXFSHR_RXCE				(1 << 0)
147
148#define KS_RXFHBCR				0x7E
149#define RXFHBCR_CNT_MASK			(0xfff << 0)
150
151#define KS_TXQCR				0x80
152#define TXQCR_AETFE				(1 << 2)    /* KSZ8851SNL    */
153#define TXQCR_TXQMAM				(1 << 1)
154#define TXQCR_METFE				(1 << 0)
155
156#define KS_RXQCR				0x82
157#define RXQCR_RXDTTS				(1 << 12)
158#define RXQCR_RXDBCTS				(1 << 11)
159#define RXQCR_RXFCTS				(1 << 10)
160#define RXQCR_RXIPHTOE				(1 << 9)
161#define RXQCR_RXDTTE				(1 << 7)
162#define RXQCR_RXDBCTE				(1 << 6)
163#define RXQCR_RXFCTE				(1 << 5)
164#define RXQCR_ADRFE				(1 << 4)
165#define RXQCR_SDA				(1 << 3)
166#define RXQCR_RRXEF				(1 << 0)
167
168#define KS_TXFDPR				0x84
169#define TXFDPR_TXFPAI				(1 << 14)
170#define TXFDPR_TXFP_MASK			(0x7ff << 0)
171#define TXFDPR_TXFP_SHIFT			(0)
172
173#define KS_RXFDPR				0x86
174#define RXFDPR_RXFPAI				(1 << 14)
175#define RXFDPR_WST				(1 << 12)   /* KSZ8851-16MLL */
176#define RXFDPR_EMS				(1 << 11)   /* KSZ8851-16MLL */
177#define RXFDPR_RXFP_MASK			(0x7ff << 0)
178#define RXFDPR_RXFP_SHIFT			(0)
179
180#define KS_RXDTTR				0x8C
181#define KS_RXDBCTR				0x8E
182
183#define KS_IER					0x90
184#define KS_ISR					0x92
185#define IRQ_LCI					(1 << 15)
186#define IRQ_TXI					(1 << 14)
187#define IRQ_RXI					(1 << 13)
188#define IRQ_RXOI				(1 << 11)
189#define IRQ_TXPSI				(1 << 9)
190#define IRQ_RXPSI				(1 << 8)
191#define IRQ_TXSAI				(1 << 6)
192#define IRQ_RXWFDI				(1 << 5)
193#define IRQ_RXMPDI				(1 << 4)
194#define IRQ_LDI					(1 << 3)
195#define IRQ_EDI					(1 << 2)
196#define IRQ_SPIBEI				(1 << 1)    /* KSZ8851SNL    */
197#define IRQ_DEDI				(1 << 0)
198
199#define KS_RXFCTR				0x9C
200#define KS_RXFC					0x9D
201#define RXFCTR_RXFC_MASK			(0xff << 8)
202#define RXFCTR_RXFC_SHIFT			(8)
203#define RXFCTR_RXFC_GET(_v)			(((_v) >> 8) & 0xff)
204#define RXFCTR_RXFCT_MASK			(0xff << 0)
205#define RXFCTR_RXFCT_SHIFT			(0)
206
207#define KS_TXNTFSR				0x9E
208
209#define KS_MAHTR0				0xA0
210#define KS_MAHTR1				0xA2
211#define KS_MAHTR2				0xA4
212#define KS_MAHTR3				0xA6
213
214#define KS_FCLWR				0xB0
215#define KS_FCHWR				0xB2
216#define KS_FCOWR				0xB4
217
218#define KS_CIDER				0xC0
219#define CIDER_ID				0x8870
220#define CIDER_REV_MASK				(0x7 << 1)
221#define CIDER_REV_SHIFT				(1)
222#define CIDER_REV_GET(_v)			(((_v) >> 1) & 0x7)
223
224#define KS_CGCR					0xC6
225
226#define KS_IACR					0xC8
227#define IACR_RDEN				(1 << 12)
228#define IACR_TSEL_MASK				(0x3 << 10)
229#define IACR_TSEL_SHIFT				(10)
230#define IACR_TSEL_MIB				(0x3 << 10)
231#define IACR_ADDR_MASK				(0x1f << 0)
232#define IACR_ADDR_SHIFT				(0)
233
234#define KS_IADLR				0xD0
235#define KS_IAHDR				0xD2
236
237#define KS_PMECR				0xD4
238#define PMECR_PME_DELAY				(1 << 14)
239#define PMECR_PME_POL				(1 << 12)
240#define PMECR_WOL_WAKEUP			(1 << 11)
241#define PMECR_WOL_MAGICPKT			(1 << 10)
242#define PMECR_WOL_LINKUP			(1 << 9)
243#define PMECR_WOL_ENERGY			(1 << 8)
244#define PMECR_AUTO_WAKE_EN			(1 << 7)
245#define PMECR_WAKEUP_NORMAL			(1 << 6)
246#define PMECR_WKEVT_MASK			(0xf << 2)
247#define PMECR_WKEVT_SHIFT			(2)
248#define PMECR_WKEVT_GET(_v)			(((_v) >> 2) & 0xf)
249#define PMECR_WKEVT_ENERGY			(0x1 << 2)
250#define PMECR_WKEVT_LINK			(0x2 << 2)
251#define PMECR_WKEVT_MAGICPKT			(0x4 << 2)
252#define PMECR_WKEVT_FRAME			(0x8 << 2)
253#define PMECR_PM_MASK				(0x3 << 0)
254#define PMECR_PM_SHIFT				(0)
255#define PMECR_PM_NORMAL				(0x0 << 0)
256#define PMECR_PM_ENERGY				(0x1 << 0)
257#define PMECR_PM_SOFTDOWN			(0x2 << 0)
258#define PMECR_PM_POWERSAVE			(0x3 << 0)
259
260/* Standard MII PHY data */
261#define KS_P1MBCR				0xE4
262#define KS_P1MBSR				0xE6
263#define KS_PHY1ILR				0xE8
264#define KS_PHY1IHR				0xEA
265#define KS_P1ANAR				0xEC
266#define KS_P1ANLPR				0xEE
267
268#define KS_P1SCLMD				0xF4
269
270#define KS_P1CR					0xF6
271#define P1CR_LEDOFF				(1 << 15)
272#define P1CR_TXIDS				(1 << 14)
273#define P1CR_RESTARTAN				(1 << 13)
274#define P1CR_DISAUTOMDIX			(1 << 10)
275#define P1CR_FORCEMDIX				(1 << 9)
276#define P1CR_AUTONEGEN				(1 << 7)
277#define P1CR_FORCE100				(1 << 6)
278#define P1CR_FORCEFDX				(1 << 5)
279#define P1CR_ADV_FLOW				(1 << 4)
280#define P1CR_ADV_100BT_FDX			(1 << 3)
281#define P1CR_ADV_100BT_HDX			(1 << 2)
282#define P1CR_ADV_10BT_FDX			(1 << 1)
283#define P1CR_ADV_10BT_HDX			(1 << 0)
284
285#define KS_P1SR					0xF8
286#define P1SR_HP_MDIX				(1 << 15)
287#define P1SR_REV_POL				(1 << 13)
288#define P1SR_OP_100M				(1 << 10)
289#define P1SR_OP_FDX				(1 << 9)
290#define P1SR_OP_MDI				(1 << 7)
291#define P1SR_AN_DONE				(1 << 6)
292#define P1SR_LINK_GOOD				(1 << 5)
293#define P1SR_PNTR_FLOW				(1 << 4)
294#define P1SR_PNTR_100BT_FDX			(1 << 3)
295#define P1SR_PNTR_100BT_HDX			(1 << 2)
296#define P1SR_PNTR_10BT_FDX			(1 << 1)
297#define P1SR_PNTR_10BT_HDX			(1 << 0)
298
299/* TX Frame control */
300#define TXFR_TXIC				(1 << 15)
301#define TXFR_TXFID_MASK				(0x3f << 0)
302#define TXFR_TXFID_SHIFT			(0)