Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6#include <linux/arm-smccc.h>
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/soc/mediatek/mtk_sip_svc.h>
19#include <soc/mediatek/smi.h>
20#include <dt-bindings/memory/mt2701-larb-port.h>
21#include <dt-bindings/memory/mtk-memory-port.h>
22
23/* SMI COMMON */
24#define SMI_L1LEN 0x100
25
26#define SMI_L1_ARB 0x200
27#define SMI_BUS_SEL 0x220
28#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
29/* All are MMU0 defaultly. Only specialize mmu1 here. */
30#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
31
32#define SMI_READ_FIFO_TH 0x230
33#define SMI_M4U_TH 0x234
34#define SMI_FIFO_TH1 0x238
35#define SMI_FIFO_TH2 0x23c
36#define SMI_DCM 0x300
37#define SMI_DUMMY 0x444
38
39/* SMI LARB */
40#define SMI_LARB_SLP_CON 0xc
41#define SLP_PROT_EN BIT(0)
42#define SLP_PROT_RDY BIT(16)
43
44#define SMI_LARB_CMD_THRT_CON 0x24
45#define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
46#define SMI_LARB_THRT_RD_NU_LMT (5 << 4)
47
48#define SMI_LARB_SW_FLAG 0x40
49#define SMI_LARB_SW_FLAG_1 0x1
50
51#define SMI_LARB_OSTDL_PORT 0x200
52#define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
53
54/* Below are about mmu enable registers, they are different in SoCs */
55/* gen1: mt2701 */
56#define REG_SMI_SECUR_CON_BASE 0x5c0
57
58/* every register control 8 port, register offset 0x4 */
59#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
60#define REG_SMI_SECUR_CON_ADDR(id) \
61 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
62
63/*
64 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
66 * or non-security.
67 */
68#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
69#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
70/* mt2701 domain should be set to 3 */
71#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
72
73/* gen2: */
74/* mt8167 */
75#define MT8167_SMI_LARB_MMU_EN 0xfc0
76
77/* mt8173 */
78#define MT8173_SMI_LARB_MMU_EN 0xf00
79
80/* general */
81#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
82#define F_MMU_EN BIT(0)
83#define BANK_SEL(id) ({ \
84 u32 _id = (id) & 0x3; \
85 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
86})
87
88#define SMI_COMMON_INIT_REGS_NR 6
89#define SMI_LARB_PORT_NR_MAX 32
90
91#define MTK_SMI_FLAG_THRT_UPDATE BIT(0)
92#define MTK_SMI_FLAG_SW_FLAG BIT(1)
93#define MTK_SMI_FLAG_SLEEP_CTL BIT(2)
94#define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3)
95#define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x)))
96
97struct mtk_smi_reg_pair {
98 unsigned int offset;
99 u32 value;
100};
101
102enum mtk_smi_type {
103 MTK_SMI_GEN1,
104 MTK_SMI_GEN2, /* gen2 smi common */
105 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */
106};
107
108/* larbs: Require apb/smi clocks while gals is optional. */
109static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
110#define MTK_SMI_LARB_REQ_CLK_NR 2
111#define MTK_SMI_LARB_OPT_CLK_NR 1
112
113/*
114 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
115 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
116 */
117static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
118#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks)
119#define MTK_SMI_COM_REQ_CLK_NR 2
120#define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
121#define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
122
123struct mtk_smi_common_plat {
124 enum mtk_smi_type type;
125 bool has_gals;
126 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
127
128 const struct mtk_smi_reg_pair *init;
129};
130
131struct mtk_smi_larb_gen {
132 int port_in_larb[MTK_LARB_NR_MAX + 1];
133 int (*config_port)(struct device *dev);
134 unsigned int larb_direct_to_common_mask;
135 unsigned int flags_general;
136 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX];
137};
138
139struct mtk_smi {
140 struct device *dev;
141 unsigned int clk_num;
142 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX];
143 struct clk *clk_async; /*only needed by mt2701*/
144 union {
145 void __iomem *smi_ao_base; /* only for gen1 */
146 void __iomem *base; /* only for gen2 */
147 };
148 struct device *smi_common_dev; /* for sub common */
149 const struct mtk_smi_common_plat *plat;
150};
151
152struct mtk_smi_larb { /* larb: local arbiter */
153 struct mtk_smi smi;
154 void __iomem *base;
155 struct device *smi_common_dev; /* common or sub-common dev */
156 const struct mtk_smi_larb_gen *larb_gen;
157 int larbid;
158 u32 *mmu;
159 unsigned char *bank;
160};
161
162static int
163mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
164{
165 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
166 struct mtk_smi_larb_iommu *larb_mmu = data;
167 unsigned int i;
168
169 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
170 if (dev == larb_mmu[i].dev) {
171 larb->larbid = i;
172 larb->mmu = &larb_mmu[i].mmu;
173 larb->bank = larb_mmu[i].bank;
174 return 0;
175 }
176 }
177 return -ENODEV;
178}
179
180static void
181mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
182{
183 /* Do nothing as the iommu is always enabled. */
184}
185
186static const struct component_ops mtk_smi_larb_component_ops = {
187 .bind = mtk_smi_larb_bind,
188 .unbind = mtk_smi_larb_unbind,
189};
190
191static int mtk_smi_larb_config_port_gen1(struct device *dev)
192{
193 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
194 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
195 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
196 int i, m4u_port_id, larb_port_num;
197 u32 sec_con_val, reg_val;
198
199 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
200 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
201 - larb_gen->port_in_larb[larb->larbid];
202
203 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
204 if (*larb->mmu & BIT(i)) {
205 /* bit[port + 3] controls the virtual or physical */
206 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
207 } else {
208 /* do not need to enable m4u for this port */
209 continue;
210 }
211 reg_val = readl(common->smi_ao_base
212 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
214 reg_val |= sec_con_val;
215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
216 writel(reg_val,
217 common->smi_ao_base
218 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
219 }
220 return 0;
221}
222
223static int mtk_smi_larb_config_port_mt8167(struct device *dev)
224{
225 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
226
227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
228 return 0;
229}
230
231static int mtk_smi_larb_config_port_mt8173(struct device *dev)
232{
233 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
234
235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
236 return 0;
237}
238
239static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
240{
241 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
242 u32 reg, flags_general = larb->larb_gen->flags_general;
243 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
244 struct arm_smccc_res res;
245 int i;
246
247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
248 return 0;
249
250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
253 reg |= SMI_LARB_THRT_RD_NU_LMT;
254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
255 }
256
257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
259
260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
262
263 /*
264 * When mmu_en bits are in security world, the bank_sel still is in the
265 * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no
266 * effect in this case.
267 */
268 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) {
269 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB,
270 larb->larbid, *larb->mmu, 0, 0, 0, 0, &res);
271 if (res.a0 != 0) {
272 dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0);
273 return -EINVAL;
274 }
275 }
276
277 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
279 reg |= F_MMU_EN;
280 reg |= BANK_SEL(larb->bank[i]);
281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
282 }
283 return 0;
284}
285
286static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
287 [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
288 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
289 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
290 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
291 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
292 [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
293 [6] = {0x06, 0x01, 0x06, 0x0a,},
294 [7] = {0x0c, 0x0c, 0x12,},
295 [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
296 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
297 0x03, 0x01, 0x1e, 0x01, 0x05,},
298 [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
299 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
300 [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
301 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
302 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
303 [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
304 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
305 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
306 [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
307 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
308 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
309 [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
310 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
311 [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
312 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
313 0x02, 0x02, 0x01, 0x01,},
314 [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
315 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
316 0x0c, 0x01, 0x01,},
317 [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
318 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
319 [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
320 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
321 [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
322 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
323 [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
324 [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
325 [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
326 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
327 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
328 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
329 0x01,},
330 [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
331 [24] = {0x12, 0x06, 0x12, 0x06,},
332 [25] = {0x01},
333};
334
335static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
336 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
337 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
338 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */
339 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
340 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
341 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
342 [6] = {0x06, 0x01, 0x06, 0x0a,},
343 [7] = {0x0c, 0x0c, 0x12,},
344 [8] = {0x0c, 0x0c, 0x12,},
345 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
346 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
347 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
348 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
349 0x0d, 0x06, 0x10, 0x10,},
350 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
351 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
352 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
353 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
354 0x01, 0x02, 0x02, 0x08, 0x02,},
355 [15] = {},
356 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
357 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
358 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
359 [18] = {0x12, 0x06, 0x12, 0x06,},
360 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
361 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
362 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
363 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
364 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
365 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
366 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
367 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
368 [23] = {0x18, 0x01,},
369 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
370 0x01, 0x01,},
371 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
372 0x02, 0x01,},
373 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
374 0x02, 0x01,},
375 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
376 0x02, 0x01,},
377 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
378};
379
380static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
381 .port_in_larb = {
382 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
383 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
384 },
385 .config_port = mtk_smi_larb_config_port_gen1,
386};
387
388static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
389 .config_port = mtk_smi_larb_config_port_gen2_general,
390 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
391};
392
393static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
394 .config_port = mtk_smi_larb_config_port_gen2_general,
395 .larb_direct_to_common_mask =
396 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
397 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
398};
399
400static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
401 /* mt8167 do not need the port in larb */
402 .config_port = mtk_smi_larb_config_port_mt8167,
403};
404
405static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
406 /* mt8173 do not need the port in larb */
407 .config_port = mtk_smi_larb_config_port_mt8173,
408};
409
410static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
411 .config_port = mtk_smi_larb_config_port_gen2_general,
412 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
413 /* IPU0 | IPU1 | CCU */
414};
415
416static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
417 .config_port = mtk_smi_larb_config_port_gen2_general,
418 .flags_general = MTK_SMI_FLAG_SLEEP_CTL,
419};
420
421static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
422 .config_port = mtk_smi_larb_config_port_gen2_general,
423 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
424 MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
425 .ostd = mtk_smi_larb_mt8188_ostd,
426};
427
428static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
429 .config_port = mtk_smi_larb_config_port_gen2_general,
430};
431
432static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
433 .config_port = mtk_smi_larb_config_port_gen2_general,
434 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
435 MTK_SMI_FLAG_SLEEP_CTL,
436 .ostd = mtk_smi_larb_mt8195_ostd,
437};
438
439static const struct of_device_id mtk_smi_larb_of_ids[] = {
440 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
441 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
442 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
443 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
444 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
445 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
446 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
447 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
448 {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
449 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
450 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
451 {}
452};
453
454static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
455{
456 int ret;
457 u32 tmp;
458
459 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
460 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
461 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
462 if (ret) {
463 /* TODO: Reset this larb if it fails here. */
464 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
465 }
466 return ret;
467}
468
469static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
470{
471 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
472}
473
474static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
475{
476 struct platform_device *smi_com_pdev;
477 struct device_node *smi_com_node;
478 struct device *smi_com_dev;
479 struct device_link *link;
480
481 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
482 if (!smi_com_node)
483 return -EINVAL;
484
485 smi_com_pdev = of_find_device_by_node(smi_com_node);
486 of_node_put(smi_com_node);
487 if (smi_com_pdev) {
488 /* smi common is the supplier, Make sure it is ready before */
489 if (!platform_get_drvdata(smi_com_pdev)) {
490 put_device(&smi_com_pdev->dev);
491 return -EPROBE_DEFER;
492 }
493 smi_com_dev = &smi_com_pdev->dev;
494 link = device_link_add(dev, smi_com_dev,
495 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
496 if (!link) {
497 dev_err(dev, "Unable to link smi-common dev\n");
498 put_device(&smi_com_pdev->dev);
499 return -ENODEV;
500 }
501 *com_dev = smi_com_dev;
502 } else {
503 dev_err(dev, "Failed to get the smi_common device\n");
504 return -EINVAL;
505 }
506 return 0;
507}
508
509static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
510 const char * const clks[],
511 unsigned int clk_nr_required,
512 unsigned int clk_nr_optional)
513{
514 int i, ret;
515
516 for (i = 0; i < clk_nr_required; i++)
517 smi->clks[i].id = clks[i];
518 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
519 if (ret)
520 return ret;
521
522 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
523 smi->clks[i].id = clks[i];
524 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
525 smi->clks + clk_nr_required);
526 smi->clk_num = clk_nr_required + clk_nr_optional;
527 return ret;
528}
529
530static int mtk_smi_larb_probe(struct platform_device *pdev)
531{
532 struct mtk_smi_larb *larb;
533 struct device *dev = &pdev->dev;
534 int ret;
535
536 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
537 if (!larb)
538 return -ENOMEM;
539
540 larb->larb_gen = of_device_get_match_data(dev);
541 larb->base = devm_platform_ioremap_resource(pdev, 0);
542 if (IS_ERR(larb->base))
543 return PTR_ERR(larb->base);
544
545 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
546 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
547 if (ret)
548 return ret;
549
550 larb->smi.dev = dev;
551
552 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
553 if (ret < 0)
554 return ret;
555
556 pm_runtime_enable(dev);
557 platform_set_drvdata(pdev, larb);
558 ret = component_add(dev, &mtk_smi_larb_component_ops);
559 if (ret)
560 goto err_pm_disable;
561 return 0;
562
563err_pm_disable:
564 pm_runtime_disable(dev);
565 device_link_remove(dev, larb->smi_common_dev);
566 return ret;
567}
568
569static int mtk_smi_larb_remove(struct platform_device *pdev)
570{
571 struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
572
573 device_link_remove(&pdev->dev, larb->smi_common_dev);
574 pm_runtime_disable(&pdev->dev);
575 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
576 return 0;
577}
578
579static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
580{
581 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
582 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
583 int ret;
584
585 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
586 if (ret)
587 return ret;
588
589 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
590 mtk_smi_larb_sleep_ctrl_disable(larb);
591
592 /* Configure the basic setting for this larb */
593 return larb_gen->config_port(dev);
594}
595
596static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
597{
598 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
599 int ret;
600
601 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
602 ret = mtk_smi_larb_sleep_ctrl_enable(larb);
603 if (ret)
604 return ret;
605 }
606
607 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
608 return 0;
609}
610
611static const struct dev_pm_ops smi_larb_pm_ops = {
612 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
613 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
614 pm_runtime_force_resume)
615};
616
617static struct platform_driver mtk_smi_larb_driver = {
618 .probe = mtk_smi_larb_probe,
619 .remove = mtk_smi_larb_remove,
620 .driver = {
621 .name = "mtk-smi-larb",
622 .of_match_table = mtk_smi_larb_of_ids,
623 .pm = &smi_larb_pm_ops,
624 }
625};
626
627static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
628 {SMI_L1_ARB, 0x1b},
629 {SMI_M4U_TH, 0xce810c85},
630 {SMI_FIFO_TH1, 0x43214c8},
631 {SMI_READ_FIFO_TH, 0x191f},
632};
633
634static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
635 {SMI_L1LEN, 0xb},
636 {SMI_M4U_TH, 0xe100e10},
637 {SMI_FIFO_TH1, 0x506090a},
638 {SMI_FIFO_TH2, 0x506090a},
639 {SMI_DCM, 0x4f1},
640 {SMI_DUMMY, 0x1},
641};
642
643static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
644 .type = MTK_SMI_GEN1,
645};
646
647static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
648 .type = MTK_SMI_GEN2,
649};
650
651static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
652 .type = MTK_SMI_GEN2,
653 .has_gals = true,
654 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
655 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
656};
657
658static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
659 .type = MTK_SMI_GEN2,
660 .bus_sel = F_MMU1_LARB(0),
661 .init = mtk_smi_common_mt6795_init,
662};
663
664static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
665 .type = MTK_SMI_GEN2,
666 .has_gals = true,
667 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
668 F_MMU1_LARB(7),
669};
670
671static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
672 .type = MTK_SMI_GEN2,
673 .has_gals = true,
674 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
675};
676
677static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
678 .type = MTK_SMI_GEN2,
679 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
680 .init = mtk_smi_common_mt8195_init,
681};
682
683static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
684 .type = MTK_SMI_GEN2,
685 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
686 .init = mtk_smi_common_mt8195_init,
687};
688
689static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
690 .type = MTK_SMI_GEN2,
691 .has_gals = true,
692 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
693 F_MMU1_LARB(6),
694};
695
696static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
697 .type = MTK_SMI_GEN2,
698 .has_gals = true,
699 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
700 F_MMU1_LARB(7),
701 .init = mtk_smi_common_mt8195_init,
702};
703
704static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
705 .type = MTK_SMI_GEN2,
706 .has_gals = true,
707 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
708 .init = mtk_smi_common_mt8195_init,
709};
710
711static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
712 .type = MTK_SMI_GEN2_SUB_COMM,
713 .has_gals = true,
714};
715
716static const struct of_device_id mtk_smi_common_of_ids[] = {
717 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
718 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
719 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
720 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
721 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
722 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
723 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
724 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
725 {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
726 {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
727 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
728 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
729 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
730 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
731 {}
732};
733
734static int mtk_smi_common_probe(struct platform_device *pdev)
735{
736 struct device *dev = &pdev->dev;
737 struct mtk_smi *common;
738 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
739
740 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
741 if (!common)
742 return -ENOMEM;
743 common->dev = dev;
744 common->plat = of_device_get_match_data(dev);
745
746 if (common->plat->has_gals) {
747 if (common->plat->type == MTK_SMI_GEN2)
748 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
749 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
750 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
751 }
752 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
753 if (ret)
754 return ret;
755
756 /*
757 * for mtk smi gen 1, we need to get the ao(always on) base to config
758 * m4u port, and we need to enable the aync clock for transform the smi
759 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
760 * base.
761 */
762 if (common->plat->type == MTK_SMI_GEN1) {
763 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
764 if (IS_ERR(common->smi_ao_base))
765 return PTR_ERR(common->smi_ao_base);
766
767 common->clk_async = devm_clk_get(dev, "async");
768 if (IS_ERR(common->clk_async))
769 return PTR_ERR(common->clk_async);
770
771 ret = clk_prepare_enable(common->clk_async);
772 if (ret)
773 return ret;
774 } else {
775 common->base = devm_platform_ioremap_resource(pdev, 0);
776 if (IS_ERR(common->base))
777 return PTR_ERR(common->base);
778 }
779
780 /* link its smi-common if this is smi-sub-common */
781 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
782 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
783 if (ret < 0)
784 return ret;
785 }
786
787 pm_runtime_enable(dev);
788 platform_set_drvdata(pdev, common);
789 return 0;
790}
791
792static int mtk_smi_common_remove(struct platform_device *pdev)
793{
794 struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
795
796 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
797 device_link_remove(&pdev->dev, common->smi_common_dev);
798 pm_runtime_disable(&pdev->dev);
799 return 0;
800}
801
802static int __maybe_unused mtk_smi_common_resume(struct device *dev)
803{
804 struct mtk_smi *common = dev_get_drvdata(dev);
805 const struct mtk_smi_reg_pair *init = common->plat->init;
806 u32 bus_sel = common->plat->bus_sel; /* default is 0 */
807 int ret, i;
808
809 ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
810 if (ret)
811 return ret;
812
813 if (common->plat->type != MTK_SMI_GEN2)
814 return 0;
815
816 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
817 writel_relaxed(init[i].value, common->base + init[i].offset);
818
819 writel(bus_sel, common->base + SMI_BUS_SEL);
820 return 0;
821}
822
823static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
824{
825 struct mtk_smi *common = dev_get_drvdata(dev);
826
827 clk_bulk_disable_unprepare(common->clk_num, common->clks);
828 return 0;
829}
830
831static const struct dev_pm_ops smi_common_pm_ops = {
832 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
833 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
834 pm_runtime_force_resume)
835};
836
837static struct platform_driver mtk_smi_common_driver = {
838 .probe = mtk_smi_common_probe,
839 .remove = mtk_smi_common_remove,
840 .driver = {
841 .name = "mtk-smi-common",
842 .of_match_table = mtk_smi_common_of_ids,
843 .pm = &smi_common_pm_ops,
844 }
845};
846
847static struct platform_driver * const smidrivers[] = {
848 &mtk_smi_common_driver,
849 &mtk_smi_larb_driver,
850};
851
852static int __init mtk_smi_init(void)
853{
854 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
855}
856module_init(mtk_smi_init);
857
858static void __exit mtk_smi_exit(void)
859{
860 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
861}
862module_exit(mtk_smi_exit);
863
864MODULE_DESCRIPTION("MediaTek SMI driver");
865MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <soc/mediatek/smi.h>
17#include <dt-bindings/memory/mt2701-larb-port.h>
18
19/* mt8173 */
20#define SMI_LARB_MMU_EN 0xf00
21
22/* mt2701 */
23#define REG_SMI_SECUR_CON_BASE 0x5c0
24
25/* every register control 8 port, register offset 0x4 */
26#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
27#define REG_SMI_SECUR_CON_ADDR(id) \
28 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
29
30/*
31 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
32 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
33 * or non-security.
34 */
35#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
36#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
37/* mt2701 domain should be set to 3 */
38#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
39
40/* mt2712 */
41#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
42#define F_MMU_EN BIT(0)
43
44/* SMI COMMON */
45#define SMI_BUS_SEL 0x220
46#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
47/* All are MMU0 defaultly. Only specialize mmu1 here. */
48#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
49
50enum mtk_smi_gen {
51 MTK_SMI_GEN1,
52 MTK_SMI_GEN2
53};
54
55struct mtk_smi_common_plat {
56 enum mtk_smi_gen gen;
57 bool has_gals;
58 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
59};
60
61struct mtk_smi_larb_gen {
62 int port_in_larb[MTK_LARB_NR_MAX + 1];
63 void (*config_port)(struct device *);
64 unsigned int larb_direct_to_common_mask;
65 bool has_gals;
66};
67
68struct mtk_smi {
69 struct device *dev;
70 struct clk *clk_apb, *clk_smi;
71 struct clk *clk_gals0, *clk_gals1;
72 struct clk *clk_async; /*only needed by mt2701*/
73 union {
74 void __iomem *smi_ao_base; /* only for gen1 */
75 void __iomem *base; /* only for gen2 */
76 };
77 const struct mtk_smi_common_plat *plat;
78};
79
80struct mtk_smi_larb { /* larb: local arbiter */
81 struct mtk_smi smi;
82 void __iomem *base;
83 struct device *smi_common_dev;
84 const struct mtk_smi_larb_gen *larb_gen;
85 int larbid;
86 u32 *mmu;
87};
88
89static int mtk_smi_clk_enable(const struct mtk_smi *smi)
90{
91 int ret;
92
93 ret = clk_prepare_enable(smi->clk_apb);
94 if (ret)
95 return ret;
96
97 ret = clk_prepare_enable(smi->clk_smi);
98 if (ret)
99 goto err_disable_apb;
100
101 ret = clk_prepare_enable(smi->clk_gals0);
102 if (ret)
103 goto err_disable_smi;
104
105 ret = clk_prepare_enable(smi->clk_gals1);
106 if (ret)
107 goto err_disable_gals0;
108
109 return 0;
110
111err_disable_gals0:
112 clk_disable_unprepare(smi->clk_gals0);
113err_disable_smi:
114 clk_disable_unprepare(smi->clk_smi);
115err_disable_apb:
116 clk_disable_unprepare(smi->clk_apb);
117 return ret;
118}
119
120static void mtk_smi_clk_disable(const struct mtk_smi *smi)
121{
122 clk_disable_unprepare(smi->clk_gals1);
123 clk_disable_unprepare(smi->clk_gals0);
124 clk_disable_unprepare(smi->clk_smi);
125 clk_disable_unprepare(smi->clk_apb);
126}
127
128int mtk_smi_larb_get(struct device *larbdev)
129{
130 int ret = pm_runtime_get_sync(larbdev);
131
132 return (ret < 0) ? ret : 0;
133}
134EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
135
136void mtk_smi_larb_put(struct device *larbdev)
137{
138 pm_runtime_put_sync(larbdev);
139}
140EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
141
142static int
143mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
144{
145 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
146 struct mtk_smi_larb_iommu *larb_mmu = data;
147 unsigned int i;
148
149 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
150 if (dev == larb_mmu[i].dev) {
151 larb->larbid = i;
152 larb->mmu = &larb_mmu[i].mmu;
153 return 0;
154 }
155 }
156 return -ENODEV;
157}
158
159static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
160{
161 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
162 u32 reg;
163 int i;
164
165 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
166 return;
167
168 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
169 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
170 reg |= F_MMU_EN;
171 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
172 }
173}
174
175static void mtk_smi_larb_config_port_mt8173(struct device *dev)
176{
177 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
178
179 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
180}
181
182static void mtk_smi_larb_config_port_gen1(struct device *dev)
183{
184 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
185 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
186 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
187 int i, m4u_port_id, larb_port_num;
188 u32 sec_con_val, reg_val;
189
190 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
191 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
192 - larb_gen->port_in_larb[larb->larbid];
193
194 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
195 if (*larb->mmu & BIT(i)) {
196 /* bit[port + 3] controls the virtual or physical */
197 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
198 } else {
199 /* do not need to enable m4u for this port */
200 continue;
201 }
202 reg_val = readl(common->smi_ao_base
203 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
204 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
205 reg_val |= sec_con_val;
206 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
207 writel(reg_val,
208 common->smi_ao_base
209 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
210 }
211}
212
213static void
214mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
215{
216 /* Do nothing as the iommu is always enabled. */
217}
218
219static const struct component_ops mtk_smi_larb_component_ops = {
220 .bind = mtk_smi_larb_bind,
221 .unbind = mtk_smi_larb_unbind,
222};
223
224static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
225 /* mt8173 do not need the port in larb */
226 .config_port = mtk_smi_larb_config_port_mt8173,
227};
228
229static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
230 .port_in_larb = {
231 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
232 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
233 },
234 .config_port = mtk_smi_larb_config_port_gen1,
235};
236
237static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
238 .config_port = mtk_smi_larb_config_port_gen2_general,
239 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
240};
241
242static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
243 .has_gals = true,
244 .config_port = mtk_smi_larb_config_port_gen2_general,
245 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
246 /* IPU0 | IPU1 | CCU */
247};
248
249static const struct of_device_id mtk_smi_larb_of_ids[] = {
250 {
251 .compatible = "mediatek,mt8173-smi-larb",
252 .data = &mtk_smi_larb_mt8173
253 },
254 {
255 .compatible = "mediatek,mt2701-smi-larb",
256 .data = &mtk_smi_larb_mt2701
257 },
258 {
259 .compatible = "mediatek,mt2712-smi-larb",
260 .data = &mtk_smi_larb_mt2712
261 },
262 {
263 .compatible = "mediatek,mt8183-smi-larb",
264 .data = &mtk_smi_larb_mt8183
265 },
266 {}
267};
268
269static int mtk_smi_larb_probe(struct platform_device *pdev)
270{
271 struct mtk_smi_larb *larb;
272 struct resource *res;
273 struct device *dev = &pdev->dev;
274 struct device_node *smi_node;
275 struct platform_device *smi_pdev;
276
277 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
278 if (!larb)
279 return -ENOMEM;
280
281 larb->larb_gen = of_device_get_match_data(dev);
282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
283 larb->base = devm_ioremap_resource(dev, res);
284 if (IS_ERR(larb->base))
285 return PTR_ERR(larb->base);
286
287 larb->smi.clk_apb = devm_clk_get(dev, "apb");
288 if (IS_ERR(larb->smi.clk_apb))
289 return PTR_ERR(larb->smi.clk_apb);
290
291 larb->smi.clk_smi = devm_clk_get(dev, "smi");
292 if (IS_ERR(larb->smi.clk_smi))
293 return PTR_ERR(larb->smi.clk_smi);
294
295 if (larb->larb_gen->has_gals) {
296 /* The larbs may still haven't gals even if the SoC support.*/
297 larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
298 if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
299 larb->smi.clk_gals0 = NULL;
300 else if (IS_ERR(larb->smi.clk_gals0))
301 return PTR_ERR(larb->smi.clk_gals0);
302 }
303 larb->smi.dev = dev;
304
305 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
306 if (!smi_node)
307 return -EINVAL;
308
309 smi_pdev = of_find_device_by_node(smi_node);
310 of_node_put(smi_node);
311 if (smi_pdev) {
312 if (!platform_get_drvdata(smi_pdev))
313 return -EPROBE_DEFER;
314 larb->smi_common_dev = &smi_pdev->dev;
315 } else {
316 dev_err(dev, "Failed to get the smi_common device\n");
317 return -EINVAL;
318 }
319
320 pm_runtime_enable(dev);
321 platform_set_drvdata(pdev, larb);
322 return component_add(dev, &mtk_smi_larb_component_ops);
323}
324
325static int mtk_smi_larb_remove(struct platform_device *pdev)
326{
327 pm_runtime_disable(&pdev->dev);
328 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
329 return 0;
330}
331
332static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
333{
334 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
335 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
336 int ret;
337
338 /* Power on smi-common. */
339 ret = pm_runtime_get_sync(larb->smi_common_dev);
340 if (ret < 0) {
341 dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
342 return ret;
343 }
344
345 ret = mtk_smi_clk_enable(&larb->smi);
346 if (ret < 0) {
347 dev_err(dev, "Failed to enable clock(%d).\n", ret);
348 pm_runtime_put_sync(larb->smi_common_dev);
349 return ret;
350 }
351
352 /* Configure the basic setting for this larb */
353 larb_gen->config_port(dev);
354
355 return 0;
356}
357
358static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
359{
360 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
361
362 mtk_smi_clk_disable(&larb->smi);
363 pm_runtime_put_sync(larb->smi_common_dev);
364 return 0;
365}
366
367static const struct dev_pm_ops smi_larb_pm_ops = {
368 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
369};
370
371static struct platform_driver mtk_smi_larb_driver = {
372 .probe = mtk_smi_larb_probe,
373 .remove = mtk_smi_larb_remove,
374 .driver = {
375 .name = "mtk-smi-larb",
376 .of_match_table = mtk_smi_larb_of_ids,
377 .pm = &smi_larb_pm_ops,
378 }
379};
380
381static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
382 .gen = MTK_SMI_GEN1,
383};
384
385static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
386 .gen = MTK_SMI_GEN2,
387};
388
389static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
390 .gen = MTK_SMI_GEN2,
391 .has_gals = true,
392 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
393 F_MMU1_LARB(7),
394};
395
396static const struct of_device_id mtk_smi_common_of_ids[] = {
397 {
398 .compatible = "mediatek,mt8173-smi-common",
399 .data = &mtk_smi_common_gen2,
400 },
401 {
402 .compatible = "mediatek,mt2701-smi-common",
403 .data = &mtk_smi_common_gen1,
404 },
405 {
406 .compatible = "mediatek,mt2712-smi-common",
407 .data = &mtk_smi_common_gen2,
408 },
409 {
410 .compatible = "mediatek,mt8183-smi-common",
411 .data = &mtk_smi_common_mt8183,
412 },
413 {}
414};
415
416static int mtk_smi_common_probe(struct platform_device *pdev)
417{
418 struct device *dev = &pdev->dev;
419 struct mtk_smi *common;
420 struct resource *res;
421 int ret;
422
423 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
424 if (!common)
425 return -ENOMEM;
426 common->dev = dev;
427 common->plat = of_device_get_match_data(dev);
428
429 common->clk_apb = devm_clk_get(dev, "apb");
430 if (IS_ERR(common->clk_apb))
431 return PTR_ERR(common->clk_apb);
432
433 common->clk_smi = devm_clk_get(dev, "smi");
434 if (IS_ERR(common->clk_smi))
435 return PTR_ERR(common->clk_smi);
436
437 if (common->plat->has_gals) {
438 common->clk_gals0 = devm_clk_get(dev, "gals0");
439 if (IS_ERR(common->clk_gals0))
440 return PTR_ERR(common->clk_gals0);
441
442 common->clk_gals1 = devm_clk_get(dev, "gals1");
443 if (IS_ERR(common->clk_gals1))
444 return PTR_ERR(common->clk_gals1);
445 }
446
447 /*
448 * for mtk smi gen 1, we need to get the ao(always on) base to config
449 * m4u port, and we need to enable the aync clock for transform the smi
450 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
451 * base.
452 */
453 if (common->plat->gen == MTK_SMI_GEN1) {
454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455 common->smi_ao_base = devm_ioremap_resource(dev, res);
456 if (IS_ERR(common->smi_ao_base))
457 return PTR_ERR(common->smi_ao_base);
458
459 common->clk_async = devm_clk_get(dev, "async");
460 if (IS_ERR(common->clk_async))
461 return PTR_ERR(common->clk_async);
462
463 ret = clk_prepare_enable(common->clk_async);
464 if (ret)
465 return ret;
466 } else {
467 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
468 common->base = devm_ioremap_resource(dev, res);
469 if (IS_ERR(common->base))
470 return PTR_ERR(common->base);
471 }
472 pm_runtime_enable(dev);
473 platform_set_drvdata(pdev, common);
474 return 0;
475}
476
477static int mtk_smi_common_remove(struct platform_device *pdev)
478{
479 pm_runtime_disable(&pdev->dev);
480 return 0;
481}
482
483static int __maybe_unused mtk_smi_common_resume(struct device *dev)
484{
485 struct mtk_smi *common = dev_get_drvdata(dev);
486 u32 bus_sel = common->plat->bus_sel;
487 int ret;
488
489 ret = mtk_smi_clk_enable(common);
490 if (ret) {
491 dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
492 return ret;
493 }
494
495 if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
496 writel(bus_sel, common->base + SMI_BUS_SEL);
497 return 0;
498}
499
500static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
501{
502 struct mtk_smi *common = dev_get_drvdata(dev);
503
504 mtk_smi_clk_disable(common);
505 return 0;
506}
507
508static const struct dev_pm_ops smi_common_pm_ops = {
509 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
510};
511
512static struct platform_driver mtk_smi_common_driver = {
513 .probe = mtk_smi_common_probe,
514 .remove = mtk_smi_common_remove,
515 .driver = {
516 .name = "mtk-smi-common",
517 .of_match_table = mtk_smi_common_of_ids,
518 .pm = &smi_common_pm_ops,
519 }
520};
521
522static int __init mtk_smi_init(void)
523{
524 int ret;
525
526 ret = platform_driver_register(&mtk_smi_common_driver);
527 if (ret != 0) {
528 pr_err("Failed to register SMI driver\n");
529 return ret;
530 }
531
532 ret = platform_driver_register(&mtk_smi_larb_driver);
533 if (ret != 0) {
534 pr_err("Failed to register SMI-LARB driver\n");
535 goto err_unreg_smi;
536 }
537 return ret;
538
539err_unreg_smi:
540 platform_driver_unregister(&mtk_smi_common_driver);
541 return ret;
542}
543
544module_init(mtk_smi_init);